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 [Search a list of Patent Appplications for class 438]   CLASS 438,SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS
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SECTION I - CLASS DEFINITION

A. This class provides for manufacturing a semiconductor containing a solid-state device by a combination of operations wherein:

(1) no other class provides for the overall combination, and

(2) the intent is to use the electrical properties of the semiconductor in the device for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.

B. This class provides for a species of Class 427 operations involving:

(1) coating a substrate with a semiconductive material, or

(2) coating a semiconductive substrate or substrate containing a semiconductive region;

wherein the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.

C. This class provides for a species of Class 216 operations involving etching a semiconductive substrate or etching a substrate containing a semiconductive region, wherein the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes:

(1) conducting or modifying an electrical current,

(2) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or

(3) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.

D. This class provides for packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor, when not elsewhere provided, wherein there are:

(1) multiple operations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor, or support (e.g., mounting, housing, lead frame, discrete heat sink, etc.),

(2) multiple operations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or

(3) a step of treating an already packaged semiconductor substrate (e.g., coating, etching, etc.); if the following conditions are also met: (a) there is significant semiconductor chip structure (e.g., such as recited semiconductor junction, etc.) or named semiconductor device (e.g., DRAM, CMOS, EPROM, etc.), or (b) there is no significant semiconductor structure if also combined with a coating operation of this class (see B above) or etching operation of this class (see C above), and (c) the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes: (i) conducting or modifying an electrical current, (ii) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (iii) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy;

(1) Note. When Class 438 coating (see B above) or etching operations (see C above) are not included, Class 29, following historical precedence, provides for processes of mounting, packaging, molding, or encapsulating of semiconductors having no significant semiconductor chip structure (e.g., merely recited as semiconductor chip, per se, etc.) when not elsewhere provided. E. This is the generic class for operations not elsewhere provided for treating a semiconductive substrate or substrate containing a semiconductive region; wherein the intent is to use the semiconductor in a solid-state device for at least one of the following purposes: (1) conducting or modifying an electrical current, (2) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (3) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.
(1) Note. Lacking an indication that the semiconducting material is to be used for a purpose other than (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy; it will be assumed that the process meets the Class 438 definition.
(2) Note. For this class certain materials will be considered to be semiconductors even if there is no other indication that semiconducting properties are present. Thus, if the criteria set forth under the (1) Note is met that there is no indication that the material is to be used for a purpose other than (a), (b), or (c), the following materials are to be considered semiconductive: silicon, germanium, selenium, tellurium, gallium nitride, gallium phosphide, gallium arsenide, aluminum phosphide, aluminum arsenide, and mercury cadmium telluride.

SECTION II - LINES WITH OTHER CLASSES AND WITHIN THIS CLASS

Several classes provide for plural step operations for manufacturing semiconductor solid-state devices or components therefor. Combined operations for manufacturing semiconductor electrical devices or semiconductor-based components therefor having plural steps not encompassed by another class are proper for Class 438.

For example, while plural steps acceptable to Class 264 (e.g., injection molding and subsequent removal of flash, etc.) remain in Class 264, combinations of molding and adhesive bonding are provided for in Class 156, even though this involves multiple steps, one of which (i.e., molding) would be considered a Class 264 unit operation even if semiconductor material is involved. However, combinations of molding, adhesive bonding, and a Class 438 unit operation acting on a semiconductor substrate which is used for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy, are considered proper for Class 438.

A. UNIT COATING OPERATIONS, COMBINED OPERATIONS INVOLVING COATING, AND PARTICLE BOMBARDMENT

The following search notes are intended to clarify the lines and distinctions for determining when coating operations are provided for in Class 438. Throughout this class, the term "coating" is used in the generic sense to include both surface coating and impregnation.

The unit coating operations in Class 438 may be viewed as a specie of a Class 427 process which was removed intact from Class 427 and transferred to Class 438 for the convenience of the searcher. Thus, plural step operations that were acceptable in Class 427 are now acceptable in Class 438 if the criteria for the semiconductor material as set forth hereinabove is met. Coating operations which do not meet the Class 438 definition may be classified in the classes identified in References to Other Classes, below.

B. UNIT ETCHING OPERATIONS AND COMBINED ETCHING OPERATIONS IN CLASS 438

In References to Other Classes, below, are search notes are intended to clarify the lines and distinctions for determining when an etching unit operation is provided for in Class 438. Throughout this class, the term "etching" is used in the generic sense to include the removal of a surface by chemical reaction or solvent action regardless of the composition thereof.

The unit etching operations in Class 438 may be viewed as a specie of a Class 216 process which was removed intact from Class 216 and transferred to Class 438 for the convenience of the searcher. Thus, plural step operations that were acceptable in Class 216 are now acceptable in Class 438 if the criteria for the semiconductor material as set forth hereinabove is met. Etching operations which do not meet the Class 438 definition may be found in References with Other Classes, below.

C. PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR

Packaging is a semiconductor art manufacturing term for integration, assembly, or surrounding of a semiconductive substrate (e.g., chip, die, etc.) with a permanent encasement, housing, capsule, or support. This is distinguished from package making found in Class 53 which is directed to preparing a manufactured product for passage through the channels of trade in a safe, convenient, and attractive condition, usually wrapped in a cover or in a container which is intended to be removed when the manufactured product is used.

Class 438 takes the following packaging or packaging related operations, if not elsewhere provided: (a) multiple operations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor, or support (e.g., mounting, housing, lead frame, discrete heat sink, etc.), (b) multiple operations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already packaged semiconductor substrate (e.g., coating, etching, etc.).

However, other manufacturing classes have established historic lines with Class 438 that must be considered when determining proper placement. These lines with external classes revolve around such concepts as: whether there is significant semiconductor device structure, whether there is a unit operation or a so-called "multi-step" operation, etc. The search notes in References to Other Classes, below, are intended to clarify these established lines and to alert the searcher to other classes for related searches.

D. LINE NOTES TO OTHER MANUFACTURING OPERATIONS

See References to Other Classes, below for lines clarifying the relationship of other chemical classes to Class 438. For many of the chemical classes, inclusion of metal casting, working or deforming, or fusion bonding step is not acceptable if combined with an operation of the chemical class.

E. LOCATION OF SEMICONDUCTOR COMPOUND, COMPOSITION, OR STOCK

Class 438 does not provide for compound, composition, or stock material produced or utilized by a Class 438 process. A process of manufacture or use of a compound or composition is usually classified with the compound or composition. The process of manufacturing a semiconductor compound or composition and the formation of a semiconductor device or semiconductor junction takes combined operations to Class 438.

Also see References to Other Classes, below, identifying this section.

F. LINE TO HEATING CLASSES

This class (438), will take the process of (a) heating of semiconductor material to modify the microstructure or electrical properties thereof, (b) combined operations involving heating of semiconductor material to modify the semiconductor structure or electrical properties when not provided in another class, or (c) heating of semiconductor substrates that affects only the nonsemiconductor region of the substrate when combined with other operations acceptable to Class 438 or combined with the establishment of device structure (e.g., connects, insulating regions, electrodes, etc.).

See References to Other Classes, below, identified as heating classes.

G. LINE NOTES TO ELECTRICAL CLASSES

See References to Other Classes, below.

SECTION III - REFERENCES TO OTHER CLASSES

SEE OR SEARCH CLASS:

29Metal Working,   especially subclasses 729+ for electrical device manufacturing apparatus, subclasses 829+ for the assembly of electrical components to an insulative base having a conductive path applied thereto, or formed thereon or therein (e.g., a printed circuit board). [See "Packaging (e.g., With Mounting, Encapsulating, etc.)" above]
(1) Note. When Class 438 coating (see "Unit Coating Operations, Combined Operations Involving Coating" above,) or etching operations (see "Unit Etching Operations And Combined Etching Operations") are not included, Class 29, subclasses 825+, following historical precedence, provides for processes of mounting, packaging, molding, or encapsulating of semiconductors having no significant semiconductor chip structure (e.g., merely recited as semiconductor chip, per se, etc.) when not elsewhere provided. If there is no significant chip structure, Class 29 takes as original (a) adhesive bonding combined with specified metal shaping steps or (b) adhesive bonding combined with mechanical joining, either broad or specific.
(2) Note. Multistep processes for packaging semiconductors having no significant semiconductor chip structure are proper for Class 156 when they claim: (a) adhesive bonding combined with shaping of nonmetals; (b) adhesive bonding combined with broad or nominally claimed metal shaping steps; or (c) adhesive bonding including steps for assembling the parts to be bonded are proper in Class 156.
53Package Making,   for passage through the channels of trade in a safe, convenient, and attractive condition, usually wrapped in a cover or in a container. In this context of trade, Class 53 provides for methods of: (a) encompassing, encasing, or completely surrounding goods or materials with a cover made from sheet stock, (b) partially encasing or surrounding goods and materials by a partial cover made from sheet stock, (c) assembling or securing a separate closure to an aperture of a preformed receptacle to complete encasement of contents, (d) depositing articles and arranging fluent materials in preformed receptacles, (e) partial or complete shaping of a cover about an article, and other related package making processes. (See "Packaging (E.g., With Mounting, Encapsulating, Etc.)" above)
(1) Note: If it cannot be perceived (a) whether the process is package making or (b) whether the process is manufacturing of a semiconductor device within or attached to a container, case, lead frame, heat sink, or enclosure as an integral part of the manufactured product; placement goes to Class 438 and Class 53 may be cross-referenced.
65Glass Manufacturing,   for processes of melting, shaping or forming, joining, or heat treating of glass. Glass is defined in the Class 65 definitions (Glossary) as an inorganic material generally including a glass former and having specific characteristics provided in the definition. Included in Class 65 is joining, per se, of glass to metal or glass. (See "Packaging (e.g., With Mounting, Encapsulating, etc.)" above)
(1) Note. Class 438 takes packaging or the packaging-related operation of semiconductor devices when glass melting, glass shaping, glass forming, or glass heat treating is combined with any coating, adhesive bonding, metal casting, metal working, or deforming, metal fusion bonding or other chemical manufacturing operation.
65Glass Manufacturing,   for processes of melting, shaping or forming, joining, or heat treating of glass. Glass is defined in the Class 65 definitions (Glossary) as an inorganic material generally including a glass former and having specific characteristics provided in the definition. It is noted that both silica and elemental silicon are also included for Class 65. Thus, melting, shaping, or fusion bonding of silicon dioxide, per se, or silicon, per se, is also considered proper for Class 65. Class 65 also takes combined operations whether preparatory or subsequent to the melting, shaping or forming, joining or heat treating of glass. Included in Class 65 is joining, per se, of glass to metal, spinning, per se, of glass fibers or joining through glass melting, per se, of glass fibers to substrates such as semiconductor substrates. (see "Line Notes To Other Manufacturing Operations," above)
(1) Note. Class 438, as the exception, takes the combination of Class 438 unit coating operation or Class 438 unit etching operation with glass melting, shaping or forming, joining, or heat treating. Moreover, Class 438 also takes the heat treating, per se, of Class 438 semiconductor material if for purposes of modifying the electrical properties thereof. Class 438 takes the mounting or packaging operation of semiconductor devices when glass melting, glass shaping, glass forming, or glass heat treating is combined with any coating, adhesive bonding, metal casting, metal working, or deforming, metal fusion bonding or other chemical manufacturing operation.
106Compositions: Coating or Plastic,   subclasses 1.05+ for metal-deposition or substrate-sensitizing compositions; subclasses 286.1+ for inorganic materials only containing at least one metal atom; subclass 286.8 for inorganic materials only; subclasses 287.1+ for silicon containing other than solely as silicon dioxide as a part of an aluminum-containing compound, and subclasses 400+ for materials or ingredients. (see "Location Of Semiconductor Compound, Composition, Or Stock" above.)
117Single-Crystal, Oriented-Crystal, and Epitaxy Growth Processes; Non-Coating Apparatus Therefore,   for processes of single crystal growth of semiconductor material upon a seed or substrate and perfecting operations combined therewith. See Class 117 definitions for examples of perfecting operations generally acceptable to Class 117. See particularly Class 117, Class Definition, (2) Note, Keywords and (3) Note, Indicative Terminology, for terms indicative of single crystal formation. Inclusion of a nonperfecting single crystal forming operation on a semiconductor substrate or producing a semiconductor product meeting the hereinabove requirements of a semiconductor material or the definition of a semiconductor substrate takes the original to Class 438, even if there is present a single crystal forming step. (Coating operation not meeting Class 438 definition)
(1) Note. When combined with single crystal formation, the following operations are acceptable in Class 438: (a) simultaneous formation of nonsingle crystalline regions intended to impart structure that will serve as a functional part of the semiconductive substrate or completed device, (b) prior or subsequent removal of a nonseed portion of the substrate in order to impart electrical device structure to the same (e.g., formation or a recess, trench, trough, ridge, mesa, stripe, etc.), or (c) prior or subsequent step acting to alter the composition of the semiconductor substrate so as to impart electrical device structure to the same.
134Cleaning and Liquid Contact With Solids,   especially subclass 1.2 and 1.3 for processes for cleaning a semiconductor substrate including the application of electrical or wave energy to the substrate. (Etching operation not meeting the Class 438 definition)
(1) Note. If the undesirable material to be removed from the semiconductor substrate resides other than on the surface thereof, the process is to be considered gettering of the substrate and thus is proper for Class 438.
148Metal Treatment,   for unit coating operations on metal, particularly subclasses 206+ wherein there is carburization or nitriding of a metal surface by chemical reaction or diffusion of an externally supplied source of carbon or nitrogen that reacts with the metal surface wherein the metal substrate remains as part of the coating and subclasses 240+wherein there is reactive coating of a metal substrate with an external reactant (e.g., oxygen, etc.) wherein the metal substrate remains as part of the coating. Class 148 also takes heat treatment of metallic compositions if during the heat treatment there is either a change in the internal physical structure (i.e., microstructure) or chemical properties. (Coating operation not meeting Class 438 definition)
(1) Note. Since in certain instances metallic compositions could be semiconductor material meeting the Class 438 criteria, placement will go to Class 438 over Class 148 if the material is identified or perceived as semiconductor material. If perceived, a mandatory cross is made in Class 148.
(2) Note. Reactive coating, per se, of a metal (i.e., not intended to be semiconductive) area on a semiconductive substrate (i.e., meeting the Class definition of semiconductor substrate in the Glossary) is original in Class 438. A mandatory cross is made in Class 148 if the only step is reactive coating of a metal portion of a semiconductive containing substrate.
(3) Note. Combination of Class 148 heat treatment of a metal substrate to modify or maintain the chemical property or microstructure of the metal with (a) additional manufacturing of semiconductor device structure or (b) with a Class 438 coating or etching operation takes the original to Class 438.
148Metal Treatment,   subclasses 33.1+ for semiconductor stock which must be essentially homogeneous and have at least two contiguous layers differing in the number of unbound electrons and/or differing in energy gap levels, which exhibit a junction between the layers. (see "Location of Semiconductor Compound, Composition, or Stock" above.)
148Metal Treatment,   for processes of heat treating metals. Class 148 takes heat treatment of metallic compositions if during the heat treatment there is either a change in the internal physical structure (i.e., microstructure) or chemical properties. Since in certain instances metallic compositions could be semiconductor material meeting the Class 438 criteria, placement will go to Class 438 over Class 148 if the material is identified or perceived as semiconductor material. If perceived, a mandatory cross is made in Class 148. (heating class)
156Adhesive Bonding and Miscellaneous Chemical Manufacture,   subclasses 60 through 338for processes of adhesively bonding and subclasses 701-719 and 930-932 for processes of delaminating, per se, while retaining identity as semiconductive. Multistep processes for packaging semiconductors having no significant semiconductor chip structure are proper for Class 156 when claiming (a) adhesive bonding combined with shaping of nonmetals, (b) adhesive bonding combined with broad or nominally claimed metal-shaping steps, or (c) adhesive bonding including steps for assembling the parts to be bonded. An adhesive bonding unit operation for packaging or mounting operations on semiconductor devices goes as original to Class 156. Adhesive bonding combined with Class 438 coating of a semiconductor substrate or Class 438 etching of a semiconductor substrate places the original in Class 438. (See Packaging (e.g., With Mounting, Encapsulating, etc.) above).
174Electricity: Conductors and Insulators,   subclasses 15.1 through 16.3for fluid cooling of electrical conductors or insulator, subclasses 50-64 for housings with electric devices or mounting means, and subclasses 250-268 for printed circuit devices.
204Chemistry: Electrical and Wave Energy,   particularly subclasses 192.1 through 192.37for sputter coating operations involving semiconductor material or substrates including a semiconductor region, even if the intent is to use the semiconductor material for (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy - Class 204 will take combinations of sputter coating with other chemical treating operations that involve (a) preparatory treatment of the substrate (e.g., etching, cleaning, etc.) or (b) subsequent perfecting treatment of the applied coating with the following exception noted (coating operation not meeting Class 438 definition); and subclasses 192.32-192.37, for sputter etching operations on semiconductor material and semiconductor containing substrates, even if the semiconductor is intended for electrical purposes - simultaneous sputter etching and chemical etching (e.g., as when utilizing a mixture of argon and halide gas, etc.) go as original in Class 204 (etching operation not meeting the Class 438 definition).
(1) Note. Creation of semiconductor structure (e.g., semiconductor active region, semiconductor junction, etc.) by subsequent treatment steps, even if limited to the Class 204 applied coating, will go to Class 438. Any subsequent operation that affects the substrate is not provided in Class 204 and is proper in Class 438. However, heat treatment of the Class 204 coating that causes interdiffusion limited to the interfacial region to perfect the bonding of the coating to the substrate is proper for Class 204.
(2) Note. Creation of semiconductor structure (e.g., semiconductor active region, semiconductor junction, etc.) by steps subsequent to sputter etching will go to Class 438.
205Electrolysis: Processes, Compositions Used Therein, and Methods of Preparing the Compositions,   particularly subclass 123 , 124, and 157 for electrolytic coating operations on semiconductor or semiconductor devices (coating operation not meeting Class 438 definition), subclasses 334-639 for electrolytic synthesis of material, such as silicon, by passing an electrical current through a fused material, and subclass 656 for electrolytic erosion of a workpiece of non-uniform internal electrical characteristics (etching operation not meeting the Class 438 definition). Class 205 will take combinations of electrolytic coating with other chemical treating operations that involve (a) preparatory treatment of the substrate (e.g., etching, cleaning, etc.) or (b) subsequent perfecting treatment of the applied coating with the following exception noted (coating operation not meeting Class 438 definition).
216Etching a Substrate: Processes,   for chemical etching processes and perfecting operations therefor, including lithos:graphic steps, of semiconductor material that is to be utilized for nonelectrical properties. (Etching operation not meeting the Class 438 definition)
(1) Note. This class provides for a species of Class 216 operations involving etching a semiconductive substrate or etching a substrate containing a semiconductive region; wherein the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.
(2) Note. Generic claims with a sole claimed specie of etching for Class 216 goes as original to Class 216. Generic claims with a sole disclosed specie of etching for Class 438 goes as original in Class 438. Generic claims with plural claimed etching specie wherein at least one of the claimed species does not belong in Class 438 goes as original in Class 216. Generic claims with plural disclosed etching specie one of which does not belong in Class 438 goes to Class 216 as original. Generic claims with no material specie claimed or disclosed goes as original in Class 216. When there is no generic claim and plural separately claimed etching specie, wherein at least one claim of which is Class 216 and one claim of which is Class 438, placement goes as original to Class 438 with a mandatory cross-reference to Class 216.
219Electric Heating,   subclasses 78.01+ for a process and apparatus for bonding by electrical current and pressure, and appropriate subclasses for electric heating of material, per se. However, inclusion of the criteria for Class 438 as set forth hereinabove takes the original to Class 438 even when electric heating is involved. (heating class)
228Metal Fusion Bonding,   appropriate subclasses for a process of fusion bonding and additional operations which are considered to be ancillary to the bonding (preheating, positioning, pretinning, etc.) of a semiconductive substrate; especially note subclass 123.1 and 179.1+. [See "Packaging (e.g., With Mounting, Encapsulating, etc.)" above]
250Radiant energy,   for methods not elsewhere provided of (a) using, generating, controlling, or detecting radiant energy, (b) combinations including such methods, and (c) subcombinations thereof. Particularly, see subclasses 492.2+ for processes of irradiation of semiconductor devices with no indication as to what occurs to the substrate. Class 250, subclasses 492.2+, generally relates to processes of exposing substrates to ion bombardment utilizing apparatus of Class 250 when limited to operating the apparatus in apparatus terms. Class 250 is also the generic home for processes of exposing substrates to ion bombardment. However, Class 438 provides for ion implantation of semiconductive substrate or substrate containing a semiconductive region and also ion implantation throughout the material mass to produce semiconductive material or to modify the semiconductive material. (Coating operation not meeting Class 438 definition)
250Radiant Energy,   for methods not elsewhere provided, of (a) using, generating, controlling, or detecting radiant energy, (b) combinations including such methods, and (c) subcombinations thereof. Particularly, see subclasses 492.2+ for processes of irradiation of semiconductor devices with no indication as to what occurs to the substrate. Class 250 subclasses 492.2+, generally relates to processes of exposing substrates to ion bombardment utilizing apparatus of Class 250 when limited to operating the apparatus in apparatus terms. Class 250 is also the generic home for processes of exposing substrates to ion bombardment. However, Class 438 takes chemically reactive ion etching of semiconductive substrate or substrate containing semiconductive region. (Etching operation not meeting the Class 438 definition)
250Radiant Energy,   for heating invisible radiant energy; subject matter of Class 438, per se, when no function other than heating is attributed to the process and for methods not elsewhere provided, of (a) using, generating, controlling, or detecting radiant energy, (b) combinations including such methods, and (c) subcombinations thereof. Particularly, see subclasses 492.2+ for processes of ion bombardment or irradiation of semiconductor devices, with no indication as to what occurs to the substrate. (heating class)
252Compositions,   for (a) subclasses 62.3+ for semiconductor compositions which have been uniformly doped or otherwise specialized for use as one layer which when combined with another such layer would provide an interface exhibiting barrier layer properties (e.g., as exists in Class 148, subclasses 33 through 33.6, stock wherein there is a semiconductor junction, etc.) and (b) subclasses 500+ for electrical conductive compositions. Also see the cross-reference art collection in Class 252, subclasses 950+, for doping agent source materials. (see "Location Of Semiconductor Compound, Composition, Or Stock" above.)
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   for active solid-state electronic device structure, per se. Subject matter may include one or more such devices combined with contacts or leads, or structures configured to be tested on a semiconductor chip, or merely semiconductor material without contacts or leads where the sole disclosed use is an active solid-state device. This subject matter does not include active solid-state devices combined with significant circuits. (electrical class)
264Plastic and Nonmetallic Article Shaping or Treating: Processes,   for a process (and steps perfecting same) of forming a composite by shaping a plastic or nonmetallic wherein a semiconducting containing preform is within a mold during the shaping operation (e.g., encapsulating, etc.). (See "Packaging (e.g., With Mounting, Encapsulating, etc.)" above)
361Electricity: Electrical Systems and Devices,   subclasses 679.01 through 679.61for housing and mounting assemblies for electronic devices and components, and subclasses 736+ and 752+ for modules for printed circuits or housing or chassis for printed circuit boards. (electrical class).
376Induced Nuclear Reactions: Processes, Systems, and Elements,   particularly subclass 183 for a process of neutron bombardment, per se, of semiconductive material containing an element which is converted to a desired dopant by nuclear transmutation. Any combination of operations that goes beyond formation of the transmutated doped semiconductor material, per se, goes as original to Class 438 if it meets the criteria of the intent to use the electrical properties of the semiconductor in a solid-state device as set forth by the Class 438 definition. (Coating operation not meeting Class 438 definition)
376Induced Nuclear Reactions: Processes, Systems, and Elements,   subclasses 320+ for the direct conversion of the energy produced in a nuclear reaction into an electrical output by a one-step process or apparatus for accomplishing such a one-step process. (electrical class)
378X-ray or Gamma Ray Systems or Devices,   especially subclasses 34+ for X-ray or gamma-ray lithography. (electrical class)
382Image Analysis,   especially subclass 145 for a process limited to image analysis per se in manufacturing of an integrated circuit. However, inclusion of subject matter for Class 438 remains with Class 438 even if there is a step of image analysis.
385Optical Waveguides,   particularly, subclass 14 for a laser in integrated optical circuit, subclasses 129+ for a planar optical waveguide, and subclasses 141+ for a waveguide having a particular optical characteristic modifying chemical composition. The (13) Note of Class 385 indicates that miscellaneous manufacturing of optical wave guide devices not elsewhere provided are in Class 385. Thus, if the manufactured article is a semiconductor device, a Class 438 process controls over the Class 385 process even if an optical fiber is part of the device. (electrical class)
420Alloys or Metallic Composition,   for alloys or metallic compositions that may also exhibit semiconductor properties (e.g., gallium arsenide, etc.). (see "Location Of Semiconductor Compound, Composition, Or Stock" above.)
423Chemistry of Inorganic Compounds,   appropriate subclasses for inorganic compounds or elements used in the manufacture of semiconductor devices. (see "Location of Semiconductor Compound, Composition, or Stock" above.)
427Coating Processes,   for coating operations provided for in that class, particularly subclasses 457+ for a process of treating a coating with radiant energy; subclasses 487+ for polymerization of applied coating utilizing direct application of electrical, magnetic, wave, or particulate energy; subclasses 523+ for ion plating or ion implanting; subclasses 532+ for pretreatment of a substrate or posttreatment of a coated substrate utilizing electrical, magnetic, wave, or particulate energy; subclasses 569+ for deposition coating processes utilizing plasma; subclasses 580+ for deposition coating processes utilizing electrical discharge; subclass 581 for coating processes utilizing chemical liquid deposition; subclass 582 for coating processes utilizing photo-initiated chemical vapor deposition; subclasses 585+ for coating processes utilizing chemical vapor deposition; subclass 591 for deposition coating utilizing induction or dielectric heating; subclasses 592+ for deposition coating utilizing resistance heating; subclasses 595+ for deposition coating utilizing electromagnetic or particulate radiation; subclasses 598+ for deposition coating utilizing magnetic field or force; subclass 600 for deposition coating utilizing sonic or ultrasonic energy. (Coating operation not meeting Class 438 definition)
(1) Note. Class 438 provides for a specie of Class 427 operations involving (a) coating a substrate with a semiconductive material or (b) coating a semiconductive substrate or substrate containing a semiconductive region; and wherein the intent is to use the electrical properties of the semiconductor in a solid state device for at least one of the following purposes: (i) conducting or modifying an electrical current, (ii) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (iii) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.
(2) Note. Generic claims with a sole claimed specie of coating for Class 438 goes as original to Class 438. Generic claims with a sole disclosed specie of coating for Class 438 goes as original in Class 438. Generic claims with plural claimed coating species wherein at least one of the claimed species does not belong in Class 438 goes as original in Class 427. Generic claims with plural disclosed coating species one of which does not belong in Class 438 goes to Class 427 as original. Generic claims with no material species claimed or disclosed goes as original in Class 427. When there is no generic claim and plural separately claimed coating specie, wherein at least one claim of which is Class 427 and one claim of which is Class 438, placement goes as original to Class 438 with a mandatory cross-reference to 427.
428Stock Material or Miscellaneous Articles,   appropriate subclasses for semiconductor stock material defined in terms of composition and structure, especially subclass 620 . (see "Location of Semiconductor Compound, Composition, or Stock" above.)
429Chemistry: Electrical Current Producing Apparatus, Product, and Process,   especially subclass 7 for a combination including a nonbattery electrical component electrically connected within a cell casing other than testing or indicating components. (electrical class)
430Radiation Imagery Chemistry: Process, Composition, or Product Thereof,   particularly for initial lithos:graphic processes in semiconductor manufacture limited to (a) exposure imaging and developing and including preparatory operations to the exposure (e.g., as coating to form the resist, etc.) or (b) developing, per se, of subject matter of Class 430 substrates. When Class 430 exposure, imaging or developing are combined with etching or coating of a semiconductor substrate for purposes other than masking and commensurate with the Class 438 definition for manufacture of a semiconductor device as set forth hereinabove, the combination goes as original to Class 438 with the following exception noted. (Coating operation not meeting Class 438 definition)
(1) Note. Since Class 430 provides for processes of (a) coating, per se, of substrates, with a composition to produce a product to be used for electric or magnetic imagery and (b) processes of coating, per se, of substrate with a photosensitive composition for use in radiation imagery, coating or etching of semiconductor material limited to forming a product intended to be used for electric, magnetic, or radiation imagery is original in Class 430.
(2) Note. Although technically classifiable as an original in Class 438 according to the above paragraph, any multistep process involving significant Class 430 operations as a subcombination of the overall process should be cross-referenced to Class 430.
430Radiation Imagery Chemistry: Process, Composition, or Product Thereof,   particularly for initial lithos:graphic processes in semiconductor manufacture limited to (a) exposure imaging and developing and including preparatory operations to the exposure (e.g., as coating to form the resist, etc.) or (b) developing, per se, of subject matter of Class 430 substrates. When Class 430 exposure imaging or developing are combined with etching or coating of a semiconductor substrate commensurate with the Class 438 definition for manufacture of a semiconductor device as set forth hereinabove, the combination goes as original to Class 438 with the following exception noted. (Etching operation not meeting the Class 438 definition)
(1) Note. Since Class 430 provides for processes of (a) coating, per se, of substrates, with a composition to produce a product to be used for electric or magnetic imagery and (b) processes of coating per se of substrate with a photosensitive composition for use in radiation imagery, coating or etching of semiconductor material limited to forming a product intended to be used for electric, magnetic, or radiation imagery is original in Class 430.
(2) Note. Although technically classifiable as an original in Class 438 according to the above paragraph, any multistep process involving significant Class 430 operations as a subcombination of the overall process should be cross-referenced to Class 430.
432Heating, for generic heating processes. However,   inclusion of the criteria for Class 438 as set forth hereinabove takes the original to Class 438 even when generic heating is involved. (heating class)
439Electrical Connectors,   appropriate subclasses for features related or analogous to electrical contact or housing features of active solid-state devices (e.g., subclasses 271+ for sealing elements or subclasses 449+ for stress relief means for conductor to terminal joint. (electrical class)
501Compositions: Ceramic,   appropriate subclasses for ceramic compositions used in semiconductor devices. (see "Location of Semiconductor Compound, Composition, or Stock" above.)
505Superconductor Technology: Apparatus, Material, Process,   particularly subclass 330 for processes of manufacturing from high temperature (i.e., above 30 degrees Kelvin) superconductive material (a) superconductor devices or (b) semiconductor devices having superconductive components or connect lines. (see "Line Notes To Other Manufacturing Operations," above)

SECTION IV - GLOSSARY

Listed below are: (1) a compilation of acronyms, abbreviations, and technological terms pertaining to solid-state electrical devices, manufacturing processes, and related apparatus and compositions useful therefor and (2) the meaning to be given to the various "art" terms appearing in this class. These latter terms, some of which have been included in the glossary below, are the same as that generally accepted or in common usage. However, certain terms employed in this class and also included below have been assigned definitions which may be more restrictive or different from those in common usage since these terms are being utilized for distinguishing this class over other classes of related art.

a-Si

Amorphous silicon

ACT

Acoustic charge transport

ADC

Analog-to-digital converter

AES

Auger electron spectroscopy

ALE

Atomic layer epitaxy

ALEP

Angle-lapping edge profilometry

AMD

Active matrix display

AMG

Alternative-metal, virtual-ground (metallization)

APCVD

Atmospheric-pressure CVD

APD

Avalanche photodiode

ARC

antireflective coating

ASG

Arsenosilicate glass

BBCO

Barium bismuth copper oxide (a HTSC)

BBD

Bucket brigade device

BBL

Buried bit-line

BED

Band edge discontinuity

BH

Buried heterostructure

BHF

Buffered hydrofluoric acid

BIC

Breakdown of insulator for conduction

BICFET

Bipolar inversion channel FET

BiCMOS

Integrated bipolar and CMOS

BiMOS

Integrated bipolar and MOSFET

BJT

Bipolar junction transistor

BKBO

Barium potassium bismuth oxide (a HTSC)

BLM

Ball limiting metallization

BMD

Bulk micro defect

BOE

Buffered oxide etch

BOX

Buried oxide

BOXES

Buried oxide with etch stop

BPSG

Borophosphosilica glass

BPTEOS

borophosphoTEOS

BSD

Back side damage

BSE

buried storage electrode

BSG

Borosilica glass

BSQ

Bias sputter quartz

BST

Barium strontium titanate

CAIBE

Chemically assisted ion beam etching

CBIC

Complementary bipolar IC

CBKR

Cross bridge Kelvin resistor (test structure)

CCB

Controlled collapse bonding

CCC

Corrugated capacitor cell

CCD

Charge coupled device

CDE

Chemical dry etching

CDI

Collector diffusion isolation

CEL

Contrast enhancement layer

CER

Contact end resistor (test structure)

CERDIP

ceramic DIP

chanstop

channel stop isolation structure

CHEMFET

Chemically sensitive FET

CHL

Current hugging logic

CID

Charge injection device

CLSEG

Confined lateral SEG

CML

Current mode logic (i.e., ECL)

CMOS

Complementary (NMOS and PMOS) FETs

CMP

chemical-mechanical polishing/planarization

COB

(a) chip-on-board or (b) capacitor over bit-line

COD

Catastrophic optical damage

COG

Chip-on-glass

COMFET

Conductivity modulation FET (i.e., IGBT)

CSBH

Channeled substrate buried heterostructure

CSL

Coherent superlattice

CTD

Charge transfer device

CTSL

Coherent tilted superlattice

CVD

Chemical vapor deposition

Cz

Czoshralski (melt pulling)

DADBS

diacetoxyditertiarybutoxysilane

DADIS

diacetoxydiisopropoxysilane

DBR

distributed Bragg reflector

DCG

dichromated gelatin

DCFL

direct-coupled FET logic

DCS

dichlorosilane

DDE

double diffused epitaxy

DDI

deep dielectric isolation

DEIS

dual electron injection structure

DEZ

diethylzinc

DFB

distributed feedback (laser)

DH

double-hetero

DHBT

double-hetero bipolar transistor

DHF

dilute hydrofluoric acid

DI

dielectric isolation

DIBL

drain induced barrier lowering

DIET

dielectrically encapsulated trench capacitor

DIP

dual-in-line package

DLP

double layer polysilicon

DLTS

deep level transient spectroscopy

DMAH

dimethylaluminumhydride

DMD

(a) depletion mode device (also D-mode or D-type) or (b) deformable mirror device

DMOS

double diffused MOS

DMS

dilute magnetic semiconductor

DOES

doublehetero optoelectronic switch

DRAM

dynamic random-access memory

DSP

double stacked capacitor

DTL

diode-transistor logic

DUF

diffusion under film

DUT

device under test

DUV

deep ultraviolet

DZ

denuded zone

-E-

EAROM

electrically alterable read-only memory

EB

(a) extrinsic base or (b) electron beam

EBES

electron beam exposure system

EBIC

electron beam induced current

EBL

electron beam lithography

ECL

emitter coupled logic

ECR

electron cyclotron resonance

EDP

ethylene-diamine-pyrocatechol etchant

EDTA

ethylenediaminotetraacetic acid

EELS

electron energy loss spectroscopy

EEPROM

electrically erasable programmable read-only memory

EFG

edge-defined film-fed growth (also EDFFG or EDFG)

EG

extrinsic gettering

EGSi

electronic-grade silicon

EL

electroluminescent

ELO

epitaxial lateral overgrowth

EMD

enhancement mode device (also E-mode or E-type)

EMI

electromagnetic interference

EMP

electron microprobe

EPB

epoxidated polybutadiene (an EB resist)

EPD

etch pit density

EPI

epitaxial (single crystalline) layer

EPP

ethylene-piperidine-pyrocatechol etchant

EPR

electron paramagnetic resonance

EPROM

erasable programmable read-only memory

EPS

effective punchthrough stopper

EPW

etchant mix of ethylenediamine, pyrocatechol, and water

ESCA

electron spectroscopy for chemical analysis

ESD

electrostatic discharge

ESR

(a) equivalent series resistance or (b) electron spin resonance

FAMOS

floating-gate avalanche-injection MOS

FASIC

folded bit-line adaptive sidewall isol. capacitor cell

FCT

field controlled thyristor

FEC

floating electrode capacitor

FED

field emission device

FET

field effect transistor

FIB

focused ion beam

FIPOS

full isolation by porous oxidized silicon

FLOTOX

floating gate tunnel oxide

FOX

field oxide

FPD

field programmable device

FPGA

field programmable gate array

FTIR

Fourier transform infrared spectroscopy

FUROX

fully recessed oxide isolation

GDMS

glow discharge mass spectroscopy

GILD

gas immersion laser doping

GRIN-SCH

graded index separate confinement heterostructure

GTO

gate turn-off

HBT

heterojunction bipolar transistor

HDC

high dielectric constant

HDI

high density interconnects

HDMI

high density multilayer interconnects

HEMT

high electron mobility transistor (Hetero MESFET)

HET

hot electron transistor (bipolar)

Hi-C

high capacitance

HIC

hybrid integrated circuit

HIMOS

(see COMFET)

HIPOX

high pressure oxidation

HMDS

hexamethyldisilizane

HNA

hetchant mix of hydrofluoric, nitric, and acetic acids

HPSC

half-Vccsheath plate capacitor

HTO

high temperature oxide

HTSC

high temperature superconductor

IB

(a) intrinsic base or (b) ion beam

IBD

ion beam deposition

IC

integrated circuit

ICP

inductively coupled plasma

IG

intrinsic gettering

IGBT

insulated gate bipolar transistor (e.g., COMFET, HIMOS)

IGFET

insulated gate field effect transistor

IID

impurity induced disordering

I2L

integrated injection logic

IJP

ink jet printhead

ILB

inner lead bonding

ILD

interlayer dielectric

IMMA

ion microprobe mass analysis

IMPATT

impact ionization avalanche transist time (diode)

INS

intrinsic nondoped semiconductor

IR

infrared

ISFET

ion sensitive FET (i.e., CHEMFET)

ITO

indium tin oxide (a TCO)

IVEC

isolation vertical capacitor cell

JFET

junction field effect transistor (junction gate)

JOFET

Josephson junction field effect transistor

JTE

junction termination extension

KMER

Kodak metal etch resist

KPR

Kodak photo resist

KTFR

Kodak thin film resist

LAGB

low-angle grain boundary

LATID

large angle tilt implant drain

LB

(a) Langmuir-Blodgett or (b) laser beam

LCCD

leadless ceramic chip carrier

LCD

liquid crystal display

LDCC

leaded ceramic chip carrier

LDD

lightly doped drain

LEC

liquid encapsulated Czoshralski

LED

light emitting diode

LEED

low-energy electron diffraction

LEK

liquid encapsulated Kyropoulus

LOCOS

local oxidation of silicon

LOPED

lift-off using edge detection

LPCVD

low-pressure chemical vapor deposition

LPE

liquid phase epitaxy

LRP

limited reaction processing

LSI

large scale integration

LSSL

lateral surface superlattice

LST

logic service terminal

LTCC

low temperature co-fired ceramic

LTG

low temperature growth

LTO

low temperature oxidation

MBE

molecular beam epitaxy

MCz

magnetic Czoshralski

MCM

multichip module

MCT

(a) MOS controlled thyristor or (b) HgCdTe

MEM

micro-electromechanical

MESFET

metal semiconductor FET (Schottky gate)

MF3R

modified fully-framed fully-recessed isolation

MGSi

metallurgical-grade silicon

MIM

metal-insulator-metal

MISFET

metal insulator semiconductor IGFET

MLEC

magnetic LEC

MLC

multilayer ceramic

MLO

multilayer oxide

MLR

multilayer resist

MMA

methyl methacrylate

MMIC

monolithic microwave integrated circuit

MNOS

metal nitride/oxide IGFET

MOCVD

metal organic chemical vapor deposition

MODFET

modulation doped MESFET (i.e., HEMT)

MOMOM

metal-oxide-metal (tunnelling device)

MOSFET

metal oxide semiconductor IGFET

MQW

multiquantum well

MTF

mean time to failure

MTL

merged transistor logic (i.e., I2L)

NDC

negative differential conductivity

NEA

negative electron affinity (e-emitter)

NMA

N-methyl-acetamide

NMOS

n-channel MOSFET

NMP

n-methyl-pyrrolidone

novolak

Thermoplastic phenol-formaldehyde used as photoresist

NPN

(bipolar transistor)

NRD

nitridation retarded diffusion

NSAG

nonself-aligned gate

NTD

neutron transmutation doping

NVRAM

nonvolatile RAM

OBG

optical band gap

ODE

orientation dependent etching

OED

oxidation enhanced diffusion

OEIC

optoelectronic integrated circuit

OF

orientation flat

OISF

oxidation induced stacking fault

OMCVD

organometallic CVD

OMCT

octamethylcyclotetrasiloxane

OMVPE

organometallic VPE

ORD

oxidation retarded diffusion

ORL

optical return loss

OSA

optical subassembly

OSF

(see OISF)

OTCR

over-the-cell routing

OTP

one-time programmable

OXSEF

oxygen-doped silicon epitaxial film

PAC

photoactive compound

PAP

peel apart

PBG

photonic band gap

PBL

polybuffered LOCOS

PBM

planarization blocking mask

PBN

pyrolytic boron nitride

PBT

permeable base transistor

PCB

printed circuit board

PCE

photoconductive element

PEB

postexposure baking

PECVD

plasma enhanced chemical vapor deposition

PEP

photo-engraving process

PFT

peeled film technology

PGA

(a) pin-grid array or (b) programmable gate array

PGMA

poly(glycidyl methacrylate) (an EB resist)

PHS

plated heat sink

PIC

photonic integrated circuit

PID

programmable interconnect device (fuse/antifuse)

PIN

P-type layer, intrinsic layer, N-type layer

PIQ

thermosetting polyimide resin

PLA

programmable logic array

PLCC

plastic leaded chip carrier

PLDD

profiled LDD

PLM

pad limiting metallurgy

PLZT

lead lanthanate zirconate titanate

PMMA

polymethylmethacrylate

PMOS

p-channel MOSFET

PNP

(bipolar transistor)

polycide

polycrystalline silicide

polySi

polycrystalline silicon

PPL

poly pad LOCOS

PR

photoresist

PROM

programmable read only memory

PROPS

planarization with resist/oxide and polysilicon

PSD

photosensitive diode or dielectric

PSG

phosphosilica glass

PTC

positive temperature coefficient

PTH

plated through-hole

PUT

programmable unijunction transistor

PVD

physical vapor deposition

PWB

printed wiring board

PZT

lead zirconate titanate

QE

quantum efficiency

QFP

quad flat package

QUIP

quad-in-line package

QW

quantum well

QWIP

quantum well infrared photodetector

RAM

random access memory

RBS

Rutherford backscattering

RBT

resonant tunneling bipolar transistor

RCT

reverse conducting thyristor

RED

radiation enhanced diffusion

resurf

reduced surface field

RETT

resonant electron transfer triode

RF

radiofrequency

RHEED

reflected high energy electron diffraction

RHET

resonant tunneling hot electron transistor (bipolar)

RIBE

reactive ion beam etching

RIE

reactive ion etching

RISC

reduced instruction set computing

RMS

refined metallurgical silicon

ROI

recessed oxide isolation

ROM

read only memory

ROX

recessed oxide

RTA

rapid thermal anneal

RTP

rapid thermal processing

salicide

self-aligned silicide

SAG

self-aligned gate

SAW

surface acoustic wave (pressure sensitive device)

SBD

Schottky barrier diode

SBH

Schottky barrier height

SBS

silicon bilateral switch

SCCM

standard cubic centimeter per minute

SCM

single chip module

SCR

silicon controlled rectifier

SDFL

Schottky diode FET logic

SDHT

selectively doped heterostructure transistor (e.g., HEMT)

S-DIP

shrink DIP

SEED

self-enhanced electro-optical devices

SEG

selective epitaxial growth

SEL

(a)surface emitting laser or (b)state excitation by light

SELFOX

selective epitaxial layer field oxidation

SEM

scanning electron microscopy

SEOT

self-aligned epitaxy over trench

SEPOX

selective polysilicon oxidation

SER

soft error rate

SFFT

superconducting flux flow transistor

SGT

surrounding gate transistor

Si

silicon

SI

semi-insulating

SICOS

sidewall base contact structure

SILO

sealed interface local oxidation

SIMOX

separation by implanted oxygen

SIMS

secondary ion mass spectrometry

SIP

single-in-line package

SIPOS

semi-insulating polycrystalline oxygen-doped silicon

SIT

(a)static induct. thyristor or (b)static induct. trans.

SLM

spatial light modulator

SLS

strained layer superlattice

SLT

solid logic technology

SMT

surface mount technology

SOG

spin-on glass

SOI

silicon on insulator

SOIC

small outline IC package

SOJ

small outline J-lead package

SOS

silicon on sapphire

SPE

solid phase epitaxy

SPOT

self-aligned planar oxidation technology

SPT

substrate plate trench capacitor

SQUID

superconductive quantum interference device

SRAM

static random access memory

SRO

stress relief oxide

SSDP

simultaneous single/polycrystalline deposition

SSI

small scale integration

SST

(a)super self-alignment tech. or (b)sealed sidewall tech.

STT

stacked transistor capacitor cell

SUBHET

superconducting base hot electron transistor

SUBSIT

superconducting base semiconductor isolated transistor

SWAMI

sidewall masked isolation

TAB

tape automated bonding

TAT

turn around time

TBES

tritertiarybutoxyethoxysilane

TBCO

thallium bismuth copper oxide (a HTSC)

TCE

trichloroethylene

TCM

thermal conduction module

TCO

transparent conductive oxide

TDDB

time dependent dielectric breakdown

TEC

thermoelectric cooler

TED

transient enhanced diffusion

TEG

(a) triethylgallium or (b) test element group

TEM

transmission electron spectroscopy

TEOS

tetraethylorthosilane

TFR

thin film resistor

TFT

thin film transistor

TGZM

temperature gradient zone melting

TH

through-hole

TIBA

triisobutylaluminum

TLTR

transmission line tap resistor (test structure)

TMA

(a) trimethylaluminum or (b) trimethylantimony

TMAH

tetramethyl ammoniumhydroxide

TMAT

tetramethylamidotitanium

TMB

tetramethylborate

TMCTS

tetramethylcyclotetrasiloxane

TMG

trimethylgallium

TMOS

tetramethyloxysilane

TMP

trimethylphosphine

TMS

tetramethylsilane

TMT

tetramethyltin

TOFER

topos:graphic feature enhancement by RIE

TPF

thermoplastic film

TRAPPAT

trapped plasma avalanche tunnel transit (diode)

TSD

temperature sensing diode

TSOP

thin small outline package

TTL

transistor-transistor logic

UHV

ultrahigh vacuum

UV

ultraviolet

VCNR

voltage controlled negative resistance

VGF

vertical gradient freeze (also VFG)

VHSIC

very high speed integrated circuit

VLE

vapor levitation epitaxy

VLSI

very large scale integration

VMOS

vertical MOS

VPE

vapor phase epitaxy

VSIS

V-channel substrate inner stripe

WSI

wafer scale integration

XRD

x-ray diffraction

YBCO

yttria barium copper oxide (a HTSC)

YSZ

yttria stabilized zirconia

ZDO

zero drain overlap

ZIP

zigzag-in-line package

ZMR

zone melt recrystallization

mc

microcrystalline

p

high resistivity intrinsic semiconductor

ACCEPTOR IMPURITY

An atom or ion different from or foreign to, but present in, a semiconductor material and which has insufficient valence electrons to complete the normal bonding arrangement in the semiconductor crystal structure. An acceptor impurity (also referred to as p-type) accepts an electron from an adjacent atom to create a positive charge carrier (i.e., a hole). A donor impurity (also referred to as n-type) provides an electron to the conduction band of the semiconductor.

ACTIVE SOLID-STATE DEVICE

An electronic device or component that is primarily made up of solid materials, usually semiconductors, which operates by the movement of charge carriers - electrons or holes - which undergo energy level changes within the material and can modify an input voltage to achieve rectification, amplification, or switching action. Active solid-state electronic devices include diodes, transistors, thyristors, etc., but exclude pure resistors, capacitors, inductors, or combinations solely thereof. The latter category is characterized as passive.

ALLOY JUNCTION

A fused junction produced by combining one or more elemental impurity metals with a semiconductor. Typical alloyed junctions include indium-germanium and aluminum-silicon.

AUTODOPING

The introduction via the vapor phase of impurities from an existing substrate region (and adjacent supports, e.g., susceptors, etc.) into another substrate region, typically during growth of the same.

AVALANCHE BREAKDOWN

A sudden change from high dynamic electrical resistance to very low dynamic resistance in a reverse biased semiconductor device (e.g., a reverse biased junction between p-type and n-type semiconductor materials) wherein current carriers are created by electrons or holes which have gained sufficient speed to dislodge valence electrons. Avalanche breakdown can cause structural damage to a semiconductor device.

BAND GAP

The difference between the energy levels of electrons bound to their nuclei (valence electrons) and the energy levels that allow electrons to migrate freely (conduction electrons). The band gap depends on the particular semiconductor involved.

BARRIER REGION OR LAYER

A region which extends on both sides of a semiconductor junction in which all carriers are swept away from the junction region. The region is depleted of carriers. This is also referred to as a depletion region. Not to be confused with diffusion barrier layers associated with metallization schemes for active solid state devices.

BINARY COMPOUND

A substance that always contains the same two elements in a fixed atomic ratio.

BIPOLAR

An active solid-state electronic device in which both positive and negative current carriers are used to support current flow.

BIPOLAR TRANSISTOR

An active solid-state electronic device with a base electrode and two or more junction electrodes in which both positive and negative current carriers are used to support current flow.

BIRD"S BEAK

The lateral encroachment of the localized oxidation region associated with a recessed oxide isolation structure.

BONDING PAD

A metallized area to which an external electrical connection is to be made.

BREAKDOWN

A sudden change from high dynamic electrical resistance to a very low dynamic resistance in a reverse biased semiconductor device (e.g., a reverse biased junction between p-type and n-type semiconductor materials) wherein reverse current increases rapidly for a small increase in reverse applied voltage, and the device behaves as if it had negative electrical resistance.

CAPACITOR

A component used in electrical and electronic circuits which stores a charge of electricity, usually for very brief periods of time, with the ability to rapidly charge and discharge. A capacitor is usually considered a passive component since it does not rectify, amplify, or switch and because charge carriers do not undergo energy level changes therein, although some active solid state devices function as voltage variable capacitors.

CHANNEL

A path for conducting current between a source and drain of a field effect transistor.

CHANNEL STOP

Means for limiting channel formation in a semiconductor device by surrounding the affected area with a ring of highly doped, low resistivity semiconductor material. In a field effect transistor, it is a region of highly doped material of the same type as the lightly doped substrate used to prevent leakage paths along the chip surface from developing. Also referred to as "chanstop."

CHANNEL PINCH-OFF REGION

The location in a current channel portion of a field effect transistor (FET) where the current is reduced to a minimum value due to its diameter being reduced to a minimum.

CHARGE CARRIER

A mobile conduction electron or hole in a semiconductor.

CHARGE CONFINEMENT

Restriction of electrical charge carriers (e.g., electrons or holes) to specified locations (e.g., by quantum wells, gate electrode potentials, etc.).

CHARGE INJECTION DEVICE

A field effect device in which storage sites for packets of electric charge are induced at or below the surface of an active solid-state device by an electric field applied to the device and wherein carrier potential energy per unit charge minima are established at a given storage site and such charge packets are injected into the device substrate or into a data bus. This type device differs from a charge transfer device in that, in the latter, charge is transferred to adjacent charge storage sites in a serial manner, whereas, in a charge injection device, the charge is injected in a nonserial manner to the device substrate or to a data bus.

CHIP

A single crystal substrate of semiconductor material on which one or more active or passive solid-state electronic devices are formed. A chip may contain an integrated circuit. A chip is not normally ready for use until packaged and provided with external connectors.

CHIP CARRIER

A package with terminals, for solid-state electronic devices, including chips which facilitates handling of the chip during assembly of the chip to other electronic elements.

CLADDING BARRIER

A higher band gap material which encases a lower band gap material that defines the walls of a quantum well.

COHERENCE LENGTH

The typical distance an electron can travel before it is scattered (e.g., by a phonon, a defect, or an impurity, etc.).

COHERER

A term which encompasses both active and passive type devices, the passive type being a resistor whose resistance decreases when subjected to a high frequency signal, and the active type being a rectifier which is made up of active solid-state particles which conduct and rectify current when connected into a cohesive element but which loses that characteristic when the particles are separated (e.g., by shaking a container in which the particles are located, etc.).

COLLECTOR DIFFUSION ISOLATION (CDI)

An electrical isolation technology used for bipolar devices which employs an epitaxial layer, which forms transistor base regions, laid on a substrate of the same conductivity type (p or n) as the epitaxial layer, with an opposite conductivity type region, more heavily doped than the epitaxial base layer and located between the layer and the substrate, forming the collector and isolating the transistor from the substrate.

COMPOUND SEMICONDUCTOR

A semiconductor composed of a chemical compound formed of elements from two or more different groups of the chemical periodic chart (e.g., Group III (B, Al, Ga, In) and Group V (N, P, As, Sb) for the following compounds: AlP, AlAs, AlSb, GaP, GaAs, GaSb, InP, InAs, and InSb, or a compound of silicon and carbon (SiC)).

CONDUCTION BAND

A partially filled energy band in which electrons can move freely, permitting a material to carry electric current where electrons are the current carriers.

CONDUCTION ELECTRONS

In a conductor or n-type semiconductor, outer shell electrons that are bound so loosely that they can move freely in the conduction band of a solid material under the influence of an electric field.

CONNECTOR AREA

That portion of the electrical conductors (e.g., bonding pad, die bond, etc.) used for providing external electrical connections from a component to a chip or other component.

CONTACT

The point or part of a conductor which touches another electrical conductor or electrical component to carry electrical current to or from the conductor or electrical component.

CRYSTAL DEFECT

Any nonuniformity in a crystal lattice. There are four categories of crystal defects: (a) point defects, (b) line defects, (c) area defects, and (d) volume defects. Point defects include any foreign atom at a regular lattice site (i.e., substitutional site) or between lattice sites (i.e., interstitial site), antisite defects in compound semiconductors (e.g., Ga in As or As in Ga), missing lattice atoms, and host atoms located between lattice sites and adjacent to a vacant site (i.e., Frenkel defects). Line defects, also called edge or screw dislocations, include extra planes of atoms in a lattice. Area defects include twins or twinning (i.e., a change in crystal orientation across a lattice) and grain boundaries (i.e., a transition between crystals having no particular positional orientation to one another). Volume defects include precipitates of impurity or dopant atoms caused by volume mismatch between a host lattice and precipitates.

DEEP DEPLETION

The condition in which a depletion layer formed in a MOS active device due to voltage applied to the gate electrode of the device is deeper than the maximum depth at which inversion would normally be expected to occur at room temperature in a semiconductor device at the surface closest to the gate electrode, without formation of an inversion layer.

DEEP LEVEL CENTERS

Energy levels that can act as traps located in the forbidden band of a semiconductor material that are not near the conduction or valence band edges.

DEGENERATION

Doping of a semiconductor to such an extent that the Fermi level lies within the conduction band (i.e., N+ semiconductor) or within the valence band (i.e., P+ semiconductor). Also, in circuit applications, negative feedback between two or more active solid-state devices.

DEPLETION MODE

The operation of a field effect transistor having appreciable channel conductivity for zero gate-source voltage and whose channel conductivity may be increased or decreased according to the polarity of the applied gate-source voltage, by changing the gate-to-source voltage from zero to a finite value, resulting in a decrease in the magnitude of the drain current.

DEPLETION REGION

The region extending on both sides of a reverse biased semiconductor junction in which free carriers are removed from the vicinity of the junction. It is also called a space charge region, a barrier region, or an intrinsic semiconductor region.

DEVICE (ACTIVE)

The physical realization of an individual electrical element in a physically independent body which cannot be further divided without destroying its stated function. Examples are transistors, pnpn structures, and tunnel diodes.

DIE

A tiny piece of semiconductor material, separated from a semiconductor slice, on which one or more active electronic components are formed. Sometimes called a chip.

DIE BOND

Attachment of a semiconductor chip to a substrate or chip carrier or package, usually with an epoxy, eutectic, or solder alloy.

DIFFUSED JUNCTION

A junction between two different conductivity regions within a semiconductor and which is formed by diffusion of appropriate impurity atoms into the material.

DIFFUSION BARRIER

An obstacle to the diffusion of atoms in a metallization scheme for an active solid-state device.

DIODE ISOLATION

A technique in which a high electrical resistance between an integrated circuit element and its substrate is achieved by surrounding the element with a reverse biased pn junction.

DIP (DUAL IN-LINE PACKAGE)

A chip carrier or package consisting of a plastic or ceramic body with two rows of vertical leads in which a semiconductor integrated circuit is assembled and sealed. The leads are typically inserted into a circuit board and secured by soldering.

DIRECT BAND GAP SEMICONDUCTOR

A semiconductor in which an electron transition from the conduction to the valence band, or vice versa, does not require a change in crystal momentum for electrons. Gallium arsenide is an example of a direct band gap semiconductor.

DISORDERED

Crystalline arrangement in which the different constituent atoms of a compound semiconductor randomly occupy lattice sites.

DISLOCATION

A line defect in a crystal, either of the edge type or screw type, in which the atoms are not arranged in a perfect latticelike structure. See CRYSTAL DEFECT for other examples of crystalline defects.

DMOSFET

Depletion-type metal oxide semiconductor field effect transistor. Such devices are normally in the on condition with no applied gate voltage.

DONOR IMPURITY

An element which when added to a semiconductor provides unbound or free electrons to the semiconductor which may serve as current carriers. Typically, donors are atoms which have more valence electrons than the atoms of the semiconductor material into which they are introduced in small quantities as an impurity or dopant. Since such donor impurities have more valence electrons than the semiconductor, a semiconductor doped with donor impurities is an n-type semiconductor.

DOPANT

An impurity added from an external source to a material by diffusion, coating, or implanting into a substrate, such as changing the properties thereof. In semiconductor technology, an impurity may be added to a semiconductor to modify its electrical properties or to a material to produce a semiconductor having desired electrical properties. N-type (negative) dopants (e.g., such as phosphorus for a group IV semiconductor) typically come from group V of the periodic table. When added to a semiconductor, n-type dopants create a material that contains conduction electrons. P-type (positive) dopants (e.g., such as boron for a group IV semiconductor) typically come from group III and result in conduction holes (i.e., vacancies in the electron shells).

DOPING OF SEMICONDUCTOR

Adding controlled amounts of conductivity modifying material, referred to as electrically active dopant or impurity, to a semiconductor material or to a material to produce a semiconductor having desired electrical properties for this class.

DOPING PROFILE

The point to point concentration throughout a semiconductor of an impurity atom doped into the semiconductor.

DOUBLE-DIFFUSED MOS (DMOS)

A metal oxide semiconductor having diffused junctions in which successive diffusions of different impurity types are made in the same well-defined region of the semiconductor.

DRAIN

The electrode of a field effect transistor which receives charge carriers which pass through the transistor channel from the source electrode.

DUAL GUARD-BAND ISOLATION

A type of electrical isolation of functional elements of an integrated circuit comprised of two distinct unused areas of chip surface area adjacent to the elements desired to be electrically isolated.

DYNAMIC RANDOM ACCESS MEMORY (DRAM)

Solid-state memory in which the information decays over time and needs to be periodically refreshed.

ELECTROMIGRATION

Mass transport of ions (i.e., usually metal) in a material as a response to the passage of current through the material by momentum exchange between thermally activated ions and conduction electrons.

ELECTRON-HOLE PAIR

A positive charge carrier (i.e., hole) and a negative charge carrier (i.e., electron) considered together as being created or destroyed as part of one and the same event.

ENHANCEMENT MODE

The operation of a field effect transistor which has a channel formed therein between its source and drain regions and which normally does not conduct current through its channel with zero voltage applied to its gate electrode. Voltage of the correct polarity will accumulate minority carriers in the channel to permit conduction of current in the channel, thus turning on the transistor.

EPITAXIAL LATERAL OVERGROWTH

Process of epitaxial deposition through an exposed opening in an insulating layer with deposition continuing epitaxially over the insulating layer laterally from the opening.

EPITAXY

The controlled growth of a single crystal of one material on the surface of a crystal of the material (i.e., homo) or onto another substance (i.e., hetero) so that the crystal lattice of the base material controls the orientation of the atoms in the grown single crystal layer.

ESAKI DIODE

A heavily doped pn-junction diode where conduction occurs through the junction potential barrier due to a quantum mechanical effect even though the carriers which tunnel through the potential barrier do not have enough energy to overcome the potential barrier. Esaki tunneling involves a tunneling barrier formed by a macroscopic depletion layer between n-type and p-type regions. It does not involve a resonant tunneling barrier using controlled quantum confinement, a layer located between junctions, nor a thin superlattice layer.

EXTRINSIC SEMICONDUCTOR

A semiconductor whose charge carrier concentration and, therefore, electrical properties depend on impurity atoms introduced therein.

FACE BONDED

A chip mounting technique wherein semiconductor chips are provided with small mounting pads, turned face down, and bonded directly to conductors on a substrate.

FIELD EFFECT TRANSISTOR (FET)

A unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electric field applied to the semiconductor from a control electrode. There are two main types of FETs, a junction FET and an insulated-gate FET. In the junction FET, the gate is isolated from the channel by a pn-junction. In an insulated-gate FET, the gate is isolated from the channel by an insulating layer so that the gate and channel form a capacitor with the insulating layer as the capacitor dielectric.

FIELD OXIDE

A thin (on a macroscopic scale) film made of an oxide of a material which overlies a device substrate to reduce parasitic capacitive coupling between conductors overlying the oxide and the substrate or devices below the oxide layer (e.g., in the substrate). See bird"s beak.

FLIP-CHIP

A term which describes the situation wherein a semiconductor device which has all terminations on one side thereof in the form of bump contacts, has a passivated surface, and has been flipped over and attached to a matching substrate.

FLOATING DIFFUSION

A region of a semiconductor device in which impurity atoms have been doped and which is electrically floating, that is, has no direct electrical connection.

FLOATING GATE

A gate electrode that is electrically floating, that is, has no direct electrical connection.

FORBIDDEN ENERGY BAND

The energy band of a material which is located between a solid material"s conduction and valence bands. It is defined by the amount of energy that is needed to release an electron from its valence band to its conduction band. Electrons cannot exist in this gap. They are either below it, and bound to an atom, or above it, and able to move freely.

FRAME TRANSFER CCD

A charge coupled device area imager array with a separate image area, storage area, and read-out register area, the storage area being located between the image area and the readout area. This is distinguished from an interline- transfer CCD in which the sensing and storage/readout function areas are located next to each other.

GATE

The control electrode or control region that exerts an effect on a semiconductive region directly associated therewith, such that the conductivity characteristic of the semiconductor region is altered in a temporary manner, often resulting in an on-off type switching action. The control electrode or control region of a field effect transistor is located between the source and drain electrodes, and regions thereof.

GATE ARRAY

A repeating geometric arrangement of groups of active solid-state devices, each group being connectable into a logic circuit, in one integrated, monolithic semiconductor chip.

GATE CONTROLLED DIODE

A three terminal semiconductor diode with the ability to be turned on or off by a pulse applied to its gate electrode.

GETTERING

The elimination or reduction of unwanted constituents (i.e., impurities) or defects from a substrate.

GRAPHOEPITAXY

The growth of a single crystalline layer across the surface of a nonsingle crystalline substrate by commencing growth at a seeding portion/region thereof.

GUNN DIODE

A diode in which electrons under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the conduction band of the active semiconductor device material or holes under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the valence band of the active semiconductor device material. A Gunn diode does not normally have a pn junction and cannot be used as a rectifier.

GUNN EFFECT

An intervalley transfer effect wherein electrons under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the conduction band of the active semiconductor device material, or holes under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the valence band of the active semiconductor device material.

HALL EFFECT DEVICE

An active solid-state device in which a current is flowing and is in a magnetic field perpendicular to the current, and in which a voltage is produced that is perpendicular to both the current flow direction and the magnetic field direction.

HETEROJUNCTION/HETEROINTERFACE

An interface between two dissimilar semiconductor materials. For example, one material may by InAs and the other may be InAlAs, or one material may be GaAs and the other material may be GaAlAs.

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

A heterojunction field effect transistor with impurity ions located on the side of the heterojunction with lower affinity for the charge carriers (holes or electrons) injected at the source that pass to the drain via a channel adjacent the heterojunction.

HOLE

An empty energy level in the valence band of a semiconductor crystal which exhibits properties of a real particle and can act as a mobile positive-charge carrier.

HOMOJUNCTION

An interface between regions of opposite polarity in the same semiconductor material.

HOT CARRIER DIODE

A diode in which electrons (or holes) have energies greater than those that are in thermal equilibrium with the material of at least one of the regions forming the diode. Schottky barrier diodes typically have "hot carriers" (hot electrons) injected into the metal from the semiconductor.

HYBRID CIRCUIT

A small printed circuit having miniature components which may include passive components (resistors, capacitors, and inductors) deposited on a printed circuit board.

IMPURITY

A foreign material present in a semiconductor crystal, such as boron or arsenic in silicon, which is added to the semiconductor to produce either p-type or n-type semiconductor material, or to otherwise result in material whose electrical characteristics depend on the impurity dopant atoms.

INDIRECT BAND GAP SEMICONDUCTOR

A semiconductor material in which a change in semiconductor crystal momentum for an electron is required when it moves from the conduction band to the valence band and vice versa. Silicon and aluminum arsenide are examples of indirect band gap semiconductors.

INSULATED-GATE FIELD EFFECT TRANSISTOR (IGFET)

A unipolar transistor with source, gate, and drain regions and electrodes, in which conduction takes place in a channel controlled by action of the voltage applied to the gate electrode of the device, in which the gate electrode is separated from the channel by an insulator layer.

INSULATOR

A material which has a high resistance to the flow of electric current. It has such low electrical conductivity that the flow of current therethrough can usually be neglected.

INTRINSIC CONCENTRATION

The number of minority carriers in a semiconductor due to thermal generation of electron-hole pairs.

INVERSION

A condition in a semiconductor material in which the concentration of minority carriers exceeds the concentration of majority carriers.

INVERSION LAYER/CHANNEL

A region in a semiconductor material in which the concentration of minority carriers exceeds the concentration of majority carriers.

ISOELECTRONIC

A condition in which two constituents have the same number of valence electrons.

ISOLATION

The separation or surrounding of active semiconductor regions or components with electrically insulative regions to prevent the flow of electrical current between the active semiconductor regions or between electronic component parts of a solid-state electronic device.

ISOPLANAR CMOS

A semiconductor device in which relatively thick regions of silicon dioxide, recessed into the semiconductor surface, are used to electrically isolate device areas and prevent parasitic device formation. More commonly called LOCOS CMOS.

ISOPLANAR ISOLATION

A type of electric isolation in which relatively thick regions of silicon dioxide, recessed into the semiconductor surface, are used to electrically isolate device areas and prevent parasitic device formation. More commonly called LOCOS ISOLATION.

JUNCTION BARRIER

The opposition to the diffusion of majority carriers across a pn junction due to the charge of the fixed donor and acceptor ions.

JUNCTION CAPACITANCE

The capacitance across a pn junction. It depends on the width of the depletion layer, which increases with increased reverse bias voltage across the junction.

JUNCTION ISOLATION

Electrical isolation of devices on a monolithic integrated circuit chip using a reverse biased junction diode to establish a depletion layer that forms the electrical isolation between devices.

JUNCTION RESISTANCE

The electrical resistance across a semiconductor PN junction.

LAND

The conductive areas, normally metal patterns, on a semiconductor integrated circuit, which form part of the contacts and interconnections between components on the integrated circuit. See bonding pad, die bond.

LIFT-OFF

Process for the removal of unwanted deposited material from a substrate (and thus patterning the same) by the dissolution of an intermediate layer and the commitant physical separation of the overlying deposited material.

LUMINESCENCE

The emission of visible or invisible radiation unaccompanied by high temperature by any substance as a result of absorption of exciting energy in the form of photons, charged particles, or chemical change. It is a general term which includes fluorescence and phosphorescence. Types include hemiluminescence, bioluminescence, photoluminescence, electroluminescence, photoluminescence, and triboluminescence. Active solid-state luminescent devices are semiconductors which operate via injection luminescence. Active devices include pn junctions (including heterojunctions), Schottky barrier junctions, metal-insulator-semiconductor (MIS) structures, and high speed traveling domains (e.g., Gunn domain and acoustoelectric wave generated domains). Passive solid-state electroluminescent devices (phosphors) are insulators which operate in an intrinsic luminescence phenomena (i.e., where an applied electric field generates free carriers) to initiate the light emission mechanism, there being no free carriers in an insulator to be accelerated by an applied field unless the field also generates them.

MAJORITY CARRIER

The predominant charge carrier in a semiconductor. Electrons are majority carriers in n-type semiconductors. Holes are majority carriers in p-type semiconductors.

MASTERSLICE ARRAY/MASTERCHIP

A substrate that contains active and passive electronic components in a predetermined pattern which may be connected into different logic or analog circuits.

MBM JUNCTION

Active solid-state devices having metal-barrier-metal layer junctions.

METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)

See Insulated-gate Field Effect Transistor.

METALLIZATION

Process of coating (a) metal or (b) other material which is identified as having the conductive characteristic of a metal onto a semiconductor or a substrate containing semiconductor regions to form electrodes, contacts, interconnects, bonding pads, or heat sinks and also including formation of conductive material by doping of nonconductive material.

MIM DIODE

A junction diode with a thin insulating layer of material sandwiched between two metallic surface layers which operates as a tunneling (direct or Fowler-Nordheim type) diode.

MINORITY CARRIER

The less predominant charge carrier in a semiconductor. In a p-type semiconductor, minority carriers are electrons, whereas in n-type semiconductor material, minority carriers are holes.

MIS

Acronym for metal-insulator-semiconductor. Typically active solid-state devices with MIS technology have a silicon dioxide layer formed on a single crystal silicon substrate. A polysilicon conductor layer is formed on the oxide.

MOBILITY

The facility with which carriers move through a semiconductor when subjected to an applied electric field. Electrons and holes typically have different mobilities in the same semiconductor.

MODFET

Acronym for a modulation doped field effect transistor. A high speed semiconductor FET in which dopant atoms containing semiconductor layers alternate with nondoped semiconductor layers, so that the carriers (electrons or holes) resulting from the dopant atoms can travel in the undoped material, so that there is little scattering of carriers from dopant atoms. Typically, the dopant atoms are in semiconductor material having a lower carrier affinity than the undoped layers to facilitate carrier spill over into the undoped layers. Such a structure may typically constitute a superlattice. See also High Electron Mobility Transistor.

MONOLITHIC DEVICE (E.G., IC, ETC.)

A device in which all components are fabricated on a single chip of silicon. Interconnections among components are provided by means of metallization patterns on the surface of the chip structure, and the individual parts are not separable from the complete circuit. External connecting wires are taken out to terminal pins or leads.

MSM

Acronym for metal-semiconductor-metal semiconductor device. Active solid-state semiconductor devices having a semiconductor layer sandwiched between two layers of metal and forming back-to-back Schottky diodes.

NEGATIVE RESISTANCE REGION

An operating region of an active solid-state electronic device in which an increase in applied voltage results in a decrease in output current.

NEGATIVE TEMPERATURE COEFFICIENT

The amount of reduction in a device parameter, such as capacitance or resistance, for each degree of device operating temperature.

NMOS

N-channel metal oxide semiconductor devices which use electrons as majority carriers.

NONDOPANT

An impurity added from an external source which does not modify the electrical properties of a semiconductor.

NPN TRANSISTOR

A bipolar transistor with n-type emitter and collector regions separated by a p-type base.

N-CHANNEL FET

A field effect transistor that has an n-type conduction channel.

N-TYPE SEMICONDUCTOR

An extrinsic semiconductor having n-type dopant atoms (e.g., atoms with one or more valence electron than the host atoms). Electron density exceeds hole density.

ORDERED

Crystalline arrangement in which different constituent atoms of a compound semiconductor occupy specific lattice sites resulting in long range regularity of the resultant structure.

OUTDIFFUSION

The solid-state diffusion of impurities from the underlying substrate into a deposited layer during the growth thereof.

PACKAGE

A container, case, or enclosure utilized in the context of semiconductor art for protecting a solid-state electronic device from the environment and which is considered a part of a manufacture product (i.e., as opposed to a package utilized for passage of a product through the channels of trade in a safe, convenient, and attractive condition).

PAD

A. The portion of a conductive pattern on a solid-state electronic device for making external connection thereto. B. The portion of a conductive pattern on a chip or a printed circuit board designed for mounting or attaching a substrate or solid-state active electronic device. See also bonding pad, die bond, etc.

PARASITIC DEVICES/CHANNELS

A. Junctions forming unintended interconnection of intended active solid-state devices. B. Devices which were not designed to carry current flow and which result from unintended interconnection of intended active solid-state devices.

PASSIVE DEVICE

A solid-state electronic device or component in which charge carriers do not change their energy levels and that does not provide rectification, amplification, or switching, but which does react to voltage and current. Examples are pure resistors, capacitors, and inductors.

P-CHANNEL

A conduction path, made of p-type semiconductor material, located between source and drain of a field effect device.

PHOTODIODE

A diode in which charge carriers are created by light which illuminates the diode junction. It is a photovoltaic as well as a photoconductive device.

PINCH-EFFECT RESISTOR

A monolithic integrated circuit resistor having a layer of one conductivity type, typically a P-layer formed at the same time as integrated circuit bipolar transistor base regions, which is thinned by an inset region of opposite conductivity type, typically an N-layer formed at the same time as integrated circuit bipolar transistor emitter regions.

PIN DIODE/DEVICE

A diode having an intrinsic semiconductor (i.e., one with no dopants) sandwiched between a p-type layer and an n-type layer. The depletion region (the intrinsic semiconductor layer) thickness can be tailored to optimize quantum efficiency for use as a photo diode or frequency response for use as a microwave diode.

PIN-GRID ARRAY

A semiconductor chip package having leads in the form of pins arranged in columns and rows.

PLANAR TRANSISTOR

A bipolar transistor in which the emitter base and collector regions terminate at the same plane surface without indentations in or protrusions from the surface. Hence, the emitter and base regions form dish-shaped portions extending into the semiconductor from the common surface.

PN-JUNCTION

The interface and region of transition between p-type and n-type semiconductors. See also barrier layer.

PN-JUNCTION DIODE

A semiconductor device having two terminals connected to opposite-type semiconductor materials with a junction therebetween and exhibiting a nonlinear voltage-current characteristic, usually used for switching or rectification.

PNP TRANSISTOR

A bipolar transistor with p-type emitter and collector regions separated by an n-type base.

POINT DEFECT

A crystal defect occurring at a point in a crystal. Examples include (a) a foreign atom incorporated into the crystal lattice at either a substitutional (regular lattice) site or interstitial (between regular lattice sites) site, (b) a missing atom in the lattice, or (c) a host atom located between regular lattice sites and adjacent to a vacancy (called a Frenkel defect). See CRYSTAL DEFECT for other examples of crystalline defects.

POLYSILICON

A polycrystalline form of silicon.

POTENTIAL BARRIER

The difference in electrical potential across a pn junction in a semiconductor. See also barrier layer.

POTTING

An embedding process in which an electronic component is placed in a can, shell, or other container and buried in a fluid dielectric which subsequently is hardened material. Even though the container is not removed from the finished part, this is considered a molding operation since the fluid is confined to a definite shape during hardening.

PRINTED CIRCUIT BOARD

A structure formed on one or more layers of electrically insulating material having electrical terminals and conductive material deposited thereon, in continuous paths, from terminal to terminal, to form circuits for electronic apparatus such as chips or substrates.

P-TYPE

An extrinsic semiconductor in which the hole density exceeds the conduction electron density.

PUNCHTHROUGH

Expansion of a depletion region* from one junction to another junction in an active solid-state device.

QUANTUM TRANSISTOR

Transistors whose operation is based on the properties of electrons confined in quantum wells - semiconductor films only a hundred or so angstroms thick sandwiched between high confining walls made of a second semiconductor material.

QUANTUM WELL

Semiconductor films only a hundred or so angstroms thick sandwiched between high confining walls made of a second material.

RECOMBINATION

The process by which excess holes and electrons in a semiconductor crystal recombine and no longer function as charge carriers in the semiconductor. Basic recombination processes are band-to-band recombination which occurs when an electron in the conduction band recombines with a hole in the valence band, and trapping recombination which occurs when an electron or hole is captured by a deep energy level, such as produced by a deep level dopant, before recombining with an opposite conductivity-type carrier.

RESISTIVITY

A measure of the resistance of a material to electric current. Resistivity is a bulk material property measured in ohm-cm.

RESONANT TUNNELLING DEVICE

A device that works on the principle of resonant electron (or hole) tunneling through a pair of matched potential barriers. This occurs when the energy of the electrons (or holes) matches that of a quantum energy level in the quantum well formed between the barriers.

SEMICONDUCTOR

A. A generic term for (1) a substance or material whose electronic conductivity at ordinary temperature is intermediate between that of a metal and an insulator and whose conductivity is capable of being modified by the addition of a dopant or (2) an electronic device the main functioning parts are made from semiconductor materials.

B. For the purposes of Class 438, a semiconductor material (1) must have resistivity between that of an insulator and a conductor and (2) be intended for use in a solid state device for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge,or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy. The resistivity is commonly changed by light, heat, or electric or magnetic fields incident on the material.

SEMICONDUCTOR JUNCTION

The region of transition, which usually exhibits asymmetric conductivity, between two joined semiconductors of different electrical properties or of joined semiconductor and conductor (e.g., metal, etc.) and which is also referred to in the art as a barrier layer. Types of junctions include heterojunctions, Schottky barrier junctions, and PN junctions.

SILICON ON INSULATOR (SOI)

A semiconductor structure using an insulating substrate, instead of silicon as a substrate material, with an overlying active layer of single crystal silicon containing active solid state devices. The substrate may typically be of the form of an insulating layer which is itself formed on a single crystal substrate.

SILICON ON SAPPHIRE (SOS) CMOS

A complementary metal oxide semiconductor device (e.g., a transistor) wherein single crystal silicon is grown on a passive insulating base of sapphire (single crystal alpha phase aluminum oxide) with complementary MOS transistors formed in the silicon in one or more island portions.

SINGLE CRYSTAL

A body of material having atoms regularly located at periodic lattice sites throughout.

SINKER

A buried electrically conductive, low resistance path in an integrated circuit which connects an electrical contact to a conductive region buried in the integrated circuit. It may be made up of a heavily doped impurity region.

SOLID-STATE DEVICE

An electronic device or component that uses current flow through solid (as opposed to liquid), gas, or vacuum materials. Solid-state devices may be active or passive.

SOURCE

In a field effect transistor, the active region/electrode to which the source of charge carriers is connected.

SPACE CHARGE REGION

The region around a pn junction in which holes and electrons recombine to leave no mobile charge carriers and a net charge density due to the residual dopant ions.

SPIKING

Phenomena associated with electromigration wherein a fingerlike protrusion of a metallization layer is allowed to grow through a dielectric layer and eventually contact a further layer.

SUBSTRATE

A. A base upon which a coating is formed. See the class definition for the requirements for coating, per se, or etching, per se, when a base of semiconductor or containing a semiconductive region is the substrate. B. The supporting material on or in which the components of an integrated circuit are fabricated or attached.

SUPERLATTICE

A periodic sequence of variations in carrier potential energy in a semiconductor, of such magnitude and spacing that the current carrier wave function is spread out over many periods, so that carrier energy and other properties are determined in part by the periodic variations. The variation may be in chemical composition of the material, as in a sequence of heterojunctions, or in impurity concentration, forming a doping superlattice, or both.

SURFACE MOUNT DEVICES

Active or passive solid-state devices which are structured and configured to be mounted directly to a printed circuit board surface. This type of mounting is distinguished from "through-hole" mounting which involves the electrical and physical connection of devices to a printed circuit board using drilled and plated holes through the conductive pattern of the board.

SURFACE RESISTIVITY

The resistance of a material between two opposite sides of a unit square of its surface. Also called Sheet Resistance. Measured in ohms, often written as "ohms per square" in this case.

THERMISTOR

A thermoelectric device whose electrical resistance varies with temperature. Its temperature coefficient of resistance is high, nonlinear, and usually negative.

THIN-FILM

A material on a substrate with a thickness not greater than 10 microns and uniformity within 20% of it"s average value (Grant and Hackh"s Chemical Dictionary, 5th Edition, edited by Roger & Claire Grant, McGraw-Hill, Inc., 1987, page 235).

THICK-FILM DEVICES

Printed thin-film circuits. Silk screen printing techniques are used to make the desired circuit patterns on a ceramic substrate. Active devices may be added thereto as separate devices (see HYBRID CIRCUIT).

THIN-FILM DEVICES

Solid-state electronic devices which are constructed by depositing films of conducting material on the surface of electrically insulating bases.

THYRISTOR

A four layer p-n-p-n bistable switching device that changes from an off or blocking state to an on or conducting state which uses both electron and hole-type carrier transport.

TRANSFERRED ELECTRON DEVICE

See GUNN EFFECT. In such devices, advantage is taken of the negative differential mobility of electrons or holes in certain semiconducting compounds, particularly GaAs or InP.

TRANSISTOR

An active solid-state semiconductor device having three or more electrodes in which the current flowing between two specified electrodes is modulated by the voltage or current applied to one or more specified electrodes, and is capable of performing switching or amplification. May be of unipolar type (i.e., field effect transistor) or bipolar type.

TRAPATT DEVICE

An acronym for trapped plasma avalanche triggered transit diodes, which are biased into avalanche condition. As the diode breaks down, a highly conducting electron-hole plasma quickly fills the entire n-type region, and the voltage across the diode drops to a low value. The plasma is then extracted from the diode by the low residual electric field, thus causing a large current flow even though the voltage is low. Once extraction of the plasma is completed, the current drops and the voltage rises.

TRENCH ISOLATION

Electrical isolation of electronic components in a monolithic integrated circuit by the use of grooves or other indentations in the surface of the substrate, which may or may not be filled with electrically insulative (i.e., dielectric) material.

TUNNEL DIODE

A semiconductor diode in which the electrons penetrate a quantum barrier that is impenetrable in terms of classical physics, but which is penetrable in terms of quantum physics due to the quantum mechanical uncertainty in position of current carriers.

TWO-DIMENSIONAL ELECTRON GAS

A description of the motion of electrons which are confined in only one direction, such as electrons in the conducting channel of a MOSFET. In an electron gas, the electrons move around without apparent restriction. The behavior of electrons in conducting metals (e.g., copper) is an example of a three-dimensional electron gas. In a two dimensional electron gas, motion is restricted to a single plane (two dimensions). See also MODFET.

UNIPOLAR

An active solid-state electronic device in which only one type of charge carrier (i.e., positive holes or negative electrons) is used to support current flow.

VARACTOR

A semiconductor diode comprising a two terminal active device using the voltage variable capacitance of a pn junction or a Schottky junction that changes capacitance with a change in applied voltage.

VARISTOR

A varistor is a two-electrode active or passive semiconductor device with a voltage dependent nonlinear resistance which falls significantly as the voltage is increased. In an active device, the nonlinear property is due to the presence of one or more potential barriers. In a passive-type varistor, it is due to electrical heating of the material due to current flow therethrough. Varistors are to be contrasted with passive variable resistors such as rheostats or potentiometers.

VIA

A metallized or plated-through hole in an insulating layer, a semiconductor containing substrate or chip, or a printed circuit board which forms a conduction path itself without having a wire or lead inserted therethrough.

WAFER

A thin slice of semiconductor material with parallel faces used as the substrate for active solid-state devices in discrete or monolithic integrated circuit form.

WIRING CHANNEL

An area on an integrated circuit, such as a gate array, which is left free of active devices and in which interconnection metallization patterns are formed.

WORK FUNCTION

The minimum energy required to remove an electron from the Fermi level of a material and liberate it to free space outside the solid.

ZENER DIODE

A single pn junction, two terminal semiconductor diode reversed biased into breakdown caused by the Zener effect (i.e., by field emission of charge carriers in the device"s depletion layer). NOTE: True Zener breakdown occurs in silicon at values below 6 volts. It is to be distinguished from the avalanche breakdown mechanism that occurs in reverse biased diodes at higher (about 6 volts) voltages.

SUBCLASSES

[List of Patents for class 438 subclass 1]    1HAVING BIOMATERIAL COMPONENT OR INTEGRATED WITH LIVING ORGANISM:
 This subclass is indented under the class definition.  Process for making an electrical device utilizing a semiconductor substrate which contains a component identical to material found in a living organism or is integrated with a living organism.

SEE OR SEARCH CLASS:

128Surgery,   for a method of treatment of a living body or organism.
429Chemistry: Electrical Current Producing Apparatus, Product, and Process,   subclass 2 for subject matter under the class definition having living matter (e.g., microorganism, etc.).
  
[List of Patents for class 438 subclass 2]    2HAVING SUPERCONDUCTIVE COMPONENT:
 This subclass is indented under the class definition.  Process for producing an electrical device utilizing a semiconductor substrate having an electrically conductive component which at temperatures of less than or equal to 30K is able to conduct electricity in the absence of resistance.

SEE OR SEARCH CLASS:

29Metal Working,   subclasses 25.01+ for manufacturing a nonsemiconductor-type barrier layer device and subclass 599 for a method of mechanical manufacture of a superconductor electrical device.
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 30+ for an active solid-state device in which the active layer through which carrier tunnelling occurs has a lower conductivity than the material adjacent thereto, especially subclasses 31+ for Josephson junction devices, and subclasses 661+ for a superconductive contact or lead.
331Oscillators,   subclass 107 for superconductive element and tunnelling element oscillators.
427Coating Processes,   subclasses 62+ for a process of coating, per se, wherein the product is a superconductive electrical device.
505Superconductor Technology: Apparatus, Material, Process,   particularly subclass 330 for a process of manufacturing a semiconductor electrical device having a superconductive component possessing an operating temperature greater than 30K and subclass 923 for a process of making a semiconductor electrical device having a superconductive component possessing an operating temperature of less than 30K.
  
[List of Patents for class 438 subclass 3]    3HAVING MAGNETIC OR FERROELECTRIC COMPONENT:
 This subclass is indented under the class definition.  Process for making an electrical device wherein the semiconductor substrate has integral therewith a component with recited magnetic or ferroelectric properties.

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48,for a process of manufacturing an electrical device or circuit utilizing a semiconductor substrate, said device or circuit being responsive to an external magnetic signal.

SEE OR SEARCH CLASS:

257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 295 for an insulated gate field effect transistor having a ferroelectric material layer.
427Coating Processes,   subclasses 127+ for coating a magnetic base or coating a base with a magnetic material.
  
[List of Patents for class 438 subclass 4]    4REPAIR OR RESTORATION:
 This subclass is indented under the class definition.  Process for the renewal, reconstruction, or refurbishment of the previously possessed electrical or mechanical properties of a semiconductor electrical device which have become degraded.
(1) Note. This subclass includes patents to a process of removing and replacing a defective chip from a package as well as a process of repair of defective electrical conduct paths (e.g., wirings).
  
[List of Patents for class 438 subclass 5]    5INCLUDING CONTROL RESPONSIVE TO SENSED CONDITION:
 This subclass is indented under the class definition.  Process including the step of regulating an operation by detecting a characteristic or a change in a characteristic of the process or the semiconductor substrate acted upon and by implementing an action in the process based upon the detected characteristic or change therein.
(1) Note. There must be a positive action carried out in response to the detected characteristic or change therein which furthers the semiconductor substrate toward its subsequent indented utilization. Thus, the removal of defective devices or substrates from a manufacturing process flow (e.g., by sorting, etc.) or the identification of same (e.g., by inking, etc.) is not deemed to be a positive action proper for this subclass.

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209Classifying, Separating, and Assorting Solids,   especially subclasses 552+ for methods sensing a condition of an item and controlling the separation in accordance therewith.
340Communications: Electrical,   for control responsive indicating systems not having structural details, especially subclass 653 for electronic circuit or component and subclasses 657+ for electrical characteristic.
365Static Information Storage and Retrieval,   subclass 201 for testing of memory systems.
377Electrical Pulse Counters, Pulse Dividers or Shift Registers: Circuits and Systems,   subclasses 28+ for error checking of pulse counters.
714Error Detection/Correction and Fault Detection/Recovery,   appropriate subclasses for diagnostic testing, per se, particularly subclasses 100+ for reliability and availability, fault recovery, locating and avoidance, diagnostic testing or monitoring of a digital processing system for reliability purpose.
  
[List of Patents for class 438 subclass 6]    6Interconnecting plural devices on semiconductor substrate:
 This subclass is indented under subclass 5.  Process for electrically connecting multiple electrical devices on a monolithic semiconductive substrate to establish a desired circuit pattern (e.g., wiring, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:

128,for a process of forming an array of electrical devices and selectively interconnecting the devices to produce a desired electrical circuit.
  
[List of Patents for class 438 subclass 7]    7Optical characteristic sensed:
 This subclass is indented under subclass 5.  Process wherein the sensed condition is an optical property of the device or an optical property of the process.
(1) Note. Optical aligning, per se, is not deemed to be a control responsive operation for the purposes of this subclass.

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348Television,   subclasses 86+ for manufacturing wherein a picture signal generator (i.e., television camera) is utilized for monitoring a manufacturing operation.
356Optics: Measuring and Testing,   for optical alignment processes.
382Image Analysis,   for methods for the automated analysis of an image or recognition of a pattern, including measuring significant characteristics of the image or pattern.
  
[List of Patents for class 438 subclass 8]    8Chemical etching:
 This subclass is indented under subclass 7.  Process having a step of chemically etching the semiconductor substrate in conjunction with the sensing of an optical property of the process or of the semiconductor device.
  
[List of Patents for class 438 subclass 9]    9Plasma etching:
 This subclass is indented under subclass 8.  Process wherein the chemical etching step utilizes an ionized chemically reactive gas to etch the semiconductor substrate.
  
[List of Patents for class 438 subclass 10]    10Electrical characteristic sensed:
 This subclass is indented under subclass 5.  Process wherein the sensed condition is an electrical property of the device or an electrical property of the process.

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209Classifying, Separating, and Assorting Solids,   especially subclasses 571+ for methods of electrical testing thereby sensing a property of an item to facilitate subsequent separation.
  
[List of Patents for class 438 subclass 11]    11Utilizing integral test element:
 This subclass is indented under subclass 10.  Process wherein the electrical property is sensed utilizing a specific test structure integral to the semiconductor substrate and which has no other function in the completed device.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 48 for test or calibration structures provided on active solid-state devices to permit or facilitate the measurement, test, or calibration of the characteristics of the devices.
  
[List of Patents for class 438 subclass 12]    12And removal of defect:
 This subclass is indented under subclass 10.  Process wherein a defect detected by the electrical sensing step is thereafter removed.

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4,for a process of repairing or restoring the previously possessed electrical or mechanical properties of a semiconductor electrical device which have become degraded.
  
[List of Patents for class 438 subclass 13]    13Altering electrical property by material removal:
 This subclass is indented under subclass 10.  Process whereby following or as a result of the electrical sensing step, an electrical property of the semiconductor substrate is altered by a material removal step (e.g., by etching).
  
[List of Patents for class 438 subclass 14]    14WITH MEASURING OR TESTING:
 This subclass is indented under the class definition.  Process having combined therewith a step of measuring or testing a condition of the process or of the device made thereby.
(1) Note. Processes having at least one step proper for the class and combined therewith a step of electrical aging or burn-in are classified herein.

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209Classifying, Separating, and Assorting Solids,   especially subclasses 571+ for methods of electrical testing thereby sensing a property of an item to facilitate subsequent separation.
250Radiant Energy,   subclasses 306+ for inspection of solids or liquids by charged particles, and subclass 371 for invisible radiant energy responsive methods using semiconductor devices.
324Electricity: Measuring and Testing,   for per se electrical measuring, especially subclass 71.5 for determining a nonelectrical property of a semiconductor by measuring an electrical property, subclass 451 for determining a material property using thermoelectric phenomenon, subclasses 500+ for fault detecting in electrical circuits and of electrical components, and subclass 719 for semiconductor materials quality determination using conductivity effects.
374Thermal Measuring and Testing,   especially subclass 57 for thermal testing of susceptibility to thermally induced deterioration, flaw, etc., and subclass 178 for thermal measuring utilizing a barrier layer (e.g., semiconductive junction) sensing element.
  
[List of Patents for class 438 subclass 15]    15Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:
 This subclass is indented under subclass 14.  Process provided including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).
  
[List of Patents for class 438 subclass 16]    16Optical characteristic sensed:
 This subclass is indented under subclass 14.  Process wherein the sensed condition is an optical characteristic of the process or of the device made thereby.
(1) Note. Optical aligning per se is not deemed to be a measurement of an optical characteristic and as such would not bring original classification to this subclass solely based on that claimed feature.

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348Television,   subclasses 86+ for manufacturing wherein a picture signal generator (i.e., television camera) is utilized for monitoring a manufacturing operation.
356Optics: Measuring and Testing,   for optical alignment processes.
382Image Analysis,   especially subclasses 141+ , for a manufacturing process using image analysis, aligning images/masks, or pattern recognition.
  
[List of Patents for class 438 subclass 17]    17Electrical characteristic sensed:
 This subclass is indented under subclass 14.  Process wherein the sensed condition is an electrical characteristic of the process or of the device made thereby.

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324Electricity: Measuring and Testing,   for per se electrical measuring, especially subclass 71.5 for determining a nonelectrical property of a semiconductor by measuring an electrical property, subclass 451 for determining a material property using thermoelectric phenomenon, subclasses 500+ for fault detecting in electrical circuits and of electrical components, and subclass 719 for semiconductor materials quality determination using conductivity effects.
  
[List of Patents for class 438 subclass 18]    18Utilizing integral test element:
 This subclass is indented under subclass 17.  Process wherein the electrical property is sensed utilizing a specific test structure integral to the semiconductor substrate and which has no other function in the completed device.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 48 for test or calibration structures provided on active solid-state devices to permit or facilitate the measurement, test, or calibration of the characteristics of the devices.
  
[List of Patents for class 438 subclass 19]    19HAVING INTEGRAL POWER SOURCE (E.G., BATTERY, ETC.):
 This subclass is indented under the class definition.  Process for making a semiconductor electrical device having therewith an integral structure capable of chemically or radioactively generating electrical power.

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136Batteries: Thermoelectric and Photoelectric,   subclass 202 for apparatus wherein nuclear energy other than that resulting from an induced nuclear reaction is used as a heat source for the generator or comprising a thermoelectric device designed to be employed as an ancillary unit in a nuclear reactor system.
310Electrical Generator or Motor Structure,   subclass 303 for the combination of a semiconductor junction and a radioactive source which radiates the semiconductor material and thus generates a source of current for an external load.
376Induced Nuclear Reactions: Processes, Systems, and Elements,   subclasses 320+ for the direct conversion of the energy produced in a nuclear reaction into an electrical output by a one-step process or apparatus for accomplishing such one-step process.
429Chemistry: Electrical Current Producing Apparatus, Product, and Process,   especially subclass 7 for a combination including a nonbattery electrical component electrically connected within a cell casing other than testing or indicating components.
  
[List of Patents for class 438 subclass 20]    20ELECTRON EMITTER MANUFACTURE:
 This subclass is indented under the class definition.  Process for manufacturing a structure which gives off electrons into free space utilizing a semiconductor substrate.
(1) Note. Some materials may variously be conductive, semiconductive, or insulative. See section A. above for an expansion of what comprises a semiconductor substrate for the purposes of this class.

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136Batteries: Thermoelectric and Photoelectric,   subclass 254 for a photoemissive photoelectric cell.
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 10+ for devices having a low workfunction layer for electron emission.
313Electric Lamp and Discharge Devices,   especially subclass 346 for cathodes containing or coated with electron emissive material, subclasses 499+ for subject matter under the class definition having semiconductor depletion layer-type luminescent material, and subclass 546 for photosensitive photocathodes.
427Coating Processes,   subclasses 74+ for coating processes which result in a photoelectric or photovoltaic product (e.g., a photocathode) which is responsive to visible, infrared, or ultraviolet illumination by (a) emitting electrons, (b) generating an electromotive force, or by (c) varying electrical conductivity.
445Electric Lamp or Space Discharge Component or Device Manufacturing,   for a process of manufacturing a nonsemiconductive-type space discharge device.
  
[List of Patents for class 438 subclass 21]    21MANUFACTURE OF ELECTRICAL DEVICE CONTROLLED PRINTHEAD:
 This subclass is indented under the class definition.  Process for manufacturing from a semiconductor substrate an electrical device utilized for the transfer to another surface of an imprint or mark which transfer is regulated by the electrical device.

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29Metal Working,   subclass 890.1 for fluid pattern dispersion device manufacture (e.g., ink jet manufacture).
347Incremental Printing of Symbolic Information,   subclasses 1+ for ink jet marking apparatus, subclasses 159+ for electrical discharge marking apparatus, subclasses 163+ for electrochemical marking apparatus, and subclasses 171+ for thermal marking apparatus.
  
[List of Patents for class 438 subclass 22]    22MAKING DEVICE OR CIRCUIT EMISSIVE OF NONELECTRICAL SIGNAL:
 This subclass is indented under the class definition.  Process for making a semiconductor electrical device or circuit which is emissive of a nonelectrical output during operation.
(1) Note. The nonelectrical signal serving as input stimulus to the device or circuit may be described as an information carrying wave.

SEE OR SEARCH CLASS:

257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 13 , 79 through 103, and 918 for incoherent light emitting injection luminescent devices.
372Coherent Light Generators,   for coherent light emissive devices, in particular subclasses 43.01+ for a semiconductive laser device and subclass 75 for semiconductor optical laser pump devices.
430Radiation Imagery Chemistry: Process, Composition, or Product Thereof,   subclasses 311+ for electrical device manufacture involving photolithography, and subclass 321 for nonelectro-optic device manufacture involving photolithography.
  
[List of Patents for class 438 subclass 23]    23Having diverse electrical device:
 This subclass is indented under subclass 22.  Process for manufacturing a circuit composed of a plurality of electrical devices integrated on a common substrate or chip of monolithic construction, at least one of the devices being emissive of nonelectrical signal.
  
[List of Patents for class 438 subclass 24]    24Including device responsive to nonelectrical signal:
 This subclass is indented under subclass 23.  Process for making a circuit comprising a combination of a device emissive of nonelectrical signal and a device responsive to nonelectrical signal integrated onto a common substrate or chip of monolithic or hybrid construction.

SEE OR SEARCH CLASS:

65Glass Manufacturing,   especially subclasses 406+ for process of glass bonding an optical fiber to a substrate.
250Radiant Energy,   subclass 551 for signal isolators, including optically coupled light emitters and semiconductor light receivers.
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 80 through 85for an incoherent light emitter coupled to an active solid-state light responsive device, per se.
372Coherent Light Generators,   for coherent light emissive devices, in particular subclasses 43.01+ for a semiconductive laser device and subclass 75 for semiconductor optical laser pump devices.
385Optical Waveguides,   subclass 14 for a laser in integrated optical circuit, subclasses 129+ for a planar optical waveguide, and subclasses 141+ for a waveguide having a particular optical characteristic modifying chemical composition.
  
[List of Patents for class 438 subclass 25]    25Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:
 This subclass is indented under subclass 24.  Process including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).
  
[List of Patents for class 438 subclass 26]    26Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:
 This subclass is indented under subclass 22.  Process including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:

64,for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device responsive to electromagnetic radiation.
106,for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device.
  
[List of Patents for class 438 subclass 27]    27Having additional optical element (e.g., optical fiber, etc.):
 This subclass is indented under subclass 26.  Process for making a semiconductor device wherein the device has combined therewith one or more separate optical elements to transmit or modify electromagnetic radiation incident from the semiconductor device and wherein the optical element is affixed or joined to the semiconductor device.

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65Glass Manufacturing,   especially subclass 406 for processes which involve assembling at least two individually distinct optical fibers, waveguides, or preforms directly to each other (e.g., coupling, etc.)
323Electricity: Power Supply or Regulation Systems,   subclass 902 for optical coupling to a semiconductor.
  
[List of Patents for class 438 subclass 28]    28Plural emissive devices:
 This subclass is indented under subclass 26.  Process for making a collection or grouping of multiple devices emissive of a nonelectrical signal in a single coherent monolith.
  
[List of Patents for class 438 subclass 29]    29Including integrally formed optical element (e.g., reflective layer, luminescent material, contoured surface, etc.):
 This subclass is indented under subclass 22.  Process for making a semiconductor device wherein the device has combined therewith one or more optical elements to transmit or modify electromagnetic radiation incident from the semiconductor device.
  
[List of Patents for class 438 subclass 30]    30Liquid crystal component:
 This subclass is indented under subclass 29.  Process for making a semiconductor device wherein the additional optical element is a substance, usually organic with at least one polarizable group, capable of unidirectional molecular alignment in layers, giving rise to optical bifringement.
(1) Note. Liquid crystals, on variation in pressure, temperature, electric current passing therethrough, etc., change their colors or light transmitting ability, the cholesteric type changing colors while the nematic-type changes between transparency and opacity.

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345Computer Graphics Processing and Selective Visual Display Systems,   subclasses 87+ for a display element control system for liquid crystal display elements arranged in a matrix configuration.
349Liquid Crystal Cells, Elements and Systems,   particularly subclasses 187+ for nominal manufacturing methods or postmanufacturing processing of liquid crystal cells.
  
[List of Patents for class 438 subclass 31]    31Optical waveguide structure:
 This subclass is indented under subclass 29.  Process for making a semiconductor device wherein the additional optical element is an optical conduit for the transmission of light energy.
  
[List of Patents for class 438 subclass 32]    32Optical grating structure:
 This subclass is indented under subclass 29.  Process for making a semiconductor device wherein the additional optical element is a periodic latticework or screen composed of lines producing a series of spectra by the dispersion of the radiation emitted from the device.
  
[List of Patents for class 438 subclass 33]    33Substrate dicing:
 This subclass is indented under subclass 22.  Process having a step of dividing the semiconductor substrate into plural separate bodies.
(1) Note. The dicing may be done by any manner, such as abrading, sawing, etching, cleavage, or a combination thereof.

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83Cutting,   for generic processes of cutting a substrate into discrete individual units.
156Adhesive Bonding and Miscellaneous Chemical Manufacture,   subclasses 701 through 719and 930-932 for processes directed to separating an adhered layer with the layer identity retained as semiconductive.
225Severing by Tearing or Breaking,   subclasses 1+ for methods.
451Abrading,   for a process of dicing by abrading.
  
[List of Patents for class 438 subclass 34]    34Making emissive array:
 This subclass is indented under subclass 22.  Process for making a collection or grouping of multiple devices emissive of nonelectrical signal in a single semiconductor substrate.

SEE OR SEARCH THIS CLASS, SUBCLASS:

28,for a process of packaging (e.g., with mounting, encapsulating, etc.) plural emissive devices into a coherent monolith.
  
[List of Patents for class 438 subclass 35]    35Multiple wavelength emissive:
 This subclass is indented under subclass 34.  Process wherein the array is emissive of plural electromagnetic wavelengths.
  
[List of Patents for class 438 subclass 36]    36Ordered or disordered:
 This subclass is indented under subclass 22.  Process for making a semiconductor device wherein a compound semiconductor region is ordered or disordered.
  
[List of Patents for class 438 subclass 37]    37Graded composition:
 This subclass is indented under subclass 22.  Process wherein the chemical composition of a semiconductor region of the substrate varies with location within the semiconductive region.
  
[List of Patents for class 438 subclass 38]    38Passivating of surface:
 This subclass is indented under subclass 22.  Process having a step of making the surface of the semiconductor substrate less chemically or optically active.
  
[List of Patents for class 438 subclass 39]    39Mesa formation:
 This subclass is indented under subclass 22.  Process having a step of removing material from the semiconductor substrate to form a raised feature relative to the surrounding regions of the substrate.
  
[List of Patents for class 438 subclass 40]    40Tapered etching:
 This subclass is indented under subclass 39.  Process wherein the material removal step is by etching the substrate to form a mesa with nonparallel sides.
  
[List of Patents for class 438 subclass 41]    41With epitaxial deposition of semiconductor adjacent mesa:
 This subclass is indented under subclass 39.  Process including a step of epitaxial growth of semiconductor material on the portion of the substrate adjacent the mesa.
  
[List of Patents for class 438 subclass 42]    42Groove formation:
 This subclass is indented under subclass 22.  Process having a step of removing material from the semiconductor substrate to form a recessed feature (e.g., trench, notch, etc.) relative to the surrounding regions of the substrate.
  
[List of Patents for class 438 subclass 43]    43Tapered etching:
 This subclass is indented under subclass 42.  Process wherein the material removal step is by etching the substrate to form a groove with nonparallel sides.
  
[List of Patents for class 438 subclass 44]    44With epitaxial deposition of semiconductor in groove:
 This subclass is indented under subclass 42.  Process including a step of epitaxial growth of semiconductor material in the groove.
  
[List of Patents for class 438 subclass 45]    45Dopant introduction into semiconductor region:
 This subclass is indented under subclass 22.  Process having a step of introducing a dopant into a semiconductive region of the substrate.
  
[List of Patents for class 438 subclass 46]    46Compound semiconductor:
 This subclass is indented under subclass 22.  Process for making a device emissive of electromagnetic radiation having a compound semiconductor.
  
[List of Patents for class 438 subclass 47]    47Heterojunction:
 This subclass is indented under subclass 46.  Process for making a device emissive of electromagnetic radiation having a interface between two dissimilar semiconductor materials, at least one of which is a compound semiconductor, to constitute a junction.
  
[List of Patents for class 438 subclass 48]    48MAKING DEVICE OR CIRCUIT RESPONSIVE TO NONELECTRICAL SIGNAL:
 This subclass is indented under the class definition.  Process for making a semiconductor electrical device or circuit which is responsive to a nonelectrical input or stimuli during operation.
(1) Note. The nonelectrical signal serving as input stimulus of the device or circuit may be described as an information carrying wave.

SEE OR SEARCH CLASS:

136Batteries: Thermoelectric and Photoelectric,   for active solid-state device structures with a specified usage of generating electricity, especially subclasses 200+ for batteries which generate electricity under the action of heat and subclasses 243+ for batteries which generate electricity under the action of light; some of these batteries utilize potential barrier layers.
250Radiant Energy,   subclass 338.4 for infrared responsive semiconductor devices for signaling, subclasses 370.01 through 370.15 for invisible radiant energy responsive semiconductor devices, subclasses 552 through 553 for photocell circuits and apparatus involving solid-state light sources, and subclasses 208.1 through 208.6 for plural photosensitive elements, including arrays.
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 53 through 56, 108, 414, and 467 through 470 for such devices used as temperature responsive devices; subclasses 108, 414, and 421 through 427 for devices responsive to an external magnetic field; subclasses 10, 11, 21, 53 through 56, 72, 113 through 118, 184 through 189, 225 through 234, 257, 258, 290 through 294, 414, and 431 through 466 for light responsive active semiconductor devices.
338Electrical Resistors,   especially subclass 2 for electrical resistors of the strain gage type and subclass 22 for semiconductor thermistors.
427Coating Processes,   subclasses 74+ for coating processes which result in a photoelectric or photovoltaic product (e.g., photocathode) which is responsive to visible, infrared, or ultraviolet illumination by (a) emitting electrons, (b) generating an electromotive force, or (c) varying electrical conductivity.
  
[List of Patents for class 438 subclass 49]    49Chemically responsive:
 This subclass is indented under subclass 48.  Process for making a semiconductor device responsive to a chemical reaction or the presence of a particular chemical or concentration thereof (e.g., pH level, etc.) in close proximity to the device.

SEE OR SEARCH CLASS:

257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 225 , 253, and 414+ for an active solid-state device responsive to a nonelectrical signal.
  
[List of Patents for class 438 subclass 50]    50Physical stress responsive:
 This subclass is indented under subclass 48.  Process for making a semiconductor device or circuit responsive to physical deformation (e.g., pressure, strain, etc.).
(1) Note. Processes for making semiconductor electrical device based surface acoustic wave devices, accelerometers, and strain gages are proper for this subclass.

SEE OR SEARCH CLASS:

73Measuring and Testing,   particularly subclass 777 for a semiconductor-type stress/strain sensor, subclass 514.16 for a semiconductor-type accelerometer, and subclass 754 for semiconductor-type fluid pressure sensors.
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 415+ for a solid-state active device responsive to physical deformation.
333Wave Transmission Lines and Networks,   subclasses 193+ for electromechanical filter using surface acoustic waves.
338Electrical Resistors,   subclass 2 for electrical resistors of the strain gage type.
  
[List of Patents for class 438 subclass 51]    51Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:
 This subclass is indented under subclass 50.  Process including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:

106,for process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device.
  
[List of Patents for class 438 subclass 52]    52Having cantilever element:
 This subclass is indented under subclass 50.  Process for making a physical stress responsive device or circuit which has a projecting beam or horizontal member supported at only one end.

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216Etching a Substrate: Processes,   subclass 2 for a process of making a cantilever mechanical structure using semiconductive material wherein no electrical function is attributable to the cantilever element produced.
  
[List of Patents for class 438 subclass 53]    53Having diaphragm element:
 This subclass is indented under subclass 50.  Process for making a physical stress responsive device or circuit which has a thin deflectable membrane.

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216Etching a Substrate: Processes,   subclass 2 for a process of making a diaphragm mechanical structure using semiconductive material wherein no electrical function is attributable to the structure produced.
  
[List of Patents for class 438 subclass 54]    54Thermally responsive:
 This subclass is indented under subclass 48.  Process for making a device or circuit responsive to the temperature proximate the device.
(1) Note. Processes of making devices which vary in electrical properties at various temperatures of operation are not deemed to be responsive to thermal stimuli for the purposes of this subclass.

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136Batteries: Thermoelectric and Photoelectric,   subclass 200 for a process of using a thermoelectric device for generating electrical current.
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 108 , 225, 252, and 467 through 470 for a device responsive to temperature.
  
[List of Patents for class 438 subclass 55]    55Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:
 This subclass is indented under subclass 54.  Process provided including (a) multiple operations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multiple operations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:

106,for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device.
  
[List of Patents for class 438 subclass 56]    56Responsive to corpuscular radiation (e.g., nuclear particle detector, etc.):
 This subclass is indented under subclass 48.  Process for making a device or circuit responsive to atomic or subatomic discrete particles (e.g., alpha, neutron, fission fragment or fissionable isotope).

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250Radiant Energy,   subclass 371 for invisible radiant energy responsive methods using semiconductor devices. Also see subclasses 370.01+ for invisible radiant energy responsive electric signaling means of the semiconductor type, particularly subclass 370.02 for an alpha particle detection system, subclass 370.03 for a fission fragmentor fissionable isotope detection system, and subclass 370.05 for a neutron detection system.
  
[List of Patents for class 438 subclass 57]    57Responsive to electromagnetic radiation:
 This subclass is indented under subclass 48.  Process for making a device or circuit responsive to ultraviolet, visible, or infrared light, x-rays, or gamma rays.
(1) Note. Processes of making devices in which (a) stored electrical charges are erased by exposure to electromagnetic radiation or (b) the device is switched from a nonconducting state to a conducting state or vice versa (e.g., optical turn-on type), are not considered to be responsive to a nonelectrical signal for placement in this and its indented subclasses.

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257,for a process of manufacturing a field effect transistor which has a floating gate structure capable of having electrical charge stored therein erased upon the application of electromagnetic radiation.

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427Coating Processes,   subclasses 74+ for a process of coating with a photoelectric material to produce an electrical product.
430Radiation Imagery Chemistry: Process, Composition, or Product Thereof,   subclasses 31+ for an electric or magnetic imagery process employing a photoconductive semiconductive component.
  
[List of Patents for class 438 subclass 58]    58Gettering of substrate:
 This subclass is indented under subclass 57.  Process having a step of gettering the semiconductor substrate.

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471,for a process of gettering a semiconductor substrate per se.
  
[List of Patents for class 438 subclass 59]    59Having diverse electrical device:
 This subclass is indented under subclass 57.  Process for making an electrical device responsive to electromagnetic radiation in combination with an additional electrical device which is not responsive to electromagnetic radiation.
  
[List of Patents for class 438 subclass 60]    60Charge transfer device (e.g., CCD, etc.):
 This subclass is indented under subclass 59.  Process for making a charge transfer device having combined therewith another electrical device or element, either of which being responsive to electromagnetic radiation.
(1) Note. A charge transfer device is a structure in which storage sites for packets of electrical charge are induced at or below the semiconductor surface by an electric field applied by serially arranged gate electrodes formed thereupon and wherein carrier potential energy per unit charge minima are established at a given storage site and such minima are transferred in a serial manner via an active channel region to one or more adjacent storage sites.
  
[List of Patents for class 438 subclass 61]    61Continuous processing:
 This subclass is indented under subclass 57.  Process for making a semiconductor device responsive to electromagnetic radiation wherein a series of processing steps are performed in a uninterrupted manner.
  
[List of Patents for class 438 subclass 62]    62Using running length substrate:
 This subclass is indented under subclass 61.  Process whereby the continuous processing is affected using an elongate substrate of indeterminate length having a semiconductive layer thereon.

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484,for a process of depositing amorphous active semiconductor onto a substrate of indeterminate length.
490,for a process of depositing polycrystalline active semiconductor onto a substrate of indeterminate length.
  
[List of Patents for class 438 subclass 63]    63Particulate semiconductor component:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation wherein the substrate contains particulate semiconductive material.
(1) Note. "Particulate" is defined as a mass of discrete units of matter so small (generally of largest dimension <<1000 microns) that they are not ordinarily handled as individual units, and whose shape and length-to-diameter ratio are such that in the dry state the particles will not hold together as a coherent article without the application of pressure or heat.

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136Batteries: Thermoelectric or Photoelectric,   subclass 250 for a photoelectric device having a particulate or spherical semiconductor component.
  
[List of Patents for class 438 subclass 64]    64Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:
 This subclass is indented under subclass 57.  Process provided including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).
(1) Note. The term packaging connotes the integration/assembly of the semiconductive substrate/chip/die with a preformed housing, capsule, or support.

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106,for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device.
  
[List of Patents for class 438 subclass 65]    65Having additional optical element (e.g., optical fiber, etc.):
 This subclass is indented under subclass 64.  Process for packaging a semiconductor device responsive to electromagnetic radiation wherein the device has combined therewith one or more optical elements to transmit or modify electromagnetic radiation incident upon the semiconductor device and the optical element is fixed or attached to the device or the housing or support thereof.

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65Glass Manufacturing,   especially subclass 406 for processes which involve assembling at least two individually distinct optical fibers, waveguides, or preforms directly to each other (e.g., coupling, etc.).
323Electricity: Power Supply or Regulation Systems,   subclass 902 for optical coupling to a semiconductor.
  
[List of Patents for class 438 subclass 66]    66Plural responsive devices (e.g., array, etc.):
 This subclass is indented under subclass 64.  Process for packaging a multiplicity of devices or elements responsive to electromagnetic radiation into a coherent monolith.
(1) Note. The plural responsive devices may be combined via a hybrid construction or secured onto a common support.
  
[List of Patents for class 438 subclass 67]    67Assembly of plural semiconductor substrates:
 This subclass is indented under subclass 66.  Process having a step of joining multiple semiconductor substrates into a coherent monolith in which plural devices responsive to electromagnetic radiation are formed.
  
[List of Patents for class 438 subclass 68]    68Substrate dicing:
 This subclass is indented under subclass 57.  Process having a step of dividing the semiconductor substrate into multiple separate bodies.
(1) Note. The dicing may be done by any manner, such as abrading, sawing, etching, cleavage, or a combination thereof.

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83Cutting,   for generic processes of cutting a substrate into discrete individual units.
225Severing by Tearing or Breaking,   subclasses 1+ for methods.
451Abrading,   for a process of dicing by abrading.
  
[List of Patents for class 438 subclass 69]    69Including integrally formed optical element (e.g., reflective layer, luminescent layer, etc.):
 This subclass is indented under subclass 57.  Process for making a semiconductor device responsive to electromagnetic radiation wherein the device has combined therewith one or more integrally formed optical elements to transmit or modify electromagnetic radiation incident upon the semiconductor device
  
[List of Patents for class 438 subclass 70]    70Color filter:
 This subclass is indented under subclass 69.  Process for making a semiconductor device responsive to electromagnetic radiation having combined therewith structural means functioning as a color filter element.
  
[List of Patents for class 438 subclass 71]    71Specific surface topography (e.g., textured surface, etc.):
 This subclass is indented under subclass 69.  Process having a surface of specified topography incorporated into an electromagnetic sensitive device or utilized during manufacture thereof.
  
[List of Patents for class 438 subclass 72]    72Having reflective or antireflective component:
 This subclass is indented under subclass 69.  Process for making a semiconductor device responsive to electromagnetic radiation having a component which has reflective or antireflective properties with respect to electromagnetic radiation incident thereupon.
  
[List of Patents for class 438 subclass 73]    73Making electromagnetic responsive array:
 This subclass is indented under subclass 57.  Process for making a collection or grouping of electromagnetically responsive devices on a single, coherent, semiconductor substrate.
(1) Note. Individual detectors of the array may alternatively be referred to as elements, pixels, or cells.
  
[List of Patents for class 438 subclass 74]    74Vertically arranged (e.g., tandem, stacked, etc.):
 This subclass is indented under subclass 73.  Process wherein the array of electromagnetic responsive devices is configured with one responsive device residing at a position over another such device.
  
[List of Patents for class 438 subclass 75]    75Charge transfer device (e.g., CCD, etc.):
 This subclass is indented under subclass 73.  Process for making a structure in which storage sites for packets of electrical charge are induced at or below the semiconductor surface by an electric field applied by serially arranged gate electrodes formed thereupon and wherein carrier potential energy per unit charge minima are established at a given storage site and such minima are transferred in a serial manner via an active channel region to one or more adjacent storage sites.
  
[List of Patents for class 438 subclass 76]    76Majority signal carrier (e.g., buried or bulk channel, peristaltic, etc.):
 This subclass is indented under subclass 75.  Process for making a charge transfer device wherein the transfer of such charge minima is by majority carriers of the semiconductive material (i.e., by electrons in n-type material or by holes in p-type semiconductive material) and such transfer is in response to electromagnetic radiation incident to the device.
  
[List of Patents for class 438 subclass 77]    77Compound semiconductor:
 This subclass is indented under subclass 75.  Process for making a charge transfer device in which the storage sites are composed of a compound semiconductor material.
  
[List of Patents for class 438 subclass 78]    78Having structure to improve output signal (e.g., exposure control structure, etc.):
 This subclass is indented under subclass 75.  Process for making a charge transfer device which contains structural means to improve the electrical signal it generates in response to the electromagnetic radiation.
(1) Note. The structural means to improve the output signal may serve to control the amount of light incident on the device which is transferred as output signal charge.
  
[List of Patents for class 438 subclass 79]    79Having blooming suppression structure (e.g., antiblooming drain, etc.):
 This subclass is indented under subclass 78.  Process for making a charge transfer device wherein the structural means to improve the output signal prevents spill over of a large amount of signal charge generated at a storage site which receives an electromagnetic radiation responsive input signal of very high intensity to adjacent storage sites.
(1) Note. The antiblooming suppression structure may include a drain structure for removing charge from storage sites.
(2) Note. The antiblooming drain structure may be located in the device beneath storage sites rather than on its surface.
  
[List of Patents for class 438 subclass 80]    80Lateral series connected array:
 This subclass is indented under subclass 73.  Process wherein the array of electromagnetically responsive devices is laterally arranged and serially electrically connected.
  
[List of Patents for class 438 subclass 81]    81Specified shape junction barrier (e.g., V-grooved junction, etc.):
 This subclass is indented under subclass 80.  Process wherein the junction barrier interface (i.e., between adjoining semiconductor regions of opposite conductivity type) has a specified geometrical configuration.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 465 for a light-responsive active solid-state device having a barrier junction of specified geometrical configuration and subclasses 653+ for an active solid-state device having a specified shape PN junction.
  
[List of Patents for class 438 subclass 82]    82Having organic semiconductor component:
 This subclass is indented under subclass 57.  Process wherein the semiconductor substrate contains a semiconductive compound in which the molecule is characterized by two or more carbon atoms bonded together, one atom of carbon bonded to at least one atom of hydrogen or halogen (i.e., chlorine, fluorine, bromine, iodine) or one atom of carbon bonded to at least one atom of nitrogen by a single or double bond.
(1) Note. Exceptions to this rule include HCN, CN-CN, HNCO, HNCS, cyanogen halides, cyanamide, fulminic acid, and metal carbides. These are not regarded as organic materials. Also, note that graphite and diamond are not regarded as organic semiconductors, since they are not compounds; silicon carbide is not regarded as organic.
  
[List of Patents for class 438 subclass 83]    83Forming point contact:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation including forming a potential barrier between an electrode of small contacting or cross-sectional area in touching relationship with a substantially larger area of the semiconductor substrate, thus forming a potential barrier junction at the single point therebetween.
  
[List of Patents for class 438 subclass 84]    84Having selenium or tellurium elemental semiconductor component:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation utilizing a semiconductor substrate containing semiconductive selenium or tellurium in elemental form (i.e., notin a compound) or an alloy (i.e., mixture) thereof.
  
[List of Patents for class 438 subclass 85]    85Having metal oxide or copper sulfide compound semiconductive component:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation utilizing a semiconductor substrate containing a metal oxide or copper sulfide compound semiconductor.
  
[List of Patents for class 438 subclass 86]    86And cadmium sulfide compound semiconductive component:
 This subclass is indented under subclass 85.  Process wherein the semiconductor substrate containing a metal oxide or copper sulfide compound semiconductor additionally contains a cadmium sulfide compound semiconductor.
  
[List of Patents for class 438 subclass 87]    87Graded composition:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation wherein the chemical composition of a semiconductor region of the substrate varies with location within the semiconductive region.
  
[List of Patents for class 438 subclass 88]    88Direct application of electric current:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation having a step of directly applying electrical current to the semiconductor substrate.
  
[List of Patents for class 438 subclass 89]    89Fusion or solidification of semiconductor region:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation having a step of fusing or solidifying a semiconductive region of the substrate.
  
[List of Patents for class 438 subclass 90]    90Including storage of electrical charge in substrate:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation having a step of storing electrical charge in a region of the semiconductor substrate.

SEE OR SEARCH THIS CLASS, SUBCLASS:

19,for a process of making a semiconductor electrical device having formed therewith an integral battery or power source.
  
[List of Patents for class 438 subclass 91]    91Avalanche diode:
 This subclass is indented under subclass 57.  Process for making a device which is configured to operate in a manner in which an external voltage applied in the reverse-conducting direction of the device junction with sufficient magnitude causes the potential barrier at the junction to breakdown due to electrons or holes gaining sufficient speed to dislodge valence electrons and thus create more hole-electron current carriers resulting in a sudden change from high dynamic electrical resistance to very low dynamic resistance.
(1) Note. The terms Zener diode and Zener breakdown voltage are used rather loosely in that the breakdown mechanism above about 6 volts is thought to be due to avalanching and that below about 6 volts is thought to be due essentially to tunnelling.

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380,for a process of making an avalanche diode which is not responsive to electromagnetic radiation.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 199 for an avalanche diode in a noncharge transfer device having a heterojunction, subclass 438 for a light-responsive avalanche junction device, subclass 481 for an avalanche diode having a Schottky barrier, subclass 551 for an avalanche diode used as a voltage reference element combined with pn junction isolation means in an integrated circuit, and subclasses 603+ for avalanche diodes in general.
  
[List of Patents for class 438 subclass 92]    92Schottky barrier junction:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation having a Schottky rectifying junction.
  
[List of Patents for class 438 subclass 93]    93Compound semiconductor:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation having a compound semiconductor.
  
[List of Patents for class 438 subclass 94]    94Heterojunction:
 This subclass is indented under subclass 93.  Process for making a device responsive to electromagnetic radiation having a interface between two dissimilar semiconductor materials, at least one of which is a compound semiconductor, to constitute a junction.
  
[List of Patents for class 438 subclass 95]    95Chalcogenide (i.e., oxygen (O), sulfur (S), selenium (Se), tellurium (Te)) containing:
 This subclass is indented under subclass 93.  Process wherein the compound semiconductor contains an element from the group of oxygen, sulfur, selenium, and tellurium.
  
[List of Patents for class 438 subclass 96]    96Amorphous semiconductor:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation having an amorphous semiconductor component.
  
[List of Patents for class 438 subclass 97]    97Polycrystalline semiconductor:
 This subclass is indented under subclass 57.  Process for making a device responsive to electromagnetic radiation having a polycrystalline semiconductor component.
  
[List of Patents for class 438 subclass 98]    98Contact formation (i.e., metallization):
 This subclass is indented under subclass 57.  Process for making a semiconductor device responsive to electromagnetic radiation having a step of coating the device with electrically conductive material forming an electrical connect or conductor thereto.
(1) Note. The electrically conductive material may additionally be transparent to electromagnetic radiation.
  
[List of Patents for class 438 subclass 99]    99HAVING ORGANIC SEMICONDUCTIVE COMPONENT:
 This subclass is indented under the class definition.  Process for making a semiconductor electrical device wherein the semiconductor substrate contains a semiconductive compound in which the molecule is characterized by two or more carbon atoms bonded together, one atom of carbon bonded to at least one atom of hydrogen or halogen (i.e., chlorine, fluorine, bromine, iodine) or one atom of carbon bonded to at least one atom of nitrogen by a single or double bond.
(1) Note. Exceptions to this rule include HCN, CN-CN, HNCO, HNCS, cyanogen halides, cyanamide, fulminic acid, and metal carbides. These are not regarded as organic materials. Also, note that graphite and diamond are not regarded as organic semiconductors, since they are not compounds; silicon carbide is not regarded as organic.

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82,for a process of making a device having an organic semiconductive component which is responsive to electromagnetic radiation.

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29Metal Working,   subclass 25.03 for a process of making an electrolytic capacitor using a solid organic semiconductor.
136Batteries: Thermoelectric and Photoelectric,   subclass 263 for photoelectric cells containing organic active material.
252Compositions,   subclass 62.3 for organic barrier layer device compositions.
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 40 for an active solid-state device having an organic semiconductor.
  
[List of Patents for class 438 subclass 100]    100MAKING POINT CONTACT DEVICE:
 This subclass is indented under the class definition.  Process for making a semiconductor electrical device having a potential barrier between an electrode of small contacting or cross-sectional area in touching relationship with a substantially larger area of the semiconductor substrate, thus forming a potential barrier junction at the single point of contact therebetween.

SEE OR SEARCH THIS CLASS, SUBCLASS:

83,for a process of making a point contact device which is responsive to electromagnetic radiation.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 41 for a point contact device.
  
[List of Patents for class 438 subclass 101]    101Direct application of electrical current:
 This subclass is indented under subclass 100.  Process including a step of directly applying electrical current to the point contact semiconductor electrical device.
  
[List of Patents for class 438 subclass 102]    102HAVING SELENIUM OR TELLURIUM ELEMENTAL SEMICONDUCTOR COMPONENT:
 This subclass is indented under the class definition.  Process for making a semiconductor electrical device wherein the semiconductor substrate is comprised of semiconductive selenium or tellurium in elemental form (i.e., not in a compound) or an alloy (i.e., mixture) thereof.

SEE OR SEARCH THIS CLASS, SUBCLASS:

84,for a process of making a device responsive to electromagnetic radiation comprised of semiconductive selenium or tellurium in elemental form or an alloy thereof.

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252Compositions,   subclass 62.3 for barrier layer device compositions containing free elemental selenium or tellurium.
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 42 for a device having elemental selenium or tellurium semiconductor.
420Alloys or Metallic Compositions,   subclass 579 for selenium or tellurium base alloy containing metal.
  
[List of Patents for class 438 subclass 103]    103Direct application of electrical current:
 This subclass is indented under subclass 102.  Process having a step of directly applying electrical current to the selenium or tellurium elemental semiconductor component substrate.
  
[List of Patents for class 438 subclass 104]    104HAVING METAL OXIDE OR COPPER SULFIDE COMPOUND SEMICONDUCTOR COMPONENT:
 This subclass is indented under the class definition.  Process for making a semiconductor electrical device wherein the semiconductor substrate contains a metal oxide or copper sulfide compound semiconductor.

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85,for a process of making a device responsive to electromagnetic radiation having a metal oxide or copper sulfide compound semiconductor component.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 43 for a semiconductor solid-state device having a metal oxide or copper sulfide compound semiconductor component.
264Plastic and Nonmetallic Article Shaping or Treating: Processes,   subclass 61 for methods of vitrifying or sintering an inorganic preform to make a discrete passive device (e.g., multilayer ceramic capacitor, etc.).
  
[List of Patents for class 438 subclass 105]    105HAVING DIAMOND SEMICONDUCTOR COMPONENT:
 This subclass is indented under the class definition.  Process for making a semiconductor electrical device wherein the semiconductor substrate contains a diamond semiconductor component.
(1) Note. The utilization of a diamond component for other than its semiconductor properties (e.g., as a thermal heat sink) is not proper for this subclass.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 77 , for a solid-state device having a diamond semiconductor component.
  
[List of Patents for class 438 subclass 106]    106PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR:
 This subclass is indented under the class definition.  Process provided including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor, or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).
(1) Note. Packaging is a semiconductor art manufacturing term for integration, assembly, or surrounding of a semiconductor substrate (e.g., chip, die, etc.) with a permanent encasement, housing, capsule, or support. This is distinguished from package making found in Class 53 which is directed to preparing a manufactured product for passage through the channels of trade in a safe, convenient, and attractive condition, usually wrapped in a cover or in a container which is intended to be removed when the manufactured product is used.
(2) Note. See References to Other Classes in the class definition, for a listing of various related classes providing for unit or combined operations.
(3) Note. See References to Other Classes in the class definition, for a listing of various related classes providing for electrical connectors, electrical device housing or packaging, etc.

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26,for a process of packaging (e.g., with mounting, encapsulating, etc.)or treating a packaged semiconductor device or circuit emissive of a nonelectrical signal.
51,for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device responsive to physical stress.
55,for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a thermally responsive semiconductor electrical device.
64,for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a semiconductor device or circuit responsive to electromagnetic radiation.
100,for a process of manufacturing a point-contact-type semiconductor device.
616,for a process of transcribing bump electrodes which substantially do not retain their contour following transfer from a carrier substrate (e.g., template, etc.) to a semiconductor substrate.

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29Metal Working,   especially subclass 827 for lead frame or beam lead device manufacture, subclasses 829+ for the assembly of an electrical component to an insulative base having a conductive path applied thereto, or formed thereon or therein (e.g., a printed circuit board), subclasses 854+ for the assembly of an electrical component directly to terminal or elongated conductor, and subclasses 729+ for an electrical device manufacturing apparatus.
53Package Making,   subclasses 396+ for methods of encompassing, encasing, or completely surrounding goods or materials with a cover made from sheet material stock, and for methods of assembling or securing a separate closure (hood, cap, capsule, crown, seal, etc.) to the aperture of a preformed receptacle so as to complete the encasement of contents.
65Glass Manufacturing,   especially subclasses 36+ for a process of fusion bonding of glass to a formed part, and subclass 155 for electronic device making means involving fusion bonding.
148Metal Treatment,   for a process of treating metal to modify or maintain the internal physical structure (i.e., microstructure) or chemical properties of metal.
156Adhesive Bonding and Miscellaneous Chemical Manufacture,   subclasses 60+ for a single step process of adhesively bonding and for certain multistep processes having a step of adhesively bonding a nominal semiconductive chip or wafer.
216Etching a Substrate: Processes,   especially subclasses 13+ for processes of manufacturing a printed circuit board or thick film circuit board involving an etching step.
219Electric Heating,   subclasses 78.01+ for process and apparatus for bonding by electrical current and pressure.
228Metal Fusion Bonding,   appropriate subclasses, for a process of fusion bonding and additional operations which are considered to be ancillary to the bonding (preheating, positioning, pretinning, etc.) of a semiconductive substrate, especially subclass 123.1 and 179.1+.
264Plastic and Nonmetallic Article Shaping or Treating: Processes,   for a process (and steps perfecting same) of shaping plastic or nonmetallic material and uniting it to a preform (e.g., encapsulating), said preform being a semiconductive substrate.
324Electricity: Measuring and Testing,   for a process of temporarily affixing a semiconductor substrate to a support during the electrical testing thereof.
427Coating Processes,   subclasses 96.1 through 99.5for a process of coating a nonsemiconductive substrate to produce an integrated or printed circuit or circuit board (e.g., coating an insulative substrate to form a printed or thick film circuit board, etc.).
  
[List of Patents for class 438 subclass 107]    107Assembly of plural semiconductive substrates each possessing electrical device:
 This subclass is indented under subclass 106.  Process wherein plural semiconductive substrates are combined into a hybrid construction or secured onto a common support.

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455,for a nonpackaging process of joining or bonding plural semiconductive substrates wherein none of the semiconductive substrates are intended to function as a terminal, elongated conductor, or support.
  
[List of Patents for class 438 subclass 108]    108Flip-chip-type assembly:
 This subclass is indented under subclass 107.  Process wherein a semiconductive substrate which has electric contacts on the top side thereof is flipped to juxtapose the contacts in face-to-face orientation with a substrate which has matching electrical contacts prior to bonding.
  
[List of Patents for class 438 subclass 109]    109Stacked array (e.g., rectifier, etc.):
 This subclass is indented under subclass 107.  Process for making a semiconductor device wherein a multiplicity of semiconductive substrates are juxtaposed in face-to-face orientation.
  
[List of Patents for class 438 subclass 110]    110Making plural separate devices:
 This subclass is indented under subclass 106.  Process for making a semiconductor device wherein a multiplicity of separate semiconductive devices are obtained.
  
[List of Patents for class 438 subclass 111]    111Using strip lead frame:
 This subclass is indented under subclass 110.  Process for making plural separate semiconductor devices utilizing a plurality of support structures or positions arranged on an elongated continuum prior to separation.
(1) Note. The continuum may either be the material of the lead frame (e.g., metal strip) or the lead frame may be mounted serially on another continuum (e.g., plastic strip).
  
[List of Patents for class 438 subclass 112]    112And encapsulating:
 This subclass is indented under subclass 111.  Process including a step of surrounding the semiconductor substrate with an electrically insulating material which forms a sealed encasement therefor.
  
[List of Patents for class 438 subclass 113]    113Substrate dicing:
 This subclass is indented under subclass 110.  Process wherein a semiconductive substrate is divided into discrete individual units.
(1) Note. The dicing may be done by any manner, such as abrading, sawing, etching, cleavage, or a combination thereof.

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460,for a process under the class definition of dicing a semiconductor substrate into multiple separate bodies.

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83Cutting,   for generic processes of cutting a substrate into discrete individual units.
225Severing by Tearing or Breaking,   subclasses 1+ for methods.
451Abrading,   for a process of dicing by abrading.
  
[List of Patents for class 438 subclass 114]    114Utilizing a coating to perfect the dicing:
 This subclass is indented under subclass 113.  Process including a step of coating the semiconductive substrate to enhance the dicing operation.
  
[List of Patents for class 438 subclass 115]    115Including contaminant removal or mitigation:
 This subclass is indented under subclass 106.  Process including the step of removing undesirable material through the use of a getter, desiccant, etc.
  
[List of Patents for class 438 subclass 116]    116Having light transmissive window:
 This subclass is indented under subclass 106.  Process wherein the housing contains light transmissive means allowing light to reach the enclosed semiconductive device.

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64,for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device responsive to electromagnetic radiation.
  
[List of Patents for class 438 subclass 117]    117Incorporating resilient component (e.g., spring, etc.):
 This subclass is indented under subclass 106.  Process for packaging a semiconductor substrate wherein the resulting structure includes an elastically compressible component.
  
[List of Patents for class 438 subclass 118]    118Including adhesive bonding step:
 This subclass is indented under subclass 106.  Process for packaging a semiconductor substrate including a step of joining the semiconductor substrate to a another body by nonmetallic bonding.
(1) Note. See Lines With Other Classes, "Packaging (e.g., With Mounting, Encapsulating, etc.) or Treatment of Packaged Semiconductor" above. Also see the search notes below.

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156Adhesive Bonding and Miscellaneous Chemical Manufacture,   subclasses 60+ for a step of surface bonding or assembly therefor, and the Class 156 definition for special lines to Class 29, Metal Working.
  
[List of Patents for class 438 subclass 119]    119Electrically conductive adhesive:
 This subclass is indented under subclass 118.  Process wherein the nonmetallic bonding material is electrically conductive.
(1) Note. The nonmetallic bonding material may possess particulate metal dispersed in the nonmetallic adhesive binder to render the composition electrically conductive.
  
[List of Patents for class 438 subclass 120]    120With vibration step:
 This subclass is indented under subclass 106.  Process for packaging a semiconductor substrate including a step of applying vibratory energy.
  
[List of Patents for class 438 subclass 121]    121Metallic housing or support:
 This subclass is indented under subclass 106.  Process for mounting, packaging, or encapsulating a semiconductor device wherein a semiconductive substrate is supported or enclosed by joining the substrate to a metallic body.
  
[List of Patents for class 438 subclass 122]    122Possessing thermal dissipation structure (i.e., heat sink):
 This subclass is indented under subclass 121.  Process wherein the metallic body joined to the semiconductor substrate possesses structure for the dissipation of thermal energy generated during operation of the electrical device.

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584,for a process of coating a semiconductor substrate with a thermally conductive material (e.g., plated heat sink, etc.)
  
[List of Patents for class 438 subclass 123]    123Lead frame:
 This subclass is indented under subclass 121.  Process wherein the metallic body joined to the semiconductor device is in the form of a metallic support with electrically conductive leads depending therefrom.
  
[List of Patents for class 438 subclass 124]    124And encapsulating:
 This subclass is indented under subclass 121.  Process including a step of surrounding the semiconductor substrate or the metallic housing or support with an electrically insulating material which forms a sealed encasement therefor.
  
[List of Patents for class 438 subclass 125]    125Insulative housing or support:
 This subclass is indented under subclass 106.  Process for making a structure wherein the semiconductive device is supported or enclosed by preformed insulative body.
(1) Note. An encapsulant, per se, is not considered to be a supporting structure proper for this and indented subclasses.
  
[List of Patents for class 438 subclass 126]    126And encapsulating:
 This subclass is indented under subclass 125.  Process including a step of surrounding the semiconductor substrate or insulative housing or support with an electrically insulating material which forms a sealed encasement therefor.
  
[List of Patents for class 438 subclass 127]    127Encapsulating:
 This subclass is indented under subclass 106.  Process including a step of surrounding the semiconductor substrate with an electrically insulating material which forms a sealed encasement therefor.

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65Glass Manufacturing,   for a per se process of shaping glass material about an electrical device to encapsulate same.
264Plastic and Nonmetallic Article Shaping or Treating: Processes,   especially subclasses 272.11+ for per se electrical component encapsulating by molding of insulative material about the electrical component.
  
[List of Patents for class 438 subclass 128]    128MAKING DEVICE ARRAY AND SELECTIVELY INTERCONNECTING:
 This subclass is indented under the class definition.  Process for forming an array of active devices on a semiconductor substrate and electrically interconnecting the devices into a designated circuit arrangement.
(1) Note. The processes found in this and its indented subclasses result in circuits which are alter-natively referred to as personalized, customized, or application specific.
(2) Note. This and its indented subclasses do not take processes of producing a shorted or shunted structure as an integral part of a single device.

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6,for processes of interconnecting plural devices wherein at least one operation is responsive to a sensed condition.
587,for process of forming an array of gate electrodes upon a semiconductor substrate.
598+,for a process of metallizing a semiconductor substrate wherein the electrically conductive metallization contains a portion which is alterable from the conductive to nonconductive condition or vice-versa (e.g., a fuse or antifuse).

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   particularly subclasses 202+ for gate arrays.
  
[List of Patents for class 438 subclass 129]    129With electrical circuit layout:
 This subclass is indented under subclass 128.  Process including a step of designing the topological arrangement of arrayed device components or electrical conductors therebetween in combination with making the semiconductor device array.

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369Dynamic Information Storage or Retrieval,   for processes of storing or retrieving dynamic information, subclasses 99+ for a particular detail of the information handling portion of a system, especially subclasses 100+ for radiation beam modification of or by a storage medium and subclass 126 for electrical modification or sensing of a storage medium (e.g., capacitive, resistive, or electrostatic discharge)
  
[List of Patents for class 438 subclass 130]    130Rendering selected devices operable or inoperable:
 This subclass is indented under subclass 128.  Process wherein selected devices located on a semiconductive substrate are electrically completed or electrically shorted so as to be rendered operable or inoperable.
(1) Note. Adjusting an operating characteristic (e.g., threshold voltage) of selected devices so as to render them operational yet nonresponsive to the intended operating voltage is specifically excluded from herein.

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276,for processes of programming or encoding a grouping of insulated gate field effect transistors by altering the operative mode (enhancement type or depletion type) of selected transistors.
  
[List of Patents for class 438 subclass 131]    131Using structure alterable to conductive state (i.e., antifuse):
 This subclass is indented under subclass 128.  Process for making an array of electrical devices and selectively interconnecting the devices via a structure which is alterable from a nonconductive state to a conductive state.

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467,for altering the conductivity of an antifuse element through the direct application of an electrical current.
600,for metallization processes forming a structure alterable to a conductive state.
  
[List of Patents for class 438 subclass 132]    132Using structure alterable to nonconductive state (i.e., fuse):
 This subclass is indented under subclass 128.  Process for making an array of electrical devices and selectively interconnecting the devices via a structure which is alterable from a conductive state to a nonconductive state.

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467,for altering the conductivity of a fuse element through the direct application of electrical current.
601,for metallization processes forming a structure alterable to a nonconductive state.

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327Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems,   especially subclass 525 for a specific identifiable device, circuit, or system having as a part of it"s construction or arrangement a fusible link element.
365Static Information Storage and Retrieval,   subclass 96 for fusible links relating to programmable read-only memory and subclass 200 for eliminating "bad bit" information associated with read/write circuits.
  
[List of Patents for class 438 subclass 133]    133MAKING REGENERATIVE-TYPE SWITCHING DEVICE (E.G., SCR, IGBT, THYRISTOR, ETC.):
 This subclass is indented under the class definition.  Process for making a switching device structure acting as if it has two or more active emitter junctions each of which is associated with a separate, equivalent transistor having an individual gain and which, when initiated by a base region current, causes the equivalent transistors to mutually drive each other in a regenerative manner to lower the voltage drop between emitter regions.
(1) Note. If the current is above a level Ih, called the "holding current", then the device will remain ON when the triggering signal is removed by the regenerative feedback therebetween, and is then said to be "latched.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 107+ for a regenerative-type switching device.
361Electricity: Electrical Systems and Devices,   subclasses 100+ and 205 for circuits employing thyristors (e.g., silicon controlled rectifiers (SCRs))
363Electric Power Conversion Systems,   subclasses 27+ , 54, 57+, 68, 85+, 96+, 128+, 135+, and 160+ for circuits employing thyristors (e.g., silicon controlled rectifiers (SCRs))
  
[List of Patents for class 438 subclass 134]    134Bidirectional rectifier with control electrode (e.g., triac, diac, etc.):
 This subclass is indented under subclass 133.  Process for making a regenerative switching device having a control electrode which device can conduct in both the forward and reverse directions, being triggered into conduction by a pulse applied to the control electrode.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 119+ for a bidirectional rectifier with control electrode.
  
[List of Patents for class 438 subclass 135]    135Having field effect structure:
 This subclass is indented under subclass 133.  Process wherein the regenerative switching device includes or is combined with a field effect structure (i.e., wherein the current through a active channel region is controlled by an electric field coming from a voltage which is applied between the gate and source terminals thereof).
(1) Note. Includes amplifying gate-type and optical turn-on-type structures.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 133+ for a regenerative device combined with a field effect transistor.
  
[List of Patents for class 438 subclass 136]    136Junction gate:
 This subclass is indented under subclass 135.  Process for making a regenerative switching device which possesses a gate electrode which forms a PN (rectifying) junction with the semiconductor substrate.
  
[List of Patents for class 438 subclass 137]    137Vertical channel:
 This subclass is indented under subclass 136.  Process for making a junction gate regenerative-type switching device wherein the active channel is configured to provide, in whole or in part, a vertically conductive pathway between source and drain regions.
  
[List of Patents for class 438 subclass 138]    138Vertical channel:
 This subclass is indented under subclass 135.  Process for making a regenerative-type switching device wherein the active channel is configured to provide, in whole or in part, a vertically conductive pathway between source and drain regions.

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268,for a process of making a vertical channel insulated gate field effect transistor.
  
[List of Patents for class 438 subclass 139]    139Altering electrical characteristic:
 This subclass is indented under subclass 133.  Process having a step of altering an electrical characteristic of the regenerative-type switching device.
  
[List of Patents for class 438 subclass 140]    140Having structure increasing breakdown voltage (e.g., guard ring, field plate, etc.):
 This subclass is indented under subclass 133.  Process for making a regenerative switching device having a structure for increasing the breakdown voltage of the device (e.g., beveled junction, contoured edge, etc.).

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 168+ for a regenerative-type switching device having means to increase breakdown voltage.
  
[List of Patents for class 438 subclass 141]    141MAKING CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR, ETC.):
 This subclass is indented under the class definition.  Process for making a conductivity modulation device structure which has a high resistivity semiconductor region of one conductivity-type having a region of opposite conductivity-type forming a pn junction with a central portion of the high resistivity region, with structural means provided to forward bias the pn junction to inject minority carriers into the high resistivity region to vary its conductivity producing modulated wave response (i.e., conductivity modulation).

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 212 for a conductivity modulation device.
388Electricity: Motor Control Systems,   subclass 919 for unijunction transistor circuit trigger control means.
  
[List of Patents for class 438 subclass 142]    142MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS:
 This subclass is indented under the class definition.  Process for forming or altering a pair of device active regions (i.e., source or drain) separated by a gate structure intended to permit or block the flow of electrical current therebetween.
(1) Note. To be proper hereunder, the claim must include a positive recitation of (a) formation of semiconductive active regions or (b) altering the electrical properties of active semiconductive regions of the substrate.

Image 1 for class 438 subclass 142

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49,for a process of making a chemically sensitive field effect transistor (i.e., CHEMFET.)
  
[List of Patents for class 438 subclass 143]    143Gettering of semiconductor substrate:
 This subclass is indented under subclass 142.  Process including a step of gettering the semiconductor substrate.

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471,for process of gettering a semiconductor substrate, per se.
  
[List of Patents for class 438 subclass 144]    144Charge transfer device (e.g., CCD, etc.):
 This subclass is indented under subclass 142.  Process for making a structure in which storage sites for packets of electrical charge are induced at or below the semiconductor surface by an electric field applied by serially arranged gate electrodes formed thereupon and wherein carrier potential energy per unit charge minima are established at a given storage site and such minima are transferred in a serial manner via an active channel region to one or more adjacent storage sites.
(1) Note. Included herein are devices commonly referred to as charge coupled devices as well as bucket brigade devices.
(2) Note. A field effect device of the charge injection-type (i.e., CID) that transfers the charge in a nonserial manner to the device substrate or the data bus is not proper hereunder.

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75,for a process of making a charge transfer device which is responsive to electromagnetic radiation.
587,for a process of making an array of gate electrodes upon a semiconductor substrate.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 215+ for a charge transfer device structure.
365Static Information Storage and Retrieval,   subclass 183 for a charge coupled memory.
377Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems,   subclasses 57+ for charge transfer device systems.
  
[List of Patents for class 438 subclass 145]    145Having additional electrical device:
 This subclass is indented under subclass 144.  Process for making a charge transfer device structure in combination with an additional electrical device.
  
[List of Patents for class 438 subclass 146]    146Majority signal carrier (e.g., buried or bulk channel, peristaltic, etc.):
 This subclass is indented under subclass 144.  Process for making a charge transfer device structure wherein the transfer of such charge minima is by majority carriers of the semiconductive material (i.e., by electrons in n-type material, and is by holes in p-type semiconductive material).
  
[List of Patents for class 438 subclass 147]    147Changing width or direction of channel (e.g., meandering channel, etc.):
 This subclass is indented under subclass 144.  Process for making a charge transfer device structure wherein the active channel region changes its width or direction throughout all or part of the distance between adjacent storage sites.
  
[List of Patents for class 438 subclass 148]    148Substantially incomplete signal charge transfer (e.g., bucket brigade, etc.):
 This subclass is indented under subclass 144.  Process for making a charge transfer device structure wherein the charge transferred is less than the entire charge stored in the storage site from which it originates.
  
[List of Patents for class 438 subclass 149]    149On insulating substrate or layer (e.g., TFT, etc.):
 This subclass is indented under subclass 142.  Process for making a field effect transistor from a semiconductive layer formed upon an insulating substrate (for example, glass or sapphire) or an insulating layer.

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30,for process of making a device or circuit emissive of nonelectrical signal comprising an array of field effect transistors on an insulating substrate combined with a liquid crystal optical material.
  
[List of Patents for class 438 subclass 150]    150Specified crystallographic orientation:
 This subclass is indented under subclass 149.  Process wherein a given feature of the field effect device on an insulating substrate or layer is formed in a definite crystallographic relationship relative to the insulating substrate or layer or the semiconductor layer thereupon.
  
[List of Patents for class 438 subclass 151]    151Having insulated gate:
 This subclass is indented under subclass 149.  Process for making an insulated gate field effect transistor from a semiconductive layer formed upon an insulating substrate (for example, glass or sapphire) or an insulating layer.
  
[List of Patents for class 438 subclass 152]    152Combined with electrical device not on insulating substrate or layer:
 This subclass is indented under subclass 151.  Process for making a field effect transistor formed on an insulating substrate or layer combined with an additional electrical device which is not formed upon an insulating substrate or layer.
(1) Note. The electrical device not on an insulating substrate or layer is often referred to as a bulk device while the electrical device on the insulating substrate or layer is often referred to as a thin film device with the combined structure either horizontally disposed or vertically stacked (i.e., 3-dimensional).

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155,for a process of making a field effect transistor on an insulating substrate or layer and an additional electrical device on an insulating substrate or layer.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 350+ for an insulated gate field effect device formed on a single crystal semiconductor layer on an insulating substrate combined with a diverse-type device structure.
  
[List of Patents for class 438 subclass 153]    153Complementary field effect transistors:
 This subclass is indented under subclass 152.  Process for making plural field effect transistors of opposite conductivity type (i.e., wherein source and drain regions of a first field effect transistor are of opposite conductivity type to source and drain regions of a second field effect transistor).
  
[List of Patents for class 438 subclass 154]    154Complementary field effect transistors:
 This subclass is indented under subclass 151.  Process for making plural field effect transistors of opposite conductivity type (i.e., wherein source and drain regions of a first field effect transistor are of opposite conductivity type to source and drain regions of a second field effect transistor).
  
[List of Patents for class 438 subclass 155]    155And additional electrical device on insulating substrate or layer:
 This subclass is indented under subclass 151.  Process for making a field effect transistor formed on an insulating layer or substrate combined with an additional electrical device which is also formed on an insulating substrate or layer.
(1) Note. The additional electrical device must be other than an insulated gate field effect transistor if formed utilizing the same semiconductive layer or may be any type of electrical device if formed utilizing a different semiconductive layer with the structure formed referred to as a vertically stacked or 3-dimensional structure.

SEE OR SEARCH THIS CLASS, SUBCLASS:

152,for a process of making a field effect transistor on an insulating substrate or layer and an additional electrical device not on an insulating substrate or layer.
  
[List of Patents for class 438 subclass 156]    156Vertical channel:
 This subclass is indented under subclass 151.  Process for making a junction gate field effect transistor wherein the active channel is configured to provide, in whole or in part, a vertically conductive pathway between source and drain regions.
  
[List of Patents for class 438 subclass 157]    157Plural gate electrodes (e.g., dual gate, etc.):
 This subclass is indented under subclass 151.  Process for making a field effect transistor formed on an insulating layer or substrate wherein plural insulated gate electrodes on either the same or opposite sides of the active channel region serve to control the electrical conduction characteristics of the semiconductive active channel region.

SEE OR SEARCH THIS CLASS, SUBCLASS:

283,for a process of making an insulated gate field effect transistor having either dual gate or opposed gate structure.
  
[List of Patents for class 438 subclass 158]    158Inverted transistor structure:
 This subclass is indented under subclass 151.  Process for making a field effect transistor formed on an insulating substrate or layer wherein the gate electrode of the field effect transistor is formed so as to be in direct contact with the insulating substrate or layer.
  
[List of Patents for class 438 subclass 159]    159Source-to-gate or drain-to-gate overlap:
 This subclass is indented under subclass 158.  Process wherein the source or drain regions or layers of the inverted field effect transistor are formed so as to extend over a portion of the gate electrode formed on the insulating substrate or layer.
  
[List of Patents for class 438 subclass 160]    160Utilizing backside irradiation:
 This subclass is indented under subclass 158.  Process wherein single or multiple layers formed over the gate are patterned by irradiating a photoresist layer with a radiation source located on the opposite side of the substrate from which the gate is formed.
  
[List of Patents for class 438 subclass 161]    161Including source or drain electrode formation prior to semiconductor layer formation (i.e., staggered electrodes):
 This subclass is indented under subclass 151.  Process wherein the source or drain electrodes of the field effect transistor are formed on the insulating substrate or layer prior to the deposition of a semiconductive layer.
  
[List of Patents for class 438 subclass 162]    162Introduction of nondopant into semiconductor layer:
 This subclass is indented under subclass 151.  Process wherein a nonelectrically active impurity (i.e., one that does not change the electrically properties) is introduced into the semiconductive layer.
  
[List of Patents for class 438 subclass 163]    163Adjusting channel dimension (e.g., providing lightly doped source or drain region, etc.):
 This subclass is indented under subclass 151.  Process wherein a particular dimension of the active channel region of the field effect transistor (e.g., thickness, length, etc.) is adjusted.
  
[List of Patents for class 438 subclass 164]    164Semiconductor islands formed upon insulating substrate or layer (e.g., mesa formation, etc.):
 This subclass is indented under subclass 151.  Process wherein the semiconductor layer selectively deposited or deposited and subsequently patterned to form a semiconductive region electrically isolated from laterally adjoining semiconductor regions.
(1) Note. The separate laterally adjacent semiconductor layers are each intended to possess a single field effect transistor and be electrically isolated with respect to one another prior to electrically interconnecting.
  
[List of Patents for class 438 subclass 165]    165Including differential oxidation:
 This subclass is indented under subclass 164.  Process in which the patterning of the semiconductive layer includes a step of oxidizing the semiconductive layer to form regions of differing oxide thickness.
  
[List of Patents for class 438 subclass 166]    166Including recrystallization step:
 This subclass is indented under subclass 151.  Process wherein the crystalline structure of the semiconductive layer is altered or modified (e.g., from amorphous to polycrystalline or single crystalline).

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150,for a process of making a field effect transistor on an insulating substrate or layer having a specified crystallographic orientation.
  
[List of Patents for class 438 subclass 167]    167Having Schottky gate (e.g., MESFET, HEMT, etc.):
 This subclass is indented under subclass 142.  Process for making a field effect transistor which possesses a gate which forms a metal-semiconductor rectifying junction with the underlying semiconductive active channel region.
  
[List of Patents for class 438 subclass 168]    168Specified crystallographic orientation:
 This subclass is indented under subclass 167.  Process wherein a given feature of the Schottky gate field effect device is formed in a definite crystallographic orientation relative to the substrate.
(1) Note. Processes of making a transistor in a semiconductor substrate of given orientation are not sufficient for placement in this subclass.
  
[List of Patents for class 438 subclass 169]    169Complementary Schottky gate field effect transistors:
 This subclass is indented under subclass 167.  Process for making plural Schottky gate field effect transistors of opposite conductivity type (i.e., wherein source and drain regions of a first field effect transistor are of opposite conductivity type to source and drain regions of a second field effect transistor).
  
[List of Patents for class 438 subclass 170]    170And bipolar device:
 This subclass is indented under subclass 167.  Process for making a bipolar transistor in addition to the Schottky gate field effect transistor.
  
[List of Patents for class 438 subclass 171]    171And passive electrical device (e.g., resistor, capacitor, etc.):
 This subclass is indented under subclass 167.  Process for making a Schottky gate field effect transistor having combined therewith an electrical device or element in which charge carriers do not change their energy levels and do not provide electrical rectification, amplification, or switching, but which does react to voltage and current input.
  
[List of Patents for class 438 subclass 172]    172Having heterojunction (e.g., HEMT, MODFET, etc.):
 This subclass is indented under subclass 167.  Process for making a Schottky gate field effect transistor wherein the Schottky gate field effect transistor possesses an interface between two dissimilar semiconductor materials which constitute a junction.
  
[List of Patents for class 438 subclass 173]    173Vertical channel:
 This subclass is indented under subclass 167.  Process for making a Schottky gate field effect transistor wherein the active channel is configured to provide, in whole or in part, a vertically conductive pathway between source and drain regions.
  
[List of Patents for class 438 subclass 174]    174Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.):
 This subclass is indented under subclass 167.  Process for making a Schottky gate field effect transistor having a step of introducing an electrically active dopant species into the semiconductor channel region beneath the gate electrode.
(1) Note. To be proper herein, the transistor channel region must possess semiconductive characteristics prior to the introduction of the dopant.
  
[List of Patents for class 438 subclass 175]    175Buried channel:
 This subclass is indented under subclass 167.  Process for making a Schottky gate field effect transistor wherein the channel formed between the source and drain regions is configured so as to be buried beneath the semiconductor substrate surface.
  
[List of Patents for class 438 subclass 176]    176Plural gate electrodes (e.g., dual gate, etc.):
 This subclass is indented under subclass 167.  Process for making a Schottky gate field effect transistor wherein plural gate electrodes on either the same or opposite side of the active channel region serve to control the electrical conduction characteristics of the semiconductive active channel region.
  
[List of Patents for class 438 subclass 177]    177Closed or loop gate:
 This subclass is indented under subclass 167.  Process for making a Schottky field effect transistor wherein the gate electrode is configured such that it closes upon itself to thereby totally surround one of the device active regions.
  
[List of Patents for class 438 subclass 178]    178Elemental semiconductor:
 This subclass is indented under subclass 167.  Process for making a Schottky gate field effect transistor wherein the gate electrode is formed upon an elemental semiconductor active channel region.
  
[List of Patents for class 438 subclass 179]    179Asymmetric:
 This subclass is indented under subclass 167.  Process for making a Schottky gate field effect transistor wherein the pair of active regions are off-set or nonsymmetrical with respect to the centerline of the Schottky gate electrode.
  
[List of Patents for class 438 subclass 180]    180Self-aligned:
 This subclass is indented under subclass 167.  Process for making a Schottky gate field effect transistor wherein a previously formed device feature is utilized to make device regions in the desired registration to the previously formed feature.
(1) Note. A self-aligned gate is one which is aligned between the source and drain via a masking process which uses the gate material itself to achieve the registration of the related device regions.
  
[List of Patents for class 438 subclass 181]    181Doping of semiconductive region:
 This subclass is indented under subclass 180.  Process wherein a semiconductive region of the substrate is changed in electrical properties by introduction of an electrically active impurity.
  
[List of Patents for class 438 subclass 182]    182T-gate:
 This subclass is indented under subclass 181.  Process wherein a T-shaped gate structure is formed or utilized at any stage in the process.
  
[List of Patents for class 438 subclass 183]    183Dummy gate:
 This subclass is indented under subclass 181.  Process wherein a temporary gate is formed or utilized at any stage in the process and is intended to be removed or have no function in the final device.
  
[List of Patents for class 438 subclass 184]    184Utilizing gate sidewall structure:
 This subclass is indented under subclass 181.  Process wherein a gate sidewall structure is utilized during the doping of semiconductive regions adjacent the gate structure.
(1) Note. The sidewall structure may function as a masking layer or dopant source during the self-aligned doping step.
  
[List of Patents for class 438 subclass 185]    185Multiple doping steps:
 This subclass is indented under subclass 184.  Process including plural steps of doping the semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 186]    186Having junction gate (e.g., JFET, SIT, etc.):
 This subclass is indented under subclass 142.  Process for making a field effect transistor which possesses a gate electrode which forms a PN (rectifying) junction with the semiconductor active channel region.
  
[List of Patents for class 438 subclass 187]    187Specified crystallographic orientation:
 This subclass is indented under subclass 186.  Process wherein a given feature of the junction gate field effect device is formed in a definite crystallographic orientation relative to the substrate.
(1) Note. Processes of making a transistor in a semiconductor substrate of given orientation are not sufficient for placement in this subclass.
  
[List of Patents for class 438 subclass 188]    188Complementary junction gate field effect transistors:
 This subclass is indented under subclass 186.  Process for making plural junction gate field effect transistors of opposite conductivity type (i.e., wherein source and drain regions of a first field effect transistor are of opposite conductivity type to source and drain regions of a second field effect transistor).
  
[List of Patents for class 438 subclass 189]    189And bipolar transistor:
 This subclass is indented under subclass 186.  Process for making a junction gate field effect transistor which additionally contains a bipolar transistor.
  
[List of Patents for class 438 subclass 190]    190And passive device (e.g., resistor, capacitor, etc.):
 This subclass is indented under subclass 186.  Process for making a junction gate field effect transistor having combined therewith an electrical device or component in which charge carriers do not change their energy levels and do not provide electrical rectification, amplification, or switching, but which does react to voltage and current input.
  
[List of Patents for class 438 subclass 191]    191Having heterojunction:
 This subclass is indented under subclass 186.  Process for making a junction gate field effect transistor which possesses an interface between two dissimilar semiconductor materials which constitute a junction.
  
[List of Patents for class 438 subclass 192]    192Vertical channel:
 This subclass is indented under subclass 186.  Process for making a junction gate field effect transistor wherein the active channel is configured to provide, in whole or in part, a vertically conductive pathway between source and drain regions.

SEE OR SEARCH THIS CLASS, SUBCLASS:

347,for a process of making a permeable base bipolar transistor.
  
[List of Patents for class 438 subclass 193]    193Multiple parallel current paths (e.g., grid gate, etc.):
 This subclass is indented under subclass 192.  Process for making a junction gate field effect transistor wherein the junction gate which controls the vertical channel consists of a plurality of parallel current paths.
  
[List of Patents for class 438 subclass 194]    194Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.):
 This subclass is indented under subclass 186.  Process for making a junction gate field effect transistor having a step of introducing an electrically active dopant species into the semiconductor channel region beneath the gate electrode.
(1) Note. To be proper herein, the transistor channel region must possess semiconductive characteristics prior to the introduction of the dopant.
  
[List of Patents for class 438 subclass 195]    195Plural gate electrodes:
 This subclass is indented under subclass 186.  Process for making a junction gate field effect transistor having plural gate electrodes on either the same or opposite side of the active channel region which serve to control the electrical conduction characteristics of the semiconductive active channel region.
  
[List of Patents for class 438 subclass 196]    196Including isolation structure:
 This subclass is indented under subclass 186.  Process for making a junction gate field effect transistor having a structure which serves to at least partially electrically isolate the semiconductor region in which the device is formed from laterally adjacent semiconductive regions.
  
[List of Patents for class 438 subclass 197]    197Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.):
 This subclass is indented under subclass 142.  Process for making a field effect transistor wherein the gate electrode is electrically insulated from the semiconductive substrate, that portion of the semiconductive substrate therebeneath being the active channel region separating source and drain.

SEE OR SEARCH THIS CLASS, SUBCLASS:

151,for a process of making an insulated gate field effect transistor on an insulating substrate or layer
585,for insulated gate metallization processes, per se.
  
[List of Patents for class 438 subclass 198]    198Specified crystallographic orientation:
 This subclass is indented under subclass 197.  Process wherein a given feature of the junction gate field effect device is formed in a definite crystallographic orientation relative to the substrate.
(1) Note. Processes of making a transistor in a semiconductor substrate of given orientation are not sufficient for placement in this subclass.
  
[List of Patents for class 438 subclass 199]    199Complementary insulated gate field effect transistors (i.e., CMOS):
 This subclass is indented under subclass 197.  Process for making plural insulated gate field effect transistors of opposite conductivity type (i.e., wherein source and drain regions of a first field effect transistor are of opposite conductivity type to source and drain regions of a second field effect transistor).
  
[List of Patents for class 438 subclass 200]    200And additional electrical device:
 This subclass is indented under subclass 199.  Process for making complementary insulated gate field effect transistors having combined therewith an additional electrical device.
  
[List of Patents for class 438 subclass 201]    201Including insulated gate field effect transistor having gate surrounded by dielectric (i.e., floating gate):
 This subclass is indented under subclass 200.  Process for making complementary insulated gate field effect transistors having combined therewith an additional insulated gate field effect transistor possessing a gate electrode enclosed by dielectric.
(1) Note. Usually, the floating gate electrode is located (a) above and insulated from the channel region and (b) below and insulated from a controlling gate electrode. A floating gate electrode, due to accumulated electrical influence derived from the controlling gate electrode, provides on-off operation of the channel region. Floating gate arrangements are prevalent in ultraviolet erasable programmable read-only memory devices (i.e., EPROMs)
  
[List of Patents for class 438 subclass 202]    202Including bipolar transistor (i.e., BiCMOS):
 This subclass is indented under subclass 200.  Process for making complementary insulated gate field effect transistors combined with a bipolar transistor.
  
[List of Patents for class 438 subclass 203]    203Complementary bipolar transistors:
 This subclass is indented under subclass 202.  Process for making complementary insulated gate field effect transistors combined with a first bipolar transistor which additionally contains a second bipolar transistor which is of opposite conductivity type to the first bipolar transistor.
  
[List of Patents for class 438 subclass 204]    204Lateral bipolar transistor:
 This subclass is indented under subclass 202.  Process for making complementary insulated gate field effect transistors additionally having a bipolar transistor possessing a horizontal-type structure so that current flow between its emitter and collector regions is parallel to a major surface of the semiconductor substrate.
  
[List of Patents for class 438 subclass 205]    205Plural bipolar transistors of differing electrical characteristics:
 This subclass is indented under subclass 202.  Process for making complementary insulated gate field effect transistors combined with multiple bipolar transistors of differing electrical properties.
  
[List of Patents for class 438 subclass 206]    206Vertical channel insulated gate field effect transistor:
 This subclass is indented under subclass 202.  Process for making complementary insulated gate field effect transistors combined with a bipolar transistor and wherein at least one insulated gate field effect transistor possesses an active channel region which is configured to provide, at least in part, a vertically conductive pathway between source and drain regions.
  
[List of Patents for class 438 subclass 207]    207Including isolation structure:
 This subclass is indented under subclass 202.  Process for making complementary insulated gate field effect transistors combined with a bipolar transistor having a structure serving to at least partially electrically isolate the semiconductive region in which one transistor is formed from laterally adjacent semiconductive regions.
  
[List of Patents for class 438 subclass 208]    208Isolation by PN junction only:
 This subclass is indented under subclass 207.  Process for making complementary insulated gate field effect transistors combined with a bipolar transistor in which the transistors are electrically isolated solely through the use of properly biased PN junctions.
  
[List of Patents for class 438 subclass 209]    209Including additional vertical channel insulated gate field effect transistor:
 This subclass is indented under subclass 200.  Process for making complementary insulated gate field effect transistors having combined therewith an additional field effect transistor having an active channel region configured to provide, at least in part, a vertically conductive pathway between source and drain regions.
  
[List of Patents for class 438 subclass 210]    210Including passive device (e.g., resistor, capacitor, etc.):
 This subclass is indented under subclass 200.  Process for making complementary insulated gate field effect transistors having combined therewith a passive electrical device or element (i.e., an electrical device or component in which charge carriers do not change their energy levels and do not provide electrical rectification, amplification, or switching, but which does react to voltage and current input).
  
[List of Patents for class 438 subclass 211]    211Having gate surrounded by dielectric (i.e., floating gate):
 This subclass is indented under subclass 199.  Process for making complementary insulated gate field effect transistors wherein at least one field effect transistor has an additional insulated gate electrode completely separated by dielectric from its first insulated gate electrode.
(1) Note. Usually, the floating gate electrode is located (a) above and insulated from the channel region and (b) below and insulated from a controlling gate electrode. A floating gate electrode, due to accumulated electrical influence derived from the controlling gate electrode, provides on-off operation of the channel region. Floating gate arrangements are prevalent in ultraviolet erasable programmable read-only memory devices (i.e., EPROMs)
  
[List of Patents for class 438 subclass 212]    212Vertical channel:
 This subclass is indented under subclass 199.  Process for making complementary insulated gate field effect transistors wherein the active channel region of at least one of the transistors is configured to provide, at least in part, a vertically conductive pathway between source and drain regions.

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268,for a process of making a vertical channel insulated gate field effect transistor.
  
[List of Patents for class 438 subclass 213]    213Common active region:
 This subclass is indented under subclass 199.  Process for making complementary insulated gate field effect transistors wherein the transistors share a device active region.
  
[List of Patents for class 438 subclass 214]    214Having underpass or crossunder:
 This subclass is indented under subclass 199.  Process for making complementary insulated gate field effect transistors having an electrically conductive structure located within the semiconductor substrate which functions to electrically connect the transistors.
  
[List of Patents for class 438 subclass 215]    215Having fuse or integral short:
 This subclass is indented under subclass 199.  Process for making complementary field effect transistors having a structure which is alterable from the conductive to nonconductive state or functions to electrically short the transistor structure.
  
[List of Patents for class 438 subclass 216]    216Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound:
 This subclass is indented under subclass 199.  Process for making complementary insulated gate field effect transistors wherein the gate dielectric insulator of at least one of the transistors is constructed of plural diverse dielectrics (e.g., nitride and oxide layers, etc.) or of a nonsilicon containing dielectric compound.
  
[List of Patents for class 438 subclass 217]    217Doping of semiconductor channel region beneath gate insulator (e.g., threshold voltage adjustment, etc.):
 This subclass is indented under subclass 199.  Process having a step of introducing an electrically active dopant species into the semiconductor active channel region beneath the gate insulator of at least one of the complementary insulated gate field effect transistors.
  
[List of Patents for class 438 subclass 218]    218Including isolation structure:
 This subclass is indented under subclass 199.  Process for making complementary field effect transistors having a structure serving to at least partially electrically isolate the semiconductive region in which one transistor is formed from laterally adjacent semiconductive regions.
  
[List of Patents for class 438 subclass 219]    219Total dielectric isolation:
 This subclass is indented under subclass 218.  Process for making complementary insulated gate field effect transistors in which at least one of the insulated gate complementary field effect transistors is fully electrically isolated by dielectric insulative material from laterally adjacent semiconductive regions.
  
[List of Patents for class 438 subclass 220]    220Isolation by PN junction only:
 This subclass is indented under subclass 218.  Process for making complementary insulated gate field effect transistors in which the transistors are electrically isolated solely through the use of properly biased PN junctions.
  
[List of Patents for class 438 subclass 221]    221Dielectric isolation formed by grooving and refilling with dielectric material:
 This subclass is indented under subclass 218.  Process for making complementary insulated gate field effect transistors wherein lateral isolation means is provided by forming a recess into the semiconductor substrate and refilling the recess at least in part with electrically insulative material.
  
[List of Patents for class 438 subclass 222]    222With epitaxial semiconductor layer formation:
 This subclass is indented under subclass 221.  Process for making complementary insulated gate field effect transistors with dielectric isolation formed by grooving and refilling with dielectric material including a step of forming an epitaxial semiconductor layer.
  
[List of Patents for class 438 subclass 223]    223Having well structure of opposite conductivity type:
 This subclass is indented under subclass 221.  Process for making complementary insulated gate field effect transistors including a step of forming a well of opposite conductivity to the adjoining semiconductor region in which well is formed an insulated gate field effect transistor of opposite conductivity type to an insulated gate field effect transistor located in the adjoining semiconductor region.
  
[List of Patents for class 438 subclass 224]    224Plural wells:
 This subclass is indented under subclass 223.  Process for making complementary insulated gate field effect transistors wherein plural wells of the same or opposite conductivity type are formed in the semiconductive substrate, each well utilized for formation therein of an insulated gate field effect transistor.
  
[List of Patents for class 438 subclass 225]    225Recessed oxide formed by localized oxidation (i.e., LOCOS):
 This subclass is indented under subclass 218.  Process for making complementary insulated gate field effect transistors wherein lateral isolation means is provided by a step of selectively oxidizing semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 226]    226With epitaxial semiconductor layer formation:
 This subclass is indented under subclass 225.  Process for making complementary insulated gate field effect transistors with dielectric isolation formed by selectively oxidizing semiconductive regions of the substrate combined with a step of forming an epitaxial semiconductor layer.
  
[List of Patents for class 438 subclass 227]    227Having well structure of opposite conductivity type:
 This subclass is indented under subclass 225.  Process for making complementary insulated gate field effect transistors including a step of forming a well of opposite conductivity to the adjoining semiconductor regions in which well is formed an insulated gate field effect transistor of opposite conductivity type to an insulated gate field effect transistor located in the adjoining semiconductor region.
  
[List of Patents for class 438 subclass 228]    228Plural wells:
 This subclass is indented under subclass 227.  Process for making complementary insulated gate field effect transistors wherein plural wells of the same or opposite conductivity type are formed in the semiconductive substrate, each well utilized for formation therein of an insulated gate field effect transistor.
  
[List of Patents for class 438 subclass 229]    229Self-aligned:
 This subclass is indented under subclass 199.  Process for making complementary insulated gate field effect transistors wherein a previously formed device feature is utilized to make device regions in the desired registration to the previously formed feature.
(1) Note. A self-aligned gate is one which is aligned between the source and drain via a masking process which uses the gate material itself to achieve the registration of related device regions.
  
[List of Patents for class 438 subclass 230]    230Utilizing gate sidewall structure:
 This subclass is indented under subclass 229.  Process with a step of utilizing a structure located on the sidewall of the gate electrode as the previously formed device feature.
  
[List of Patents for class 438 subclass 231]    231Plural doping steps:
 This subclass is indented under subclass 230.  Process including multiple steps of introducing electrically active dopant species into semiconductor regions of the substrate.
  
[List of Patents for class 438 subclass 232]    232Plural doping steps:
 This subclass is indented under subclass 229.  Process including multiple steps of introducing electrically active dopant species into semiconductor regions of the substrate.
  
[List of Patents for class 438 subclass 233]    233And contact formation:
 This subclass is indented under subclass 199.  Process for making complementary insulated gate field effect transistors including a step of forming electrical connections to the transistors.
  
[List of Patents for class 438 subclass 234]    234Including bipolar transistor (i.e., BiMOS):
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor having combined therewith a bipolar transistor.
  
[List of Patents for class 438 subclass 235]    235Heterojunction bipolar transistor:
 This subclass is indented under subclass 234.  Process for making an insulated gate field effect transistor combined with a bipolar transistor wherein the emitter-base junction or the collector-base junction of the bipolar transistor possesses an interface between two dissimilar semiconductor materials.
  
[List of Patents for class 438 subclass 236]    236Lateral bipolar transistor:
 This subclass is indented under subclass 234.  Process for making an insulated gate field effect transistor combined with a bipolar transistor which has a horizontal-type structure resulting in current flow between its emitter and collector regions parallel to a major surface of the semiconductor substrate.
  
[List of Patents for class 438 subclass 237]    237Including diode:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor having combined therewith a diode device or element.
  
[List of Patents for class 438 subclass 238]    238Including passive device (e.g., resistor, capacitor, etc.):
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor having combined therewith an electrical device or component in which charge carriers do not change their energy levels and do not provide electrical rectification, amplification, or switching, but which does react to voltage and current input.

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273,for a process of making an insulated gate field effect transistor which possesses an integral short of the active regions of a single transistor.
  
[List of Patents for class 438 subclass 239]    239Capacitor:
 This subclass is indented under subclass 238.  Process for making an insulated gate field effect transistor having combined therewith a capacitor as the passive device.
  
[List of Patents for class 438 subclass 240]    240Having high dielectric constant insulator (e.g., Ta2O5, etc.):
 This subclass is indented under subclass 239.  Process wherein the capacitor dielectric is constructed of a material having a dielectric constant of greater than 7.5, the dielectric constant of Si3N4.
  
[List of Patents for class 438 subclass 241]    241And additional field effect transistor (e.g., sense or access transistor, etc.):
 This subclass is indented under subclass 239.  Process for making an insulated gate field effect transistor having combined therewith a capacitor and an additional field effect transistor.

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258,for process of making a floating gate-type insulated gate field effect transistor having combined therewith an additional insulated gate field effect transistor.
  
[List of Patents for class 438 subclass 242]    242Including transistor formed on trench sidewalls:
 This subclass is indented under subclass 241.  Process wherein the additional diverse field effect transistor is formed on the side-walls of a groove formed in the semiconductor substrate.
(1) Note. The access transistor serves to sense the storage of electrical charges on the capacitor.
  
[List of Patents for class 438 subclass 243]    243Trench capacitor:
 This subclass is indented under subclass 239.  Process for making an insulated gate field effect transistor combined with a capacitor which is located in a groove in the semiconductor substrate.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 301+ for an insulated gate field effect transistor combined with a trench capacitor.
  
[List of Patents for class 438 subclass 244]    244Utilizing stacked capacitor structure (e.g., stacked trench, buried stacked capacitor, etc.):
 This subclass is indented under subclass 243.  Process wherein the trench capacitor contains a number of capacitor plate regions aligned vertically above each other or wherein the capacitor and the insulated gate field effect transistor are located such that one overlies the other.
  
[List of Patents for class 438 subclass 245]    245With epitaxial layer formed over the trench:
 This subclass is indented under subclass 243.  Process including a step of forming an epitaxial semiconductive layer over the trench region.
  
[List of Patents for class 438 subclass 246]    246Including doping of trench surfaces:
 This subclass is indented under subclass 243.  Process having a step of introducing electrically active dopant species into the surfaces of the groove in which the capacitor is located.

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524,for a process of implanting a dopant into a grooved semiconductive region.
  
[List of Patents for class 438 subclass 247]    247Multiple doping steps:
 This subclass is indented under subclass 246.  Process utilizing plural steps of introducing electrically active dopant species into the trench surfaces.
  
[List of Patents for class 438 subclass 248]    248Including isolating means formed in trench:
 This subclass is indented under subclass 246.  Process including forming a structure functioning as electrical isolation means at the groove bottom.
  
[List of Patents for class 438 subclass 249]    249Doping by outdiffusion from a dopant source layer (e.g., doped oxide, etc.):
 This subclass is indented under subclass 246.  Process wherein doping the trench surfaces is via diffusion from an adjacent dopant source layer formed thereupon.
  
[List of Patents for class 438 subclass 250]    250Planar capacitor:
 This subclass is indented under subclass 239.  Process for making an insulated gate field effect transistor combined with a capacitor wherein a generally planar region of the semiconductive substrate forms a first capacitor plate with the capacitor dielectric and a second capacitor plate formed thereupon.
  
[List of Patents for class 438 subclass 251]    251Including doping of semiconductive region:
 This subclass is indented under subclass 250.  Process having a step of introducing an electrically active dopant species into a semiconductive region of the substrate forming the first capacitor plate.
  
[List of Patents for class 438 subclass 252]    252Multiple doping steps:
 This subclass is indented under subclass 251.  Process having plural steps of introducing electrically active dopant species into a semiconductive region of the substrate forming the first capacitor plate.
  
[List of Patents for class 438 subclass 253]    253Stacked capacitor:
 This subclass is indented under subclass 239.  Process for making an insulated gate field effect transistor in combination with a capacitor containing a number of capacitor plate and dielectric layers deposited successively one atop another and overlying the field effect transistor.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 306+ for an insulated gate field effect transistor combined with a stacked capacitor.
  
[List of Patents for class 438 subclass 254]    254Including selectively removing material to undercut and expose storage node layer:
 This subclass is indented under subclass 253.  Process having a step of selectively removing material (e.g., by etching, etc.) to undercut and expose the capacitor electrode which serves as the storage node layer of the stacked capacitor.
(1) Note. The capacitor electrode on which the electrical charge is stored is referred to as the storage node layer.
  
[List of Patents for class 438 subclass 255]    255Including texturizing storage node layer:
 This subclass is indented under subclass 253.  Process having a step of roughening the surface of the capacitor plate which serves as the storage node layer of the stacked capacitor.
(1) Note. The capacitor electrode on which the electrical charge is stored is referred to as the storage node layer.
  
[List of Patents for class 438 subclass 256]    256Contacts formed by selective growth or deposition:
 This subclass is indented under subclass 253.  Process wherein electrical contacts are formed by selective growth or deposition of conductive material onto the semiconductor substrate.
  
[List of Patents for class 438 subclass 257]    257Having additional gate electrode surrounded by dielectric (i.e., floating gate):
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor wherein an additional gate electrode completely separated by dielectric from a first insulated gate electrode is formed.
(1) Note. Usually, the floating gate electrode is located (a) above and insulated from the channel region and (b) below and insulated from a controlling gate electrode that determines operation of the floating gate electrode. A floating gate electrode, due to accumulated electrical influence derived from the controlling gate electrode, provides on-off operation of the channel region. Floating gate arrangements are prevalent in ultraviolet erasable programmable read-only memory devices (i.e., EPROMs).

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201,for a process of making complementary insulated gate field effect transistors combined with an additional floating gate-type insulated gate field effect transistor.
  
[List of Patents for class 438 subclass 258]    258Including additional field effect transistor (e.g., sense or access transistor, etc.):
 This subclass is indented under subclass 257.  Process for making a floating gate-type insulated gate field effect transistor having combined therewith an additional field effect transistor.

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241,for a process of making an insulated gate field effect transistor combined with a capacitor which structure contains an additional insulated gate field effect transistor.
  
[List of Patents for class 438 subclass 259]    259Including forming gate electrode in trench or recess in substrate:
 This subclass is indented under subclass 257.  Process for making a floating gate type insulated gate field effect transistor including forming a gate electrode in a groove located in the semiconductor substrate.
  
[List of Patents for class 438 subclass 260]    260Textured surface of gate insulator or gate electrode:
 This subclass is indented under subclass 257.  Process for making a floating gate-type insulated gate field effect transistor wherein a roughened surface is utilized for the gate insulator or gate electrode.
  
[List of Patents for class 438 subclass 261]    261Multiple interelectrode dielectrics or nonsilicon compound gate insulator:
 This subclass is indented under subclass 257.  Process for making a floating gate-type insulated gate field effect transistor with plural interelectrode dielectrics or a nonsilicon compound dielectric material.

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287,for a process of making an insulated gate field effect transistor having the gate insulator constructed of diverse dielectrics or of a nonsilicon compound dielectric.
  
[List of Patents for class 438 subclass 262]    262Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.):
 This subclass is indented under subclass 257.  Process for making a floating gate-type insulated gate field effect transistor having elongated source or drain region located under thick oxide dielectric regions.
(1) Note. The regions disposed under the thick oxide regions must be active source or drain regions rather than channel stops serving to electrically isolate laterally spaced FETs.

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294,for a process of making an insulated gate field effect transistor including dielectric isolation structure.
  
[List of Patents for class 438 subclass 263]    263Tunneling insulator:
 This subclass is indented under subclass 262.  Process for making a floating gate type insulated gate field effect transistor including an insulative layer adjacent the gate electrode which allows passage of charge carriers therethrough.
  
[List of Patents for class 438 subclass 264]    264Tunneling insulator:
 This subclass is indented under subclass 257.  Process for making a floating gate-type insulated gate field effect transistor including an insulative layer adjacent the gate electrode which allows passage of charge carriers therethrough.
  
[List of Patents for class 438 subclass 265]    265Oxidizing sidewall of gate electrode:
 This subclass is indented under subclass 257.  Process for making a floating gate-type field effect transistor including a step of forming a dielectric sidewall on the gate electrode by reacting the gate electrode material with oxygen.
  
[List of Patents for class 438 subclass 266]    266Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.):
 This subclass is indented under subclass 257.  Process for making a floating gate-type field effect transistor having an additional, nonmemory control electrode (i.e., having direct electrical contact thereto) or channel portion.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 316 for a floating gate memory device with an additional contacted control electrode.
  
[List of Patents for class 438 subclass 267]    267Including forming gate electrode as conductive sidewall spacer to another electrode:
 This subclass is indented under subclass 266.  Process including a step of forming a conductive electrode on the sidewall of another electrode wherein the conductive sidewall serves as a gate electrode.
  
[List of Patents for class 438 subclass 268]    268Vertical channel:
 This subclass is indented under subclass 197.  Process for making a insulated gate field effect transistor wherein the active channel is configured to provide, in whole or in part, a vertically conductive pathway between source and drain regions.
  
[List of Patents for class 438 subclass 269]    269Utilizing epitaxial semiconductor layer grown through an opening in an insulating layer:
 This subclass is indented under subclass 268.  Process for making an insulated gate field effect transistor wherein a epitaxial semiconductor layer is deposited through an opening in an insulating layer upon a semiconductor substrate.
  
[List of Patents for class 438 subclass 270]    270Gate electrode in trench or recess in semiconductor substrate:
 This subclass is indented under subclass 268.  Process for making an insulated gate field effect transistor wherein the gate electrode is formed in a groove or recess in the semiconductor substrate.

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259,for a process of making a floating gate-type insulated gate field effect transistor having a gate electrode formed in a groove located in the semiconductive substrate.
  
[List of Patents for class 438 subclass 271]    271V-gate:
 This subclass is indented under subclass 270.  Process for making an insulated gate field effect transistor wherein the gate electrode has a V-shape configuration.
  
[List of Patents for class 438 subclass 272]    272Totally embedded in semiconductive layers:
 This subclass is indented under subclass 270.  Process wherein the gate electrode is surrounded on all sides by semiconductive layers.
  
[List of Patents for class 438 subclass 273]    273Having integral short of source and base regions:
 This subclass is indented under subclass 268.  Process for making an insulated gate field effect transistor having an integral electrical connection between the source and base (i.e., substrate) regions.
  
[List of Patents for class 438 subclass 274]    274Short formed in recess in substrate:
 This subclass is indented under subclass 273.  Process wherein the integral short is formed in a groove in the semiconductor substrate
  
[List of Patents for class 438 subclass 275]    275Making plural insulated gate field effect transistors of differing electrical characteristics:
 This subclass is indented under subclass 197.  Process for making multiple insulated gate field effect transistors of differing electrical characteristics.

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128,for processes of selectively wiring an array of electrical devices by completing particular devices of the array or by completion or destruction of conductive pathways between particular devices of the array.
  
[List of Patents for class 438 subclass 276]    276Introducing a dopant into the channel region of selected transistors:
 This subclass is indented under subclass 275.  Process for making plural insulated gate field effect transistors having a step of introducing an electrically active dopant species into the semiconductor channel region beneath the gate insulator of one or more transistors to produce transistors of differing electrical characteristics.

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130,for processes of rendering electrical devices in an array operable or inoperable by electrically completing or electrically shorting designated devices thereof to selectively interconnect the array.
289,for a process of doping the semiconductor channel region beneath gate insulator to (a) produce field effect transistors of identical electrical characteristics or (b) alter the electrical characteristics of a single field effect transistor.
  
[List of Patents for class 438 subclass 277]    277Including forming overlapping gate electrodes:
 This subclass is indented under subclass 276.  Process for making plural insulated gate field effect transistors of differing electrical characteristics including a step of forming overlapping gate electrodes.
  
[List of Patents for class 438 subclass 278]    278After formation of source or drain regions and gate electrode (e.g., late programming, encoding, etc.):
 This subclass is indented under subclass 276.  Process for making plural insulated gate field effect transistors of differing electrical characteristics wherein the semiconductor channel region is doped subsequent to the formation of the source and drain regions and the gate electrode.
  
[List of Patents for class 438 subclass 279]    279Making plural insulated gate field effect transistors having common active region:
 This subclass is indented under subclass 197.  Process for making multiple insulated gate field effect transistors in which a transistor active region is shared between two or more field effect transistors.
  
[List of Patents for class 438 subclass 280]    280Having underpass or crossunder:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor electrically interconnected to an adjoining electrical device via a conductive structure located within the semiconductor substrate.

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214,for a process of making complementary insulated gate field effect transistors combined with an underpass or crossunder.
  
[List of Patents for class 438 subclass 281]    281Having fuse or integral short:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor which possesses a structure alterable to a nonconductive state (i.e., fuse) or an integral electrical connection between source and gate regions or between drain and gate regions.

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132,for a process of making an array of electrical devices and selectively interconnecting the devices via fusible links.
238,for a process of making an insulated gate field effect transistor combined with a resistor.
  
[List of Patents for class 438 subclass 282]    282Buried channel:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor wherein the channel formed between the source and drain regions is configured so as to be located beneath the semiconductor substrate surface.
  
[List of Patents for class 438 subclass 283]    283Plural gate electrodes (e.g., dual gate, etc.):
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor wherein plural gate electrodes on either the same or opposite side of the active channel region serve to control the electrical conduction characteristics of the semiconductive active channel region.

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157,for a process of making an insulated gate field effect transistor upon an insulating substrate or layer wherein the transistor possesses dual gate or opposed gate structure.
  
[List of Patents for class 438 subclass 284]    284Closed or loop gate:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor wherein the gate electrode is configured such that it closes upon itself to thereby totally surround one of the device active regions.
  
[List of Patents for class 438 subclass 285]    285Utilizing compound semiconductor:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor utilizing a compound semiconductor active region.
  
[List of Patents for class 438 subclass 286]    286Asymmetric:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor wherein the pair of active regions are offset or nonsymmetrical with respect to the centerline of the insulated gate electrode.
  
[List of Patents for class 438 subclass 287]    287Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor wherein the gate dielectric insulator is constructed of plural diverse dielectrics (e.g., nitride and oxide, etc.) or of a nonsilicon containing dielectric compound.

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216,for a process of making complementary insulated gate field effect transistors at least one transistor having a gate insulator structure constructed of diverse dielectrics or of nonsilicon compound.
261,for a process of making a floating gate-type insulated gate field effect transistor having multiple interelectrode dielectrics or nonsilicon containing dielectric.
  
[List of Patents for class 438 subclass 288]    288Having step of storing electrical charge in gate dielectric:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor having an active step of storing electrical charge in the gate dielectric insulator.
  
[List of Patents for class 438 subclass 289]    289Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.):
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor having a step of introducing electrically active dopant species into the semiconductor active channel region beneath the gate insulator.

Image 1 for class 438 subclass 289

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276,for a process of doping the semiconductor channel region beneath gate insulator of selected transistors to make plural field effect transistors of differing electrical characteristics.
  
[List of Patents for class 438 subclass 290]    290After formation of source or drain regions and gate electrode:
 This subclass is indented under subclass 289.  Process wherein the semiconductor channel region is doped subsequent to the formation of the source and drain regions and the gate electrode.
  
[List of Patents for class 438 subclass 291]    291Using channel conductivity dopant of opposite type as that of source and drain:
 This subclass is indented under subclass 289.  Process wherein the dopant and the semiconductor active channel region beneath the gate insulator are of the same conductivity type.
  
[List of Patents for class 438 subclass 292]    292Direct application of electrical current:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor having a step of directly applying an electrical current to the semiconductor substrate.

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17,for a step of measuring involving aging electrical devices formed on a semiconductor substrate via the direct application of electrical current.
  
[List of Patents for class 438 subclass 293]    293Fusion or solidification of semiconductor region:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor having a step of fusing or solidifying a semiconductive region of the substrate.
  
[List of Patents for class 438 subclass 294]    294Including isolation structure:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor having a structure which serves to at least partially electrically isolate the semiconductor region in which the device is formed from laterally adjacent semiconductive regions.

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400,for processes of forming an electrically isolated lateral semiconductor structure utilizing dielectric or junction isolation.
  
[List of Patents for class 438 subclass 295]    295Total dielectric isolation:
 This subclass is indented under subclass 294.  Process for making an insulated gate field effect transistor which is fully electrically isolated by dielectric insulative material from laterally adjacent semiconductive regions.
  
[List of Patents for class 438 subclass 296]    296Dielectric isolation formed by grooving and refilling with dielectric material:
 This subclass is indented under subclass 294.  Process for making an insulated gate field effect transistor including the step of forming an isolation structure by making a recess in the semiconductor substrate and refilling the recess with an insulative material.
  
[List of Patents for class 438 subclass 297]    297Recessed oxide formed by localized oxidation (i.e., LOCOS):
 This subclass is indented under subclass 294.  Process for making an insulated gate field effect transistor including the step of oxidizing a selected region of a semiconductive substrate to form an embedded oxide (e.g., field oxide) therein which forms the periphery of a semiconductive region utilized for the formation of the field effect transistor.
  
[List of Patents for class 438 subclass 298]    298Doping region beneath recessed oxide (e.g., to form chanstop, etc.):
 This subclass is indented under subclass 297.  Process including a step of introducing electrically active dopant species into the semiconductor substrate region beneath the recessed oxide (e.g., to form a channel stop thereby preventing electric field inversion beneath the recessed oxide, etc.).
  
[List of Patents for class 438 subclass 299]    299Self-aligned:
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor wherein a previously formed device feature is utilized to make device regions in the desired registration to the previously formed feature.
(1) Note. A self-aligned gate is one which is aligned between the source and drain via a masking process which uses the gate material itself to achieve the registration of the related device regions.
  
[List of Patents for class 438 subclass 300]    300Having elevated source or drain (e.g., epitaxially formed source or drain, etc.):
 This subclass is indented under subclass 299.  Process including a step of forming the source or drain active region at a position above and laterally adjacent to the channel region of the transistor.
  
[List of Patents for class 438 subclass 301]    301Source or drain doping:
 This subclass is indented under subclass 299.  Process having a step for the self-aligned introduction of electrically active dopant species into the semiconductor regions of the substrate to form the transistor source or drain regions or portions thereof.
  
[List of Patents for class 438 subclass 302]    302Oblique implantation:
 This subclass is indented under subclass 301.  Process involving implanting ions other than perpendicularly with respect to the plane of the substrate.
  
[List of Patents for class 438 subclass 303]    303Utilizing gate sidewall structure:
 This subclass is indented under subclass 301.  Process having structure on the sidewall of the gate electrode or gate insulator which is utilized as the previously formed device feature.
  
[List of Patents for class 438 subclass 304]    304Conductive sidewall component:
 This subclass is indented under subclass 303.  Process wherein the gate sidewall structure is composed at least in part of a conductive component.
  
[List of Patents for class 438 subclass 305]    305Plural doping steps:
 This subclass is indented under subclass 303.  Process including multiple steps of introducing dopant species into the semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 306]    306Plural doping steps:
 This subclass is indented under subclass 301.  Process including multiple steps of introducing dopant species into the semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 307]    307Using same conductivity-type dopant:
 This subclass is indented under subclass 306.  Process wherein the same conductivity-type electrically active dopant is introduced using plural doping steps.
  
[List of Patents for class 438 subclass 308]    308Radiation or energy treatment modifying properties of semiconductor regions of substrate (e.g., thermal, corpuscular, electromagnetic, etc.):
 This subclass is indented under subclass 197.  Process for making an insulated gate field effect transistor having a step of irradiating the semiconductor substrate to alter the electrical properties of semiconductive regions thereof.

SEE OR SEARCH THIS CLASS, SUBCLASS:

795,for a process of modifying properties of semiconductive regions of the substrate via radiation or energy treatment.
  
[List of Patents for class 438 subclass 309]    309FORMING BIPOLAR TRANSISTOR BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS:
 This subclass is indented under the class definition.  Process for forming a transistor structure which upon completion possesses a base region separating two or more active regions and in which both positive and negative charge carriers are used to support current flow.

Image 1 for class 438 subclass 309

(1) Note. To be proper hereunder, the claim must include a positive recitation of (a) formation of semiconductive active regions or (b) altering the electrical properties of active semiconductive regions of the substrate.
(2) Note. The regions of a bipolar transistor are commonly referred to as collector, base, and emitter. A bipolar device may alternatively be identified by the semiconductive regions from which the device is formed (i.e., a NPN or PNP device).

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170,for a process of making a Schottky gate field effect transistor combined with a bipolar transistor.
189,for a process of making a junction gate field effect transistor combined with a bipolar transistor.
202,for a process of making complementary insulated gate field effect transistors combined with a bipolar transistor.
234,for a process of making an insulated gate field effect transistor combined with a bipolar transistor.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 47 , 197, 205, 273, 350, 361, 370, 378, 423, 462, 477+, 511, 512, 517, 518, 525, 526, 539+, and 552+ for a bipolar transistor structure.
  
[List of Patents for class 438 subclass 310]    310Gettering of semiconductor substrate:
 This subclass is indented under subclass 309.  Process having a step of gettering the semiconductor substrate.
  
[List of Patents for class 438 subclass 311]    311On insulating substrate or layer (i.e., SOI type):
 This subclass is indented under subclass 309.  Process for making a bipolar transistor wherein the transistor is formed upon an insulating substrate (e.g., glass, sapphire, etc.) or layer.
  
[List of Patents for class 438 subclass 312]    312Having heterojunction:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor wherein the emitter-base or the collector-base junction is an interface of two dissimilar semiconductor materials resulting in a heterojunction therebetween.

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235,for a process of making an insulated gate field effect transistor combined with a heterojunction bipolar transistor.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 197+ for a heterojunction bipolar transistor structure.
  
[List of Patents for class 438 subclass 313]    313Complementary bipolar transistors:
 This subclass is indented under subclass 312.  Process for making a structure which comprises plural bipolar transistors wherein the emitter and collector regions of a first bipolar transistor are of opposite conductivity type to the emitter and collector regions of a second bipolar transistor.(i.e., both pnp and npn bipolar transistor structures), at least one of which possesses a heterojunction.
  
[List of Patents for class 438 subclass 314]    314And additional electrical device:
 This subclass is indented under subclass 312.  Process for making a heterojunction bipolar transistor and an additional electrical device.
  
[List of Patents for class 438 subclass 315]    315Forming inverted transistor structure:
 This subclass is indented under subclass 312.  Process forming a heterojunction bipolar transistor structure in which a semiconductor body such as a semiconductor substrate or a semiconductor layer is used as its emitter region, a first semiconductor region formed in the semiconductor body is used as the base region and a second semiconductor region formed in the first semiconductor region is used as the collector region.
  
[List of Patents for class 438 subclass 316]    316Forming lateral transistor structure:
 This subclass is indented under subclass 312.  Process for making a heterojunction bipolar transistor which has a horizontal structure resulting in current flow between its emitter and collector parallel to a major surface of the semiconductor substrate.
  
[List of Patents for class 438 subclass 317]    317Wide bandgap emitter:
 This subclass is indented under subclass 312.  Process for making a heterojunction bipolar transistor with an active region which involves a charge carrier emitter region made of a semiconductor material having an energy gap between its conduction and valence band which is greater than the energy gap of the dissimilar semiconductor material of the base region.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 198 for a wide band-gap emitter heterojunction bipolar transistor structure.
  
[List of Patents for class 438 subclass 318]    318Including isolation structure:
 This subclass is indented under subclass 312.  Process for making a heterojunction bipolar transistor which has structure so as to at least partially electrically isolate the device from laterally adjacent semiconductor regions.

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353,for an electrical isolation process in a nonheterojunction bipolar device.
  
[List of Patents for class 438 subclass 319]    319Air isolation (e.g., mesa, etc.):
 This subclass is indented under subclass 318.  Process for making a heterojunction bipolar transistor wherein the emitter or collector region of the device is a raised feature with respect to the plane of the substrate.

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343,for a process of making a nonheterojunction bipolar device having a mesa or stacked emitter.
  
[List of Patents for class 438 subclass 320]    320Self-aligned:
 This subclass is indented under subclass 312.  Process for making a heterojunction bipolar transistor wherein a previously formed device feature is utilized to make device regions in the desired registration to the previously formed feature.
  
[List of Patents for class 438 subclass 321]    321Utilizing dummy emitter:
 This subclass is indented under subclass 320.  Process for making a heterojunction bipolar transistor wherein a substitute emitter is formed or removed prior to the forming of the active emitter region of the device.
  
[List of Patents for class 438 subclass 322]    322Complementary bipolar transistors:
 This subclass is indented under subclass 309.  Process for making plural bipolar transistors wherein the emitter and collector regions or a first bipolar transistor are of opposite conductivity type to the emitter and collector regions of a second bipolar transistor.
  
[List of Patents for class 438 subclass 323]    323Having common active region (i.e., integrated injection logic (I2L), etc.):
 This subclass is indented under subclass 322.  Process for making complementary bipolar transistors which possess a common active region.
  
[List of Patents for class 438 subclass 324]    324Including additional electrical device:
 This subclass is indented under subclass 323.  Process for making complementary bipolar transistors with shared common region having combined therewith an additional electrical device.
  
[List of Patents for class 438 subclass 325]    325Having lateral bipolar transistor:
 This subclass is indented under subclass 323.  Process for making complementary bipolar transistors with shared common region wherein at least one of the bipolar transistors has a horizontal structure resulting in current flow between its emitter and collector parallel to a major surface of the semiconductor substrate.
  
[List of Patents for class 438 subclass 326]    326Including additional electrical device:
 This subclass is indented under subclass 322.  Process for making complementary bipolar transistors having combined therewith an additional electrical device.
  
[List of Patents for class 438 subclass 327]    327Having lateral bipolar transistor:
 This subclass is indented under subclass 322.  Process for making complementary bipolar transistors wherein at least one of the bipolar transistors has a horizontal structure resulting in current flow between its emitter and collector parallel to a major surface of the semiconductor substrate.
  
[List of Patents for class 438 subclass 328]    328Including diode:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor having combined therewith a diode.
  
[List of Patents for class 438 subclass 329]    329Including passive device (e.g., resistor, capacitor, etc.):
 This subclass is indented under subclass 309.  Process for making a bipolar transistor having combined therewith an electrical device or component in which charge carriers do not change their energy levels and do not provide electrical rectification, amplification, or switching, but which does react to voltage and current input.
  
[List of Patents for class 438 subclass 330]    330Resistor:
 This subclass is indented under subclass 329.  Process for making a bipolar transistor combined with a resistive element or component.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 539+ , 577, and 582 for bipolar transistor structure combined with a resistive element.
  
[List of Patents for class 438 subclass 331]    331Having same doping as emitter or collector:
 This subclass is indented under subclass 330.  Process wherein the resistor region has the same doping profile (i.e., is formed in the same step) as either the emitter or collector region of the bipolar transistor with which the resistor is combined.
(1) Note. Most resistors in bipolar integrated circuits are formed with the same doping step as the bipolar transistor base regions. Resistors that are instead formed at the same doping step as the emitter or collector, rather than the base, go in this subclass.
  
[List of Patents for class 438 subclass 332]    332Lightly doped junction isolated resistor:
 This subclass is indented under subclass 330.  Process wherein the resistive element is in the form of a lightly doped layer of one conductivity type located in a region of opposite conductivity type, such that the pn junction between the resistor region and its containing opposite conductivity-type region serves to electrically isolate the resistor.
(1) Note. A resistor region is considered to be lightly doped if it is substantially less heavily doped than the base region of the bipolar transistor combined therewith, or if it has a doping density not greater than 100 times that of the opposite conductivity-type region in which it is contained.
  
[List of Patents for class 438 subclass 333]    333Having fuse or integral short:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor which possesses a structure which is alterable from a conductive to a nonconductive state (i.e., fuse) or an integral electrical short between the collector and emitter active regions or between the base and emitter active regions.

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132,for a process of making an array of electrical devices and selectively interconnecting the devices via fusible links.
  
[List of Patents for class 438 subclass 334]    334Forming inverted transistor structure:
 This subclass is indented under subclass 309.  Process forming a bipolar transistor structure in which a semiconductor body such as a semiconductor substrate or a semiconductor layer is used as its emitter region, a first semiconductor region formed in the semiconductor body is used as the base region and a second semiconductor region formed in the first semiconductor region is used as the collector region.

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315,for a process of making a heterojunction bipolar transistor having an inverted structure.
  
[List of Patents for class 438 subclass 335]    335Forming lateral transistor structure:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor wherein the transistor has a horizontal structure resulting in current flow between its emitter and collector parallel to a major surface of the semiconductor substrate.

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204,for a process of making complementary insulated gate field effect transistors combined with a lateral bipolar transistor.
236,for a process of making an insulated gate field effect transistor combined with a lateral bipolar transistor.
327,for a process of making a structure comprising complementary bipolar transistors one of which possesses a lateral transistor structure.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 557+ for a lateral bipolar transistor structure.
  
[List of Patents for class 438 subclass 336]    336Combined with vertical bipolar transistor:
 This subclass is indented under subclass 335.  Process for making a lateral bipolar transistor combined with a vertical bipolar transistor having current flow between its emitter and collector perpendicular to a major surface of the semiconductor substrate.
  
[List of Patents for class 438 subclass 337]    337Active region formed along groove or exposed edge in semiconductor:
 This subclass is indented under subclass 335.  Process for making a lateral bipolar transistor wherein the transistor has a recess or exposed edge and an active region of the transistor is formed along the recess or exposed edge.
  
[List of Patents for class 438 subclass 338]    338Having multiple emitter or collector structure:
 This subclass is indented under subclass 335.  Process for making a lateral bipolar transistor having plural emitter active regions or plural collector active regions.
  
[List of Patents for class 438 subclass 339]    339Self-aligned:
 This subclass is indented under subclass 335.  Process for making a lateral bipolar transistor wherein a previously formed device feature is utilized to make device active regions in the desired registration to the previously formed feature.
  
[List of Patents for class 438 subclass 340]    340Making plural bipolar transistors of differing electrical characteristics:
 This subclass is indented under subclass 309.  Process for making multiple bipolar transistors possessing differing electrical properties.
  
[List of Patents for class 438 subclass 341]    341Using epitaxial lateral overgrowth:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor including forming a single crystalline semiconductor layer epitaxially on the semiconductor substrate and laterally over an insulative layer thereupon.

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481,for a process utilizing fluid growth or deposition of semiconductor active material onto an insulating layer by epitaxial lateral overgrowth.
  
[List of Patents for class 438 subclass 342]    342Having multiple emitter or collector structure:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor having plural emitter active regions or plural collector active regions.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 563+ for multiple separately connected emitter, collector, or base regions in the same transistor structure.
  
[List of Patents for class 438 subclass 343]    343Mesa or stacked emitter:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor wherein the emitter is a raised feature relative to the adjoining semiconductive regions.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 586 for a bipolar transistor structure with a nonplanar semiconductor surface (e.g., groove, mesa, bevel, etc.).
  
[List of Patents for class 438 subclass 344]    344Washed emitter:
 This subclass is indented under subclass 309.  Process wherein the surface of the semiconductive substrate is etched to remove oxide layers formed on the emitter region during emitter diffusion thus allowing an aperature used for diffusing the emitter impurity to be directly utilized as the aperature for electrical contact formation.
  
[List of Patents for class 438 subclass 345]    345Walled emitter:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor wherein the emitter-base junction terminates against a dielectric isolation sidewall.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   especially subclasses 514 and 515 for walled emitter bipolar transistor structure.
  
[List of Patents for class 438 subclass 346]    346Emitter dip prevention or utilization:
 This subclass is indented under subclass 309.  Process involving special diffusion techniques to eliminate or utilize the tendency of the base-collector junction to "bulge" downward during the emitter diffusion.
  
[List of Patents for class 438 subclass 347]    347Permeable or metal base:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor wherein the base region incompletely separates the collector and emitter regions, or is constructed of a metallic material.

SEE OR SEARCH THIS CLASS, SUBCLASS:

192,for a method of making a vertical junction gate field effect transistor.
  
[List of Patents for class 438 subclass 348]    348Sidewall base contact:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor wherein a conductive layer serving as the base electrode makes contact to the sidewall of the base region.
  
[List of Patents for class 438 subclass 349]    349Pedestal base:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor wherein the base region is provided with a projecting portion.
  
[List of Patents for class 438 subclass 350]    350Forming base region of specified dopant concentration profile (e.g., inactive base region more heavily doped than active base region, etc.):
 This subclass is indented under subclass 309.  Process for making a bipolar transistor with a semiconductor base region possessing a specified concentration profile of an electrically active dopant species contained therein.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 592 for a bipolar transistor device having a base region possessing specified doping concentration profile.
  
[List of Patents for class 438 subclass 351]    351Direct application of electrical current:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor involving having a step of directly applying an electric current to the semiconductor substrate.

SEE OR SEARCH THIS CLASS, SUBCLASS:

17,for a step of measuring involving aging electrical devices formed on a semiconductor substrate via the direct application of electrical current.
  
[List of Patents for class 438 subclass 352]    352Fusion or solidification of semiconductor region:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor having a step of fusing or solidifying semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 353]    353Including isolation structure:
 This subclass is indented under subclass 309.  Process for making a bipolar transistor having a structure which serves to at least partially electrically isolate the semiconductive region in which the transistor is formed from laterally adjacent semiconductive regions.

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400,for processes of forming an electrically isolated lateral semiconductor structure utilizing dielectric or junction isolation without a step of bipolar transistor manufacture.
  
[List of Patents for class 438 subclass 354]    354Having semi-insulative region:
 This subclass is indented under subclass 353.  Process for making a bipolar transistor wherein the electrical isolation is provided at least in part by a high resistivity semiconductive component.
  
[List of Patents for class 438 subclass 355]    355Total dielectrical isolation:
 This subclass is indented under subclass 353.  Process for making a bipolar transistor which is fully electrically isolated by dielectric insulative material from laterally adjacent semiconductive regions.
  
[List of Patents for class 438 subclass 356]    356Isolation by PN junction only:
 This subclass is indented under subclass 353.  Process for making a bipolar transistor in a semiconductive region which is completely electrically isolated from laterally spaced regions of the semiconductor substrate solely through the use of properly biased PN junctions.

Image 1 for class 438 subclass 356

  
[List of Patents for class 438 subclass 357]    357Including epitaxial semiconductor layer formation:
 This subclass is indented under subclass 356.  Process for making a junction isolated bipolar transistor utilizing the formation of an epitaxial semiconductor layer.
  
[List of Patents for class 438 subclass 358]    358Up diffusion of dopant from substrate into epitaxial layer:
 This subclass is indented under subclass 357.  Process including a step of diffusing a dopant from the semiconductor substrate into the epitaxial layer form thereupon.
  
[List of Patents for class 438 subclass 359]    359Dielectric isolation formed by grooving and refilling with dielectrical material:
 This subclass is indented under subclass 353.  Process for making a bipolar transistor involving the formation of a recess in the semiconductor followed by the refilling of the recess with an insulative material.
  
[List of Patents for class 438 subclass 360]    360With epitaxial semiconductor formation in groove:
 This subclass is indented under subclass 359.  Process for making a bipolar transistor additionally involving the epitaxial deposition of a semiconductor material in the groove.
  
[List of Patents for class 438 subclass 361]    361Including deposition of polysilicon or noninsulative material into groove:
 This subclass is indented under subclass 359.  Process for making a bipolar transistor wherein a noninsulative material is deposited into the groove in addition to the insulative material.
  
[List of Patents for class 438 subclass 362]    362Recessed oxide by localized oxidation (i.e., LOCOS):
 This subclass is indented under subclass 353.  Process for making a bipolar transistor including the step of oxidizing a portion of a semiconductive material to form an embedded oxide (i.e., field oxide) therein which forms the periphery of a semiconductive region utilized for the formation of the bipolar transistor.
  
[List of Patents for class 438 subclass 363]    363With epitaxial semiconductor layer formation:
 This subclass is indented under subclass 362.  Process for making a bipolar transistor utilizing in addition to the recessed oxide the formation of an epitaxial semiconductor layer.
  
[List of Patents for class 438 subclass 364]    364Self-aligned:
 This subclass is indented under subclass 309.  Process wherein a previously formed device feature is utilized to make device regions in the desired registration to the previously formed feature.
  
[List of Patents for class 438 subclass 365]    365Forming active region from adjacent doped polycrystalline or amorphous semiconductor:
 This subclass is indented under subclass 364.  Process having an active region (e.g., base, emitter, or collector) formed of polycrystalline or amorphous semiconductor.
  
[List of Patents for class 438 subclass 366]    366Having sidewall:
 This subclass is indented under subclass 365.  Process including forming dielectric isolation on the sidewall of the base region to separate the base and collector regions.
  
[List of Patents for class 438 subclass 367]    367Including conductive component:
 This subclass is indented under subclass 366.  Process wherein the sidewall is a combination of conductive and insulative components.
  
[List of Patents for class 438 subclass 368]    368Simultaneously outdiffusing plural dopants from polysilicon or amorphous semiconductor:
 This subclass is indented under subclass 365.  Process including the simultaneous outdiffusing of electrically active dopants from the polysilicon or amorphous active region.
  
[List of Patents for class 438 subclass 369]    369Dopant implantation or diffusion:
 This subclass is indented under subclass 364.  Process having a step of implanting or diffusing an electrically active dopant species into a semiconductive region of the substrate.
  
[List of Patents for class 438 subclass 370]    370Forming buried region (e.g., implanting through insulating layer, etc.):
 This subclass is indented under subclass 369.  Process wherein the dopant is implanted or diffused through an insulating layer.
  
[List of Patents for class 438 subclass 371]    371Simultaneous introduction of plural dopants:
 This subclass is indented under subclass 369.  Process involving the concurrent introduction of multiple dopant species into one or more semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 372]    372Plural doping steps:
 This subclass is indented under subclass 369.  Process having multiple steps of doping semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 373]    373Multiple ion implantation steps:
 This subclass is indented under subclass 372.  Process wherein the plural doping steps are affected by implanting electrically active dopant ions into semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 374]    374Using same conductivity-type dopant:
 This subclass is indented under subclass 373.  Process wherein the same conductivity-type electrically active dopant ion is introduced using plural ion implantation steps.
  
[List of Patents for class 438 subclass 375]    375Forming partially overlapping regions:
 This subclass is indented under subclass 372.  Process wherein the plural doping steps are affected upon localized areas which lap over each other in part.
  
[List of Patents for class 438 subclass 376]    376Single dopant forming regions of different depth or concentrations:
 This subclass is indented under subclass 372.  Process wherein the plural doping steps form regions which differ in amount of impurity or the distance the impurity has to travel inwardly from the surface.
  
[List of Patents for class 438 subclass 377]    377Through same mask opening:
 This subclass is indented under subclass 372.  Process wherein plural doping steps are affected through the same opening in a dopant masking layer.
  
[List of Patents for class 438 subclass 378]    378Radiation or energy treatment modifying properties of semiconductor regions of substrate (e.g., thermal, corpuscular, electromagnetic, etc.):
 This subclass is indented under subclass 309.  Process for making a bipolar transistor having a step of irradiating the semiconductor substrate to alter the electrical properties of semiconductive regions thereof.

SEE OR SEARCH THIS CLASS, SUBCLASS:

795,for a process of modifying properties of semiconductive regions of the substrate via radiation or energy treatment.
  
[List of Patents for class 438 subclass 379]    379VOLTAGE VARIABLE CAPACITANCE DEVICE MANUFACTURE (E.G., VARACTOR, ETC.):
 This subclass is indented under the class definition.  Process for making an active solid-state device wherein the device changes its capacitance depending on the amount of voltage applied thereto.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 312 for an insulated gate FET combined with a voltage variable capacitor, subclass 480 for a Schottky barrier in a voltage variable capacitance diode, and subclasses 595+ for a voltage variable capacitance device.
332Modulators,   subclass 136 for a modulator combined with a voltage variable capacitor.
361Electricity: Electrical Systems and Devices,   subclasses 277+ for a per se voltage variable capacitor (varactor).
  
[List of Patents for class 438 subclass 380]    380AVALANCHE DIODE MANUFACTURE (E.G., IMPATT, TRAPPAT, ETC.):
 This subclass is indented under the class definition.  Process for making a device which is configured to operate in a manner in which an external voltage is applied in the reverse-conducting direction of the semiconductor device junction with sufficient magnitude to cause the potential barrier at the junction to breakdown due to electrons or holes gaining sufficient speed to dislodge valence electrons and thus create more hole-electron current carriers resulting in a sudden change from high dynamic electrical resistance to very low dynamic resistance.
(1) Note. The terms Zener diode and Zener breakdown voltage are used rather loosely in that the breakdown mechanism above about 6 volts is thought to be due to avalanching and that below about 6 volts is thought to be due essentially to tunnelling.

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91,for a process of making a device or circuit which is responsive to a nonelectrical signal and operates in an avalanche breakdown mode.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 199 for an avalanche diode in a noncharge transfer device having a heterojunction, subclass 438 for a light-responsive avalanche junction device, subclass 481 for an avalanche diode having a Schottky barrier, subclass 551 for an avalanche diode used as a voltage reference element combined with pn junction isolation means in an integrated circuit, and subclasses 603+ for avalanche diodes in general.
  
[List of Patents for class 438 subclass 381]    381MAKING PASSIVE DEVICE (E.G., RESISTOR, CAPACITOR, ETC.):
 This subclass is indented under the class definition.  Process for making an electrical device or component utilizing a semiconductor substrate in which charge carriers do not change their energy levels and that does not provide rectification, amplification, or switching, but which does react to voltage and current input.
(1) Note. Formation of a conductive layer of specified resistivity is not sufficient for placement hereunder unless the intent is for the layer to function as a discrete resistor element.
(2) Note. An isolation structure which functions by the application of an electrical bias (e.g., a channel stop, guard ring, or field plate region) is not a passive charge storage element proper here for, nor is the floating gate structure of a field effect device.

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21,for making a device controlled ink jet printhead or thermal printhead.
50,for a process of making a pressure sensitive resistive device.
171,for a process of making a Schottky gate field effect transistor combined with a passive electrical device.
190,for a process of making a junction gate field effect transistor combined with a passive electrical device.
210,for a process of making complementary insulated gate field effect transistors combined with a passive electrical device.
238,for a process of making an insulated gate field effect transistor combined with a passive electrical device.
329,for a process of making a bipolar transistor combined with a passive electrical device.
379,for a process of making a voltage variable capacitance device.

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264Plastic and Nonmetallic Article Shaping or Treating: Processes,   subclass 61 for methods of vitrifying or sintering of inorganic preform to make a discrete passive device (e.g., multilayer ceramic capacitor, etc.).
  
[List of Patents for class 438 subclass 382]    382Resistor:
 This subclass is indented under subclass 381.  Process involving the manufacture of an electrically resistive element utilizing a semiconductor substrate.

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21,for a process of making an electrical resistor-type thermal printhead.
50,for a process of making a resistor responsive to physical stress.
238,for a process of making an insulated gate field effect transistor combined with a resistor device or element.
330,for making a bipolar transistor combined with a resistor device or element.
  
[List of Patents for class 438 subclass 383]    383Lightly doped junction isolated resistor:
 This subclass is indented under subclass 382.  Process wherein the resistive element is in the form of a lightly doped layer of one conductivity type located in a region of opposite conductivity type, such that the pn junction between the resistor region and its containing opposite conductivity-type region serves to electrically isolate the resistor.
  
[List of Patents for class 438 subclass 384]    384Deposited thin film resistor:
 This subclass is indented under subclass 382.  Process wherein the resistor is formed by the deposition of resistive material upon the semiconductor substrate.

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427Coating Processes,   especially subclasses 96.1 through 99.5for a process of coating a nonsemiconductive substrate to produce an integrated or printed circuit or circuit board and subclasses 101-103 for a process of coating a nonsemiconductive substrate to produce a resistor for current control (excludes heating element).
  
[List of Patents for class 438 subclass 385]    385Altering resistivity of conductor:
 This subclass is indented under subclass 384.  Process wherein the electrical resistivity of a conductive material (i.e., metallization) is altered subsequent to deposition.
  
[List of Patents for class 438 subclass 386]    386Trench capacitor:
 This subclass is indented under subclass 381.  Process for making a capacitor located in a groove in a semiconductive substrate.
  
[List of Patents for class 438 subclass 387]    387Having stacked capacitor structure (e.g., stacked trench, buried stacked capacitor, etc.):
 This subclass is indented under subclass 386.  Process wherein the trench capacitor contains a number of capacitor plate regions aligned vertically above each other.
  
[List of Patents for class 438 subclass 388]    388With epitaxial layer formed over the trench:
 This subclass is indented under subclass 386.  Process for making a trench capacitor including a step of forming an epitaxial semiconductive layer over the trench region.
  
[List of Patents for class 438 subclass 389]    389Including doping of trench surfaces:
 This subclass is indented under subclass 386.  Process for making a trench capacitor having a step of introducing electrically active dopant species into a surface (i.e., sidewall or bottom) of the trench in which the capacitor is located.

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524,for a process of implanting a dopant into a grooved semiconductive region.
  
[List of Patents for class 438 subclass 390]    390Multiple doping steps:
 This subclass is indented under subclass 389.  Process for making a trench capacitor utilizing plural doping steps.
  
[List of Patents for class 438 subclass 391]    391Including isolating means formed in trench:
 This subclass is indented under subclass 389.  Process for making a trench capacitor having structure functioning as electrical isolation formed in the trench bottom.
  
[List of Patents for class 438 subclass 392]    392Doping by outdiffusion from a dopant source layer (e.g., doped oxide):
 This subclass is indented under subclass 389.  Process for making a trench capacitor wherein the trench surfaces are doped via outdiffusion from a doped source layer.
  
[List of Patents for class 438 subclass 393]    393Planar capacitor:
 This subclass is indented under subclass 386.  Process for making a capacitor wherein a generally planar region of a semiconductive substrate forms a first capacitor plate with a dielectric layer and a second capacitor plate formed thereupon.
  
[List of Patents for class 438 subclass 394]    394Including doping of semiconductive region:
 This subclass is indented under subclass 393.  Process for making a planar capacitor having a step of introducing electrically active dopant species into a semiconductive region of the substrate forming the first capacitor plate.
  
[List of Patents for class 438 subclass 395]    395Multiple doping steps:
 This subclass is indented under subclass 394.  Process for making a planar capacitor utilizing plural steps of incorporating electrically active dopant species into a semiconductive region of the substrate forming the first capacitor plate.
  
[List of Patents for class 438 subclass 396]    396Stacked capacitor:
 This subclass is indented under subclass 386.  Process for making a capacitor containing a number of capacitor plate and dielectric layers deposited successively one atop another.
  
[List of Patents for class 438 subclass 397]    397Including selectively removing material to undercut and expose storage node layer:
 This subclass is indented under subclass 396.  Process for making a stacked capacitor having a step of selectively removing material to undercut and expose the capacitor electrode which serves as the storage node layer.
(1) Note. The capacitor electrode on which the electrical charge is stored is referred to as the storage node layer.
  
[List of Patents for class 438 subclass 398]    398Including texturizing storage node layer:
 This subclass is indented under subclass 396.  Process for making a stacked capacitor having a step of roughening the surface of the capacitor plate which serves as the storage node layer.
(1) Note. The capacitor electrode on which the electrical charge is stored is referred to as the storage node layer.
  
[List of Patents for class 438 subclass 399]    399Having contacts formed by selective growth or deposition:
 This subclass is indented under subclass 396.  Process for making a stacked capacitor wherein electrical contacts are formed by selective growth or deposition of conductive material onto the substrate.
  
[List of Patents for class 438 subclass 400]    400FORMATION OF ELECTRICALLY ISOLATED LATERAL SEMICONDUCTIVE STRUCTURE:
 This subclass is indented under the class definition.  Process for making partial or total electrical isolation means serving to minimize electrical current flow between laterally adjoining semiconductive regions of the substrate.
(1) Note. To be proper hereunder, the proximate function of the formed semiconductor structure must be to electrically isolate laterally adjoining semiconductive regions, wherein each region is adapted for the construction of an electrical device.

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49,for a process of manufacturing a regenerative switching device having a guard ring or field plate component.
196,for a process of making a junction gate field effect transistor having an electrical isolation structure.
207,for a process of making a structure combining complementary insulated gate field effect transistors with a bipolar transistor (BiCMOS) additionally having an electrical isolation structure.
218,for a process of making a structure having complementary insulated gate field effect transistors (CMOS) additionally having an electrical isolation structure.
294,for a process of manufacturing an insulated gate field effect transistor having an electrical isolation structure.
353,for a process of manufacturing a bipolar transistor having an electrical isolation structure.
455,for a process in which plural semiconductive substrates are joined together with insulative material to provide layered semiconductive regions which may be electrically isolated from one another.
479,for a process involving fluid growth of a layer of semiconductive material upon an insulative substrate (i.e., SOI formation).

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclasses 499+ for an integrated circuit structure with electrically isolated components.
  
[List of Patents for class 438 subclass 401]    401Having substrate registration feature (e.g., alignment mark):
 This subclass is indented under subclass 400.  Process wherein the process of forming electrical isolation utilizes an alignment feature formed on the semiconductive substrate or forms an alignment feature for subsequent use.
  
[List of Patents for class 438 subclass 402]    402And gettering of substrate:
 This subclass is indented under subclass 400.  Process for making laterally spaced electrically isolated semiconductor regions having a step of gettering a semiconductor substrate.
  
[List of Patents for class 438 subclass 403]    403Having semi-insulating component:
 This subclass is indented under subclass 400.  Process for making laterally spaced electrically isolated semiconductor regions wherein a high resistivity semiconductive component serves to electrically isolate, at least in part, the laterally spaced regions.
  
[List of Patents for class 438 subclass 404]    404Total dielectric isolation:
 This subclass is indented under subclass 400.  Process for making laterally spaced electrically isolated semiconductor regions wherein the semiconductive regions are fully electrically isolated by dielectric insulative material.

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219,for a process of making complementary insulated gate field effect transistors having total dielectric isolation means.
295,for a process of making an insulated gate field effect transistor having total dielectric isolation means.
355,for a process of making a bipolar transistor having total dielectric isolation means.
  
[List of Patents for class 438 subclass 405]    405And separate partially isolated semiconductor regions:
 This subclass is indented under subclass 404.  Process for making a total dielectric isolation semiconductor structure additionally having laterally spaced semiconductor regions at least one of which is fully electrically isolated from other laterally spaced semiconductive regions and at least one other region which is partially electrically isolated from another laterally spaced semiconductive region.
  
[List of Patents for class 438 subclass 406]    406Bonding of plural semiconductive substrates:
 This subclass is indented under subclass 404.  Process for making a total dielectric isolation semiconductor structure including a step of joining plural semiconductive substrates together into a coherent monolith, such as by thermal treatment.

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455,for a process of laminating or bonding of plural semiconductive substrates not resulting in an electrically isolated lateral semiconductor structure.
  
[List of Patents for class 438 subclass 407]    407Nondopant implantation:
 This subclass is indented under subclass 404.  Process for making a total dielectric isolation semiconductor structure including a step of ion implantation of a nonelectrically active impurity into a semiconductive region of the substrate.
(1) Note. The nondopant may react with the semiconductor region to produce a dielectric material embedded in the semiconductor region.
  
[List of Patents for class 438 subclass 408]    408With electrolytic treatment step:
 This subclass is indented under subclass 404.  Process for making a total dielectric isolation semiconductor structure including a step of electrochemical treatment of the semiconductor substrate (i.e., such as to affect etching or coating action thereupon).
  
[List of Patents for class 438 subclass 409]    409Porous semiconductor formation:
 This subclass is indented under subclass 408.  Process wherein the electrolytic treatment results in the formation of a porous semiconductor component.
  
[List of Patents for class 438 subclass 410]    410Encroachment of separate locally oxidized regions:
 This subclass is indented under subclass 404.  Process for making a total dielectric isolation semiconductor structure including a step of oxidation of adjacent semiconductive regions whereby the oxidized regions acquire a touching relationship.
  
[List of Patents for class 438 subclass 411]    411Air isolation (e.g., beam lead supported semiconductor islands, etc.):
 This subclass is indented under subclass 404.  Process for making a total dielectric isolation structure wherein the resulting structure has islands of semiconductor material supported by beam leads and separated by air.

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461,for a process of depositing electrically conductive material to a semiconductive substrate and subsequently removing portions of the substrate to separate the same into beam leaded semiconductor devices.
619,for process of depositing an electrically conductive structure (i.e., metallization) upon a semiconductive substrate contacting spaced regions thereupon utilizing an air-gap dielectric.

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257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 522 for an air bridge isolated integrated circuit structure.
  
[List of Patents for class 438 subclass 412]    412Semiconductor islands formed upon insulating substrate or layer (e.g., mesa isolation, etc.):
 This subclass is indented under subclass 411.  Process for making a total dielectric isolation semiconductor structure wherein laterally spaced semiconductor islands are formed upon an insulative substrate or layer.
  
[List of Patents for class 438 subclass 413]    413With epitaxial semiconductor formation:
 This subclass is indented under subclass 404.  Process for making a total dielectric isolation semiconductor structure having a step of epitaxially depositing a semiconductive layer onto the substrate.
  
[List of Patents for class 438 subclass 414]    414Isolation by PN junction only:
 This subclass is indented under subclass 400.  Process whereby the laterally spaced regions of the semiconductor substrate are electrically isolated solely through the use of properly biased PN junctions.
  
[List of Patents for class 438 subclass 415]    415Thermomigration:
 This subclass is indented under subclass 414.  Process for making junction isolated laterally spaced semiconductor regions having a step of dopant migration under the influence of a temperature gradient.
  
[List of Patents for class 438 subclass 416]    416With epitaxial semiconductor formation:
 This subclass is indented under subclass 414.  Process for making junction isolated laterally spaced semiconductor regions having a step of epitaxially depositing a semiconductor layer.
  
[List of Patents for class 438 subclass 417]    417And simultaneous polycrystalline growth:
 This subclass is indented under subclass 416.  Process for making junction isolated laterally spaced semiconductor regions in which polycrystalline semiconductive regions are deposited simultaneously with the epitaxial deposition.
  
[List of Patents for class 438 subclass 418]    418Dopant addition:
 This subclass is indented under subclass 416.  Process for making junction isolated laterally spaced semiconductor regions including a step of introducing an electrically active dopant species into semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 419]    419Plural doping steps:
 This subclass is indented under subclass 418.  Process for making junction isolated laterally spaced semiconductor regions including multiple steps of introducing an electrically active dopant species into semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 420]    420Plural doping steps:
 This subclass is indented under subclass 414.  Process for making an junction isolated laterally spaced semiconductor regions including multiple steps of introducing an electrically active dopant species into semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 421]    421Having air-gap dielectric (e.g., groove, etc.):
 This subclass is indented under subclass 400.  Process for making an electrically isolated laterally spaced semiconductor structure resulting in laterally spaced semiconductive regions separated at least in part by a recessed air-gap feature relative to the surrounding surface (e.g., groove, trench, notch, etc.).

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411,for a process of forming a total dielectric isolation structure utilizing air isolation.
  
[List of Patents for class 438 subclass 422]    422Enclosed cavity:
 This subclass is indented under subclass 421.  Process wherein the air-gap dielectric is in the form of an enclosed cavity or void between the laterally spaced semiconductive regions.
  
[List of Patents for class 438 subclass 423]    423Implanting to form insulator:
 This subclass is indented under subclass 400.  Process for making an electrically isolated laterally spaced semiconductor structure including a step of implanting a nonelectrically active dopant species to form an insulative region which serves to electrically isolate lateral semiconductive regions.

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407,for a process of forming total dielectric isolation with a step of implanting a nondopant ion.
766,for a process of forming a buried insulative region by ion implantation of a nondopant species.
  
[List of Patents for class 438 subclass 424]    424Grooved and refilled with deposited dielectric material:
 This subclass is indented under subclass 400.  Process for making electrically isolated laterally spaced semiconductor regions including a step of forming a recess or trench in the semiconductive substrate and refilling the same with deposited insulative material.
  
[List of Patents for class 438 subclass 425]    425Combined with formation of recessed oxide by localized oxidation:
 This subclass is indented under subclass 424.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material including the step of forming an embedded oxide by localized oxidation (of semiconductor material).
(1) Note. To be proper herein, the locally oxidized regions must consume semiconductor regions of the substrate (i.e., other than the oxidation solely of deposited layers residing within the groove). Additionally, the uppermost surface of the embedded oxide must be physically below the adjoining semiconductor top surface.

Image 1 for class 438 subclass 425

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444,for a process of forming a recessed oxide electrical isolation structure by localized oxidation including a preliminary step of forming a groove into the semiconductor substrate.
  
[List of Patents for class 438 subclass 426]    426Recessed oxide laterally extending from groove:
 This subclass is indented under subclass 425.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material whereby the embedded oxidized region extends laterally from the groove region.

Image 1 for class 438 subclass 426

  
[List of Patents for class 438 subclass 427]    427Refilling multiple grooves of different widths or depths:
 This subclass is indented under subclass 424.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material wherein grooves of differing widths or depths are filled with insulative material.
  
[List of Patents for class 438 subclass 428]    428Reflow of insulator:
 This subclass is indented under subclass 427.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material including a step of redistributing insulative material by the viscous flow of the insulative material when exposed to high temperature.
  
[List of Patents for class 438 subclass 429]    429And epitaxial semiconductor formation in groove:
 This subclass is indented under subclass 424.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material including a step of epitaxially depositing semiconductive material in the groove.
  
[List of Patents for class 438 subclass 430]    430And deposition of polysilicon or noninsulative material into groove:
 This subclass is indented under subclass 424.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material wherein polysilicon or noninsulative material is deposited into the groove.
  
[List of Patents for class 438 subclass 431]    431Oxidation of deposited material:
 This subclass is indented under subclass 430.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material including a step of oxidizing the polysilicon or noninsulative material deposited into the groove.
  
[List of Patents for class 438 subclass 432]    432Nonoxidized portions remaining in groove after oxidation:
 This subclass is indented under subclass 431.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material wherein at least a portion of the polysilicon or noninsulative material deposited into the groove remains after the oxidation step.
  
[List of Patents for class 438 subclass 433]    433Dopant addition:
 This subclass is indented under subclass 424.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material combined with a step of introducing an electrically active dopant species into a semiconductive region of the substrate.
  
[List of Patents for class 438 subclass 434]    434From doped insulator in groove:
 This subclass is indented under subclass 433.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material wherein the semiconductor regions are doped from a doped insulator residing in the groove.
  
[List of Patents for class 438 subclass 435]    435Multiple insulative layers in groove:
 This subclass is indented under subclass 424.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with plural insulative layers.
  
[List of Patents for class 438 subclass 436]    436Reflow of insulator:
 This subclass is indented under subclass 435.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material including a step of redistributing insulative material by the viscous flow of the insulative material when exposed to high temperature.
  
[List of Patents for class 438 subclass 437]    437Conformal insulator formation:
 This subclass is indented under subclass 435.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material including forming an insulative layer which follows the contour of the groove.
  
[List of Patents for class 438 subclass 438]    438Reflow of insulator:
 This subclass is indented under subclass 424.  Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material including a step of redistributing insulative material by the viscous flow of the insulative material when exposed to high temperature.
  
[List of Patents for class 438 subclass 439]    439Recessed oxide by localized oxidation (i.e., LOCOS):
 This subclass is indented under subclass 400.  Process for making electrically isolated laterally spaced semiconductor regions including the step of oxidizing a portion of a semiconductive material to form an embedded oxide (e.g., field oxide) therein which isolates the laterally adjacent semiconductive regions.
  
[List of Patents for class 438 subclass 440]    440Including nondopant implantation:
 This subclass is indented under subclass 439.  Process including a step of ion implanting a nonelectrically active impurity species into any region of the semiconductor substrate.
(1) Note. The nondopant may serve to alter the oxidation rate of the implanted region.

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423,for a process of forming a laterally spaced isolation structure involving the implantation of an ion which reacts with the substrate to form an insulative material.
  
[List of Patents for class 438 subclass 441]    441With electrolytic treatment step:
 This subclass is indented under subclass 439.  Process including a step of electrochemical treatment of the semiconductor substrate (e.g., such as to affect etching or coating action thereon).
  
[List of Patents for class 438 subclass 442]    442With epitaxial semiconductor layer formation:
 This subclass is indented under subclass 439.  Process including a step of epitaxially growing a single crystal semiconductor layer on the substrate.
  
[List of Patents for class 438 subclass 443]    443Etchback of recessed oxide:
 This subclass is indented under subclass 439.  Process having a step of thinning the formed recessed oxide by chemical etching action followed by an additional step of oxidizing a semiconductive region of the substrate.
  
[List of Patents for class 438 subclass 444]    444Preliminary etching of groove:
 This subclass is indented under subclass 439.  Process including a preliminary step of etching a trench into the semiconductive substrate followed by locally oxidizing the trench surfaces to form the recessed oxide therein.

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421,for a process of forming electrically isolated lateral semiconductive regions utilizing an air-gap separation.
425,for a process of forming a grooved and refilled electrical isolation structure including a step of forming an embedded localized oxidation region of the semiconductor substrate within or adjoining the groove.
  
[List of Patents for class 438 subclass 445]    445Masking of groove sidewall:
 This subclass is indented under subclass 444.  Process utilizing a layer in contact with the groove sidewalls which serves as a protective covering during either an etching or oxidation step.
  
[List of Patents for class 438 subclass 446]    446Polysilicon containing sidewall:
 This subclass is indented under subclass 445.  Process utilizing a polysilicon containing component for masking the groove sidewalls.
  
[List of Patents for class 438 subclass 447]    447Dopant addition:
 This subclass is indented under subclass 444.  Process including a step of introducing an electrically active dopant species into semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 448]    448Utilizing oxidation mask having polysilicon component:
 This subclass is indented under subclass 439.  Process utilizing a layer in contact with the substrate having a polysilicon containing component which serves as a protective covering during the localized oxidation step.
  
[List of Patents for class 438 subclass 449]    449Dopant addition:
 This subclass is indented under subclass 439.  Process including a step of introducing an electrically active dopant species into semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 450]    450Implanting through recessed oxide:
 This subclass is indented under subclass 449.  Process wherein the dopant species is implanted through the recessed oxide into the semiconductive regions therebeneath.
  
[List of Patents for class 438 subclass 451]    451Plural doping steps:
 This subclass is indented under subclass 449.  Process utilizing multiple steps of doping semiconductive regions of the substrate.
  
[List of Patents for class 438 subclass 452]    452Plural oxidation steps to form recessed oxide:
 This subclass is indented under subclass 439.  Process having multiple steps of oxidizing the semiconductor substrate in the region of the recessed oxide.
  
[List of Patents for class 438 subclass 453]    453And electrical conductor formation (i.e., metallization):
 This subclass is indented under subclass 439.  Process including a step of making an electrically conductive member integral to the semiconductive substrate.
(1) Note. The contact may be, for example, directly to semiconductive regions of the substrate or may reside atop the field oxide isolation structure.

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584,for a process of depositing electrically or thermally conductive material on a semiconductor substrate.
  
[List of Patents for class 438 subclass 454]    454Field plate electrode:
 This subclass is indented under subclass 400.  Process having a step of forming an electrically conductive structure formed on a major surface of the semiconductor substrate for electrically separating laterally positioned device regions.

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584,for a process of depositing electrically or thermally conductive material on a semiconductor substrate.
  
[List of Patents for class 438 subclass 455]    455BONDING OF PLURAL SEMICONDUCTOR SUBSTRATES:
 This subclass is indented under the class definition.  Process in which plural semiconductive substrates are joined together into a coherent body, such as by thermal treatment.
(1) Note. Connection of electrical terminals on transposed semiconductive substrates by joining the respective terminals on one substrate to the terminals on a second substrate (e.g., flip-chip bonding, etc.) is a packaging operation and as such cross-referencing hereunder is discouraged.

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107,for a process of packaging (e.g., mounting, encapsulating, etc.) involving the assembly of plural semiconductive substrates or the treating of a packaged device containing the same.
406,for a process of making a full electrical isolation structure including a laminating step whereby current flow will be minimized between laterally adjoining semiconductive regions.

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65Glass Manufacturing,   particularly subclasses 36+ for