Class Definition for Class 438 - SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

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CLASS 438,	SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS
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SECTION I - CLASS DEFINITION

A. This class provides for manufacturing a semiconductor containing a solid-state device by a combination of operations wherein:

(1) no other class provides for the overall combination, and

(2) the intent is to use the electrical properties of the semiconductor in the device for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.

B. This class provides for a species of Class 427 operations involving:

(1) coating a substrate with a semiconductive material, or

(2) coating a semiconductive substrate or substrate containing a semiconductive region;

wherein the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.

C. This class provides for a species of Class 216 operations involving etching a semiconductive substrate or etching a substrate containing a semiconductive region, wherein the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes:

(1) conducting or modifying an electrical current,

(2) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or

(3) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.

D. This class provides for packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor, when not elsewhere provided, wherein there are:

(1) multiple operations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor, or support (e.g., mounting, housing, lead frame, discrete heat sink, etc.),

(2) multiple operations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or

(3) a step of treating an already packaged semiconductor substrate (e.g., coating, etching, etc.); if the following conditions are also met: (a) there is significant semiconductor chip structure (e.g., such as recited semiconductor junction, etc.) or named semiconductor device (e.g., DRAM, CMOS, EPROM, etc.), or (b) there is no significant semiconductor structure if also combined with a coating operation of this class (see B above) or etching operation of this class (see C above), and (c) the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes: (i) conducting or modifying an electrical current, (ii) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (iii) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy;

(1) Note. When Class 438 coating (see B above) or etching operations (see C above) are not included, Class 29, following historical precedence, provides for processes of mounting, packaging, molding, or encapsulating of semiconductors having no significant semiconductor chip structure (e.g., merely recited as semiconductor chip, per se, etc.) when not elsewhere provided. E. This is the generic class for operations not elsewhere provided for treating a semiconductive substrate or substrate containing a semiconductive region; wherein the intent is to use the semiconductor in a solid-state device for at least one of the following purposes: (1) conducting or modifying an electrical current, (2) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (3) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.

(1) Note. Lacking an indication that the semiconducting material is to be used for a purpose other than (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy; it will be assumed that the process meets the Class 438 definition.

(2) Note. For this class certain materials will be considered to be semiconductors even if there is no other indication that semiconducting properties are present. Thus, if the criteria set forth under the (1) Note is met that there is no indication that the material is to be used for a purpose other than (a), (b), or (c), the following materials are to be considered semiconductive: silicon, germanium, selenium, tellurium, gallium nitride, gallium phosphide, gallium arsenide, aluminum phosphide, aluminum arsenide, and mercury cadmium telluride.

SECTION II - LINES WITH OTHER CLASSES AND WITHIN THIS CLASS

Several classes provide for plural step operations for manufacturing semiconductor solid-state devices or components therefor. Combined operations for manufacturing semiconductor electrical devices or semiconductor-based components therefor having plural steps not encompassed by another class are proper for Class 438.

For example, while plural steps acceptable to Class 264 (e.g., injection molding and subsequent removal of flash, etc.) remain in Class 264, combinations of molding and adhesive bonding are provided for in Class 156, even though this involves multiple steps, one of which (i.e., molding) would be considered a Class 264 unit operation even if semiconductor material is involved. However, combinations of molding, adhesive bonding, and a Class 438 unit operation acting on a semiconductor substrate which is used for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy, are considered proper for Class 438.

A. UNIT COATING OPERATIONS, COMBINED OPERATIONS INVOLVING COATING, AND PARTICLE BOMBARDMENT

The following search notes are intended to clarify the lines and distinctions for determining when coating operations are provided for in Class 438. Throughout this class, the term "coating" is used in the generic sense to include both surface coating and impregnation.

The unit coating operations in Class 438 may be viewed as a specie of a Class 427 process which was removed intact from Class 427 and transferred to Class 438 for the convenience of the searcher. Thus, plural step operations that were acceptable in Class 427 are now acceptable in Class 438 if the criteria for the semiconductor material as set forth hereinabove is met. Coating operations which do not meet the Class 438 definition may be classified in the classes identified in References to Other Classes, below.

B. UNIT ETCHING OPERATIONS AND COMBINED ETCHING OPERATIONS IN CLASS 438

In References to Other Classes, below, are search notes are intended to clarify the lines and distinctions for determining when an etching unit operation is provided for in Class 438. Throughout this class, the term "etching" is used in the generic sense to include the removal of a surface by chemical reaction or solvent action regardless of the composition thereof.

The unit etching operations in Class 438 may be viewed as a specie of a Class 216 process which was removed intact from Class 216 and transferred to Class 438 for the convenience of the searcher. Thus, plural step operations that were acceptable in Class 216 are now acceptable in Class 438 if the criteria for the semiconductor material as set forth hereinabove is met. Etching operations which do not meet the Class 438 definition may be found in References with Other Classes, below.

C. PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR

Packaging is a semiconductor art manufacturing term for integration, assembly, or surrounding of a semiconductive substrate (e.g., chip, die, etc.) with a permanent encasement, housing, capsule, or support. This is distinguished from package making found in Class 53 which is directed to preparing a manufactured product for passage through the channels of trade in a safe, convenient, and attractive condition, usually wrapped in a cover or in a container which is intended to be removed when the manufactured product is used.

Class 438 takes the following packaging or packaging related operations, if not elsewhere provided: (a) multiple operations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor, or support (e.g., mounting, housing, lead frame, discrete heat sink, etc.), (b) multiple operations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already packaged semiconductor substrate (e.g., coating, etching, etc.).

However, other manufacturing classes have established historic lines with Class 438 that must be considered when determining proper placement. These lines with external classes revolve around such concepts as: whether there is significant semiconductor device structure, whether there is a unit operation or a so-called "multi-step" operation, etc. The search notes in References to Other Classes, below, are intended to clarify these established lines and to alert the searcher to other classes for related searches.

D. LINE NOTES TO OTHER MANUFACTURING OPERATIONS

See References to Other Classes, below for lines clarifying the relationship of other chemical classes to Class 438. For many of the chemical classes, inclusion of metal casting, working or deforming, or fusion bonding step is not acceptable if combined with an operation of the chemical class.

E. LOCATION OF SEMICONDUCTOR COMPOUND, COMPOSITION, OR STOCK

Class 438 does not provide for compound, composition, or stock material produced or utilized by a Class 438 process. A process of manufacture or use of a compound or composition is usually classified with the compound or composition. The process of manufacturing a semiconductor compound or composition and the formation of a semiconductor device or semiconductor junction takes combined operations to Class 438.

Also see References to Other Classes, below, identifying this section.

F. LINE TO HEATING CLASSES

This class (438), will take the process of (a) heating of semiconductor material to modify the microstructure or electrical properties thereof, (b) combined operations involving heating of semiconductor material to modify the semiconductor structure or electrical properties when not provided in another class, or (c) heating of semiconductor substrates that affects only the nonsemiconductor region of the substrate when combined with other operations acceptable to Class 438 or combined with the establishment of device structure (e.g., connects, insulating regions, electrodes, etc.).

See References to Other Classes, below, identified as heating classes.

G. LINE NOTES TO ELECTRICAL CLASSES

See References to Other Classes, below.

SECTION III - REFERENCES TO OTHER CLASSES

SEE OR SEARCH CLASS:

29,

Metal Working, especially subclasses 729+ for electrical device manufacturing apparatus, subclasses 829+ for the assembly of electrical components to an insulative base having a conductive path applied thereto, or formed thereon or therein (e.g., a printed circuit board). [See "Packaging (e.g., With Mounting, Encapsulating, etc.)" above]

(1) Note. When Class 438 coating (see "Unit Coating Operations, Combined Operations Involving Coating" above,) or etching operations (see "Unit Etching Operations And Combined Etching Operations") are not included, Class 29, subclasses 825+, following historical precedence, provides for processes of mounting, packaging, molding, or encapsulating of semiconductors having no significant semiconductor chip structure (e.g., merely recited as semiconductor chip, per se, etc.) when not elsewhere provided. If there is no significant chip structure, Class 29 takes as original (a) adhesive bonding combined with specified metal shaping steps or (b) adhesive bonding combined with mechanical joining, either broad or specific.

(2) Note. Multistep processes for packaging semiconductors having no significant semiconductor chip structure are proper for Class 156 when they claim: (a) adhesive bonding combined with shaping of nonmetals; (b) adhesive bonding combined with broad or nominally claimed metal shaping steps; or (c) adhesive bonding including steps for assembling the parts to be bonded are proper in Class 156.

53,

Package Making, for passage through the channels of trade in a safe, convenient, and attractive condition, usually wrapped in a cover or in a container. In this context of trade, Class 53 provides for methods of: (a) encompassing, encasing, or completely surrounding goods or materials with a cover made from sheet stock, (b) partially encasing or surrounding goods and materials by a partial cover made from sheet stock, (c) assembling or securing a separate closure to an aperture of a preformed receptacle to complete encasement of contents, (d) depositing articles and arranging fluent materials in preformed receptacles, (e) partial or complete shaping of a cover about an article, and other related package making processes. (See "Packaging (E.g., With Mounting, Encapsulating, Etc.)" above)

(1) Note: If it cannot be perceived (a) whether the process is package making or (b) whether the process is manufacturing of a semiconductor device within or attached to a container, case, lead frame, heat sink, or enclosure as an integral part of the manufactured product; placement goes to Class 438 and Class 53 may be cross-referenced.

65,

(1) Note. Class 438 takes packaging or the packaging-related operation of semiconductor devices when glass melting, glass shaping, glass forming, or glass heat treating is combined with any coating, adhesive bonding, metal casting, metal working, or deforming, metal fusion bonding or other chemical manufacturing operation.

65,

Glass Manufacturing, for processes of melting, shaping or forming, joining, or heat treating of glass. Glass is defined in the Class 65 definitions (Glossary) as an inorganic material generally including a glass former and having specific characteristics provided in the definition. It is noted that both silica and elemental silicon are also included for Class 65. Thus, melting, shaping, or fusion bonding of silicon dioxide, per se, or silicon, per se, is also considered proper for Class 65. Class 65 also takes combined operations whether preparatory or subsequent to the melting, shaping or forming, joining or heat treating of glass. Included in Class 65 is joining, per se, of glass to metal, spinning, per se, of glass fibers or joining through glass melting, per se, of glass fibers to substrates such as semiconductor substrates. (see "Line Notes To Other Manufacturing Operations," above)

(1) Note. Class 438, as the exception, takes the combination of Class 438 unit coating operation or Class 438 unit etching operation with glass melting, shaping or forming, joining, or heat treating. Moreover, Class 438 also takes the heat treating, per se, of Class 438 semiconductor material if for purposes of modifying the electrical properties thereof. Class 438 takes the mounting or packaging operation of semiconductor devices when glass melting, glass shaping, glass forming, or glass heat treating is combined with any coating, adhesive bonding, metal casting, metal working, or deforming, metal fusion bonding or other chemical manufacturing operation.

106,

Compositions: Coating or Plastic, subclasses 1.05+ for metal-deposition or substrate-sensitizing compositions; subclasses 286.1+ for inorganic materials only containing at least one metal atom; subclass 286.8 for inorganic materials only; subclasses 287.1+ for silicon containing other than solely as silicon dioxide as a part of an aluminum-containing compound, and subclasses 400+ for materials or ingredients. (see "Location Of Semiconductor Compound, Composition, Or Stock" above.)

117,

Single-Crystal, Oriented-Crystal, and Epitaxy Growth Processes; Non-Coating Apparatus Therefore, for processes of single crystal growth of semiconductor material upon a seed or substrate and perfecting operations combined therewith. See Class 117 definitions for examples of perfecting operations generally acceptable to Class 117. See particularly Class 117, Class Definition, (2) Note, Keywords and (3) Note, Indicative Terminology, for terms indicative of single crystal formation. Inclusion of a nonperfecting single crystal forming operation on a semiconductor substrate or producing a semiconductor product meeting the hereinabove requirements of a semiconductor material or the definition of a semiconductor substrate takes the original to Class 438, even if there is present a single crystal forming step. (Coating operation not meeting Class 438 definition)

(1) Note. When combined with single crystal formation, the following operations are acceptable in Class 438: (a) simultaneous formation of nonsingle crystalline regions intended to impart structure that will serve as a functional part of the semiconductive substrate or completed device, (b) prior or subsequent removal of a nonseed portion of the substrate in order to impart electrical device structure to the same (e.g., formation or a recess, trench, trough, ridge, mesa, stripe, etc.), or (c) prior or subsequent step acting to alter the composition of the semiconductor substrate so as to impart electrical device structure to the same.

134,

Cleaning and Liquid Contact With Solids, especially subclass 1.2 and 1.3 for processes for cleaning a semiconductor substrate including the application of electrical or wave energy to the substrate. (Etching operation not meeting the Class 438 definition)

(1) Note. If the undesirable material to be removed from the semiconductor substrate resides other than on the surface thereof, the process is to be considered gettering of the substrate and thus is proper for Class 438.

148,

Metal Treatment, for unit coating operations on metal, particularly subclasses 206+ wherein there is carburization or nitriding of a metal surface by chemical reaction or diffusion of an externally supplied source of carbon or nitrogen that reacts with the metal surface wherein the metal substrate remains as part of the coating and subclasses 240⁺wherein there is reactive coating of a metal substrate with an external reactant (e.g., oxygen, etc.) wherein the metal substrate remains as part of the coating. Class 148 also takes heat treatment of metallic compositions if during the heat treatment there is either a change in the internal physical structure (i.e., microstructure) or chemical properties. (Coating operation not meeting Class 438 definition)

(1) Note. Since in certain instances metallic compositions could be semiconductor material meeting the Class 438 criteria, placement will go to Class 438 over Class 148 if the material is identified or perceived as semiconductor material. If perceived, a mandatory cross is made in Class 148.

(2) Note. Reactive coating, per se, of a metal (i.e., not intended to be semiconductive) area on a semiconductive substrate (i.e., meeting the Class definition of semiconductor substrate in the Glossary) is original in Class 438. A mandatory cross is made in Class 148 if the only step is reactive coating of a metal portion of a semiconductive containing substrate.

(3) Note. Combination of Class 148 heat treatment of a metal substrate to modify or maintain the chemical property or microstructure of the metal with (a) additional manufacturing of semiconductor device structure or (b) with a Class 438 coating or etching operation takes the original to Class 438.

148,

Metal Treatment, subclasses 33.1+ for semiconductor stock which must be essentially homogeneous and have at least two contiguous layers differing in the number of unbound electrons and/or differing in energy gap levels, which exhibit a junction between the layers. (see "Location of Semiconductor Compound, Composition, or Stock" above.)

148,

Metal Treatment, for processes of heat treating metals. Class 148 takes heat treatment of metallic compositions if during the heat treatment there is either a change in the internal physical structure (i.e., microstructure) or chemical properties. Since in certain instances metallic compositions could be semiconductor material meeting the Class 438 criteria, placement will go to Class 438 over Class 148 if the material is identified or perceived as semiconductor material. If perceived, a mandatory cross is made in Class 148. (heating class)

156,

Adhesive Bonding and Miscellaneous Chemical Manufacture, subclasses 60+ for a process of adhesively bonding. Multistep processes for packaging semiconductors having no significant semiconductor chip structure are proper for Class 156 when they claim (a) adhesive bonding combined with shaping of nonmetals, (b) adhesive bonding combined with broad or nominally claimed metal-shaping steps, or (c) adhesive bonding including steps for assembling the parts to be bonded are proper in Class 156. An adhesive bonding unit operation for packaging or mounting operations on semiconductor devices goes as original to Class 156. Adhesive bonding combined with Class 438 coating of a semiconductor substrate or Class 438 etching of a semiconductor substrate places the original in Class 438. (See "Packaging (e.g., With Mounting, Encapsulating, etc.)" above)

174,

Electricity: Conductors and Insulators, subclasses 15.1 through 16.3for fluid cooling of electrical conductors or insulator, subclasses 50-64 for housings with electric devices or mounting means, and subclasses 250-268 for printed circuit devices.

204,

Chemistry: Electrical and Wave Energy, particularly subclasses 192.1 through 192.37for sputter coating operations involving semiconductor material or substrates including a semiconductor region, even if the intent is to use the semiconductor material for (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy - Class 204 will take combinations of sputter coating with other chemical treating operations that involve (a) preparatory treatment of the substrate (e.g., etching, cleaning, etc.) or (b) subsequent perfecting treatment of the applied coating with the following exception noted (coating operation not meeting Class 438 definition); and subclasses 192.32-192.37, for sputter etching operations on semiconductor material and semiconductor containing substrates, even if the semiconductor is intended for electrical purposes - simultaneous sputter etching and chemical etching (e.g., as when utilizing a mixture of argon and halide gas, etc.) go as original in Class 204 (etching operation not meeting the Class 438 definition).

(1) Note. Creation of semiconductor structure (e.g., semiconductor active region, semiconductor junction, etc.) by subsequent treatment steps, even if limited to the Class 204 applied coating, will go to Class 438. Any subsequent operation that affects the substrate is not provided in Class 204 and is proper in Class 438. However, heat treatment of the Class 204 coating that causes interdiffusion limited to the interfacial region to perfect the bonding of the coating to the substrate is proper for Class 204.

(2) Note. Creation of semiconductor structure (e.g., semiconductor active region, semiconductor junction, etc.) by steps subsequent to sputter etching will go to Class 438.

205,

Electrolysis: Processes, Compositions Used Therein, and Methods of Preparing the Compositions, particularly subclass 123 , 124, and 157 for electrolytic coating operations on semiconductor or semiconductor devices (coating operation not meeting Class 438 definition), subclasses 334-639 for electrolytic synthesis of material, such as silicon, by passing an electrical current through a fused material, and subclass 656 for electrolytic erosion of a workpiece of non-uniform internal electrical characteristics (etching operation not meeting the Class 438 definition). Class 205 will take combinations of electrolytic coating with other chemical treating operations that involve (a) preparatory treatment of the substrate (e.g., etching, cleaning, etc.) or (b) subsequent perfecting treatment of the applied coating with the following exception noted (coating operation not meeting Class 438 definition).

216,

Etching a Substrate: Processes, for chemical etching processes and perfecting operations therefor, including lithos:graphic steps, of semiconductor material that is to be utilized for nonelectrical properties. (Etching operation not meeting the Class 438 definition)

(1) Note. This class provides for a species of Class 216 operations involving etching a semiconductive substrate or etching a substrate containing a semiconductive region; wherein the intent is to use the electrical properties of the semiconductor in a solid-state device for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.

(2) Note. Generic claims with a sole claimed specie of etching for Class 216 goes as original to Class 216. Generic claims with a sole disclosed specie of etching for Class 438 goes as original in Class 438. Generic claims with plural claimed etching specie wherein at least one of the claimed species does not belong in Class 438 goes as original in Class 216. Generic claims with plural disclosed etching specie one of which does not belong in Class 438 goes to Class 216 as original. Generic claims with no material specie claimed or disclosed goes as original in Class 216. When there is no generic claim and plural separately claimed etching specie, wherein at least one claim of which is Class 216 and one claim of which is Class 438, placement goes as original to Class 438 with a mandatory cross-reference to Class 216.

219,

Electric Heating, subclasses 78.01+ for a process and apparatus for bonding by electrical current and pressure, and appropriate subclasses for electric heating of material, per se. However, inclusion of the criteria for Class 438 as set forth hereinabove takes the original to Class 438 even when electric heating is involved. (heating class)

228,

Metal Fusion Bonding, appropriate subclasses for a process of fusion bonding and additional operations which are considered to be ancillary to the bonding (preheating, positioning, pretinning, etc.) of a semiconductive substrate; especially note subclass 123.1 and 179.1+. [See "Packaging (e.g., With Mounting, Encapsulating, etc.)" above]

250,

Radiant energy, for methods not elsewhere provided of (a) using, generating, controlling, or detecting radiant energy, (b) combinations including such methods, and (c) subcombinations thereof. Particularly, see subclasses 492.2+ for processes of irradiation of semiconductor devices with no indication as to what occurs to the substrate. Class 250, subclasses 492.2+^, generally relates to processes of exposing substrates to ion bombardment utilizing apparatus of Class 250 when limited to operating the apparatus in apparatus terms. Class 250 is also the generic home for processes of exposing substrates to ion bombardment. However, Class 438 provides for ion implantation of semiconductive substrate or substrate containing a semiconductive region and also ion implantation throughout the material mass to produce semiconductive material or to modify the semiconductive material. (Coating operation not meeting Class 438 definition)

250,

Radiant Energy, for methods not elsewhere provided, of (a) using, generating, controlling, or detecting radiant energy, (b) combinations including such methods, and (c) subcombinations thereof. Particularly, see subclasses 492.2+ for processes of irradiation of semiconductor devices with no indication as to what occurs to the substrate. Class 250 subclasses 492.2+^, generally relates to processes of exposing substrates to ion bombardment utilizing apparatus of Class 250 when limited to operating the apparatus in apparatus terms. Class 250 is also the generic home for processes of exposing substrates to ion bombardment. However, Class 438 takes chemically reactive ion etching of semiconductive substrate or substrate containing semiconductive region. (Etching operation not meeting the Class 438 definition)

250,

Radiant Energy, for heating invisible radiant energy; subject matter of Class 438, per se, when no function other than heating is attributed to the process and for methods not elsewhere provided, of (a) using, generating, controlling, or detecting radiant energy, (b) combinations including such methods, and (c) subcombinations thereof. Particularly, see subclasses 492.2+ for processes of ion bombardment or irradiation of semiconductor devices, with no indication as to what occurs to the substrate. (heating class)

252,

Compositions, for (a) subclasses 62.3+ for semiconductor compositions which have been uniformly doped or otherwise specialized for use as one layer which when combined with another such layer would provide an interface exhibiting barrier layer properties (e.g., as exists in Class 148, subclasses 33 through 33.6, stock wherein there is a semiconductor junction, etc.) and (b) subclasses 500+ for electrical conductive compositions. Also see the cross-reference art collection in Class 252, subclasses 950+^, for doping agent source materials. (see "Location Of Semiconductor Compound, Composition, Or Stock" above.)

257,

Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), for active solid-state electronic device structure, per se. Subject matter may include one or more such devices combined with contacts or leads, or structures configured to be tested on a semiconductor chip, or merely semiconductor material without contacts or leads where the sole disclosed use is an active solid-state device. This subject matter does not include active solid-state devices combined with significant circuits. (electrical class)

264,

Plastic and Nonmetallic Article Shaping or Treating: Processes, for a process (and steps perfecting same) of forming a composite by shaping a plastic or nonmetallic wherein a semiconducting containing preform is within a mold during the shaping operation (e.g., encapsulating, etc.). (See "Packaging (e.g., With Mounting, Encapsulating, etc.)" above)

361,

Electricity: Electrical Systems and Devices, subclasses 679.01 through 679.61for housing and mounting assemblies for electronic devices and components, and subclasses 736+ and 752+ for modules for printed circuits or housing or chassis for printed circuit boards. (electrical class).

376,

Induced Nuclear Reactions: Processes, Systems, and Elements, particularly subclass 183 for a process of neutron bombardment, per se, of semiconductive material containing an element which is converted to a desired dopant by nuclear transmutation. Any combination of operations that goes beyond formation of the transmutated doped semiconductor material, per se, goes as original to Class 438 if it meets the criteria of the intent to use the electrical properties of the semiconductor in a solid-state device as set forth by the Class 438 definition. (Coating operation not meeting Class 438 definition)

376,

Induced Nuclear Reactions: Processes, Systems, and Elements, subclasses 320+ for the direct conversion of the energy produced in a nuclear reaction into an electrical output by a one-step process or apparatus for accomplishing such a one-step process. (electrical class)

378,

X-ray or Gamma Ray Systems or Devices, especially subclasses 34+ for X-ray or gamma-ray lithography. (electrical class)

382,

Image Analysis, especially subclass 145 for a process limited to image analysis per se in manufacturing of an integrated circuit. However, inclusion of subject matter for Class 438 remains with Class 438 even if there is a step of image analysis.

385,

Optical Waveguides, particularly, subclass 14 for a laser in integrated optical circuit, subclasses 129+ for a planar optical waveguide, and subclasses 141+ for a waveguide having a particular optical characteristic modifying chemical composition. The (13) Note of Class 385 indicates that miscellaneous manufacturing of optical wave guide devices not elsewhere provided are in Class 385. Thus, if the manufactured article is a semiconductor device, a Class 438 process controls over the Class 385 process even if an optical fiber is part of the device. (electrical class)

420,

Alloys or Metallic Composition, for alloys or metallic compositions that may also exhibit semiconductor properties (e.g., gallium arsenide, etc.). (see "Location Of Semiconductor Compound, Composition, Or Stock" above.)

423,

Chemistry of Inorganic Compounds, appropriate subclasses for inorganic compounds or elements used in the manufacture of semiconductor devices. (see "Location of Semiconductor Compound, Composition, or Stock" above.)

427,

Coating Processes, for coating operations provided for in that class, particularly subclasses 457+ for a process of treating a coating with radiant energy; subclasses 487+ for polymerization of applied coating utilizing direct application of electrical, magnetic, wave, or particulate energy; subclasses 523+ for ion plating or ion implanting; subclasses 532+ for pretreatment of a substrate or posttreatment of a coated substrate utilizing electrical, magnetic, wave, or particulate energy; subclasses 569+ for deposition coating processes utilizing plasma; subclasses 580+ for deposition coating processes utilizing electrical discharge; subclass 581 for coating processes utilizing chemical liquid deposition; subclass 582 for coating processes utilizing photo-initiated chemical vapor deposition; subclasses 585+ for coating processes utilizing chemical vapor deposition; subclass 591 for deposition coating utilizing induction or dielectric heating; subclasses 592+ for deposition coating utilizing resistance heating; subclasses 595+ for deposition coating utilizing electromagnetic or particulate radiation; subclasses 598+ for deposition coating utilizing magnetic field or force; subclass 600 for deposition coating utilizing sonic or ultrasonic energy. (Coating operation not meeting Class 438 definition)

(1) Note. Class 438 provides for a specie of Class 427 operations involving (a) coating a substrate with a semiconductive material or (b) coating a semiconductive substrate or substrate containing a semiconductive region; and wherein the intent is to use the electrical properties of the semiconductor in a solid state device for at least one of the following purposes: (i) conducting or modifying an electrical current, (ii) storing electrical energy for subsequent discharge within a microelectronic integrated circuit, or (iii) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy.

(2) Note. Generic claims with a sole claimed specie of coating for Class 438 goes as original to Class 438. Generic claims with a sole disclosed specie of coating for Class 438 goes as original in Class 438. Generic claims with plural claimed coating species wherein at least one of the claimed species does not belong in Class 438 goes as original in Class 427. Generic claims with plural disclosed coating species one of which does not belong in Class 438 goes to Class 427 as original. Generic claims with no material species claimed or disclosed goes as original in Class 427. When there is no generic claim and plural separately claimed coating specie, wherein at least one claim of which is Class 427 and one claim of which is Class 438, placement goes as original to Class 438 with a mandatory cross-reference to 427.

428,

Stock Material or Miscellaneous Articles, appropriate subclasses for semiconductor stock material defined in terms of composition and structure, especially subclass 620 . (see "Location of Semiconductor Compound, Composition, or Stock" above.)

429,

Chemistry: Electrical Current Producing Apparatus, Product, and Process, especially subclass 7 for a combination including a nonbattery electrical component electrically connected within a cell casing other than testing or indicating components. (electrical class)

430,

Radiation Imagery Chemistry: Process, Composition, or Product Thereof, particularly for initial lithos:graphic processes in semiconductor manufacture limited to (a) exposure imaging and developing and including preparatory operations to the exposure (e.g., as coating to form the resist, etc.) or (b) developing, per se, of subject matter of Class 430 substrates. When Class 430 exposure, imaging or developing are combined with etching or coating of a semiconductor substrate for purposes other than masking and commensurate with the Class 438 definition for manufacture of a semiconductor device as set forth hereinabove, the combination goes as original to Class 438 with the following exception noted. (Coating operation not meeting Class 438 definition)

(1) Note. Since Class 430 provides for processes of (a) coating, per se, of substrates, with a composition to produce a product to be used for electric or magnetic imagery and (b) processes of coating, per se, of substrate with a photosensitive composition for use in radiation imagery, coating or etching of semiconductor material limited to forming a product intended to be used for electric, magnetic, or radiation imagery is original in Class 430.

(2) Note. Although technically classifiable as an original in Class 438 according to the above paragraph, any multistep process involving significant Class 430 operations as a subcombination of the overall process should be cross-referenced to Class 430.

430,

Radiation Imagery Chemistry: Process, Composition, or Product Thereof, particularly for initial lithos:graphic processes in semiconductor manufacture limited to (a) exposure imaging and developing and including preparatory operations to the exposure (e.g., as coating to form the resist, etc.) or (b) developing, per se, of subject matter of Class 430 substrates. When Class 430 exposure imaging or developing are combined with etching or coating of a semiconductor substrate commensurate with the Class 438 definition for manufacture of a semiconductor device as set forth hereinabove, the combination goes as original to Class 438 with the following exception noted. (Etching operation not meeting the Class 438 definition)

(1) Note. Since Class 430 provides for processes of (a) coating, per se, of substrates, with a composition to produce a product to be used for electric or magnetic imagery and (b) processes of coating per se of substrate with a photosensitive composition for use in radiation imagery, coating or etching of semiconductor material limited to forming a product intended to be used for electric, magnetic, or radiation imagery is original in Class 430.

432,

Heating, for generic heating processes. However, inclusion of the criteria for Class 438 as set forth hereinabove takes the original to Class 438 even when generic heating is involved. (heating class)

439,

Electrical Connectors, appropriate subclasses for features related or analogous to electrical contact or housing features of active solid-state devices (e.g., subclasses 271+ for sealing elements or subclasses 449+ for stress relief means for conductor to terminal joint. (electrical class)

501,

Compositions: Ceramic, appropriate subclasses for ceramic compositions used in semiconductor devices. (see "Location of Semiconductor Compound, Composition, or Stock" above.)

505,

Superconductor Technology: Apparatus, Material, Process, particularly subclass 330 for processes of manufacturing from high temperature (i.e., above 30 degrees Kelvin) superconductive material (a) superconductor devices or (b) semiconductor devices having superconductive components or connect lines. (see "Line Notes To Other Manufacturing Operations," above)

SECTION IV - GLOSSARY

Listed below are: (1) a compilation of acronyms, abbreviations, and technological terms pertaining to solid-state electrical devices, manufacturing processes, and related apparatus and compositions useful therefor and (2) the meaning to be given to the various "art" terms appearing in this class. These latter terms, some of which have been included in the glossary below, are the same as that generally accepted or in common usage. However, certain terms employed in this class and also included below have been assigned definitions which may be more restrictive or different from those in common usage since these terms are being utilized for distinguishing this class over other classes of related art.

a-Si

Amorphous silicon

ACT

Acoustic charge transport

ADC

Analog-to-digital converter

AES

Auger electron spectroscopy

ALE

Atomic layer epitaxy

ALEP

Angle-lapping edge profilometry

AMD

Active matrix display

AMG

Alternative-metal, virtual-ground (metallization)

APCVD

Atmospheric-pressure CVD

APD

Avalanche photodiode

ARC

antireflective coating

ASG

Arsenosilicate glass

BBCO

Barium bismuth copper oxide (a HTSC)

BBD

Bucket brigade device

BBL

Buried bit-line

BED

Band edge discontinuity

Buried heterostructure

BHF

Buffered hydrofluoric acid

BIC

Breakdown of insulator for conduction

BICFET

Bipolar inversion channel FET

BiCMOS

Integrated bipolar and CMOS

BiMOS

Integrated bipolar and MOSFET

BJT

Bipolar junction transistor

BKBO

Barium potassium bismuth oxide (a HTSC)

BLM

Ball limiting metallization

BMD

Bulk micro defect

BOE

Buffered oxide etch

BOX

Buried oxide

BOXES

Buried oxide with etch stop

BPSG

Borophosphosilica glass

BPTEOS

borophosphoTEOS

BSD

Back side damage

BSE

buried storage electrode

BSG

Borosilica glass

BSQ

Bias sputter quartz

BST

Barium strontium titanate

CAIBE

Chemically assisted ion beam etching

CBIC

Complementary bipolar IC

CBKR

Cross bridge Kelvin resistor (test structure)

CCB

Controlled collapse bonding

CCC

Corrugated capacitor cell

CCD

Charge coupled device

CDE

Chemical dry etching

CDI

Collector diffusion isolation

CEL

Contrast enhancement layer

CER

Contact end resistor (test structure)

CERDIP

ceramic DIP

chanstop

channel stop isolation structure

CHEMFET

Chemically sensitive FET

CHL

Current hugging logic

CID

Charge injection device

CLSEG

Confined lateral SEG

CML

Current mode logic (i.e., ECL)

CMOS

Complementary (NMOS and PMOS) FETs

CMP

chemical-mechanical polishing/planarization

COB

(a) chip-on-board or (b) capacitor over bit-line

COD

Catastrophic optical damage

COG

Chip-on-glass

COMFET

Conductivity modulation FET (i.e., IGBT)

CSBH

Channeled substrate buried heterostructure

CSL

Coherent superlattice

CTD

Charge transfer device

CTSL

Coherent tilted superlattice

CVD

Chemical vapor deposition

Czoshralski (melt pulling)

DADBS

diacetoxyditertiarybutoxysilane

DADIS

diacetoxydiisopropoxysilane

DBR

distributed Bragg reflector

DCG

dichromated gelatin

DCFL

direct-coupled FET logic

DCS

dichlorosilane

DDE

double diffused epitaxy

DDI

deep dielectric isolation

DEIS

dual electron injection structure

DEZ

diethylzinc

DFB

distributed feedback (laser)

double-hetero

DHBT

double-hetero bipolar transistor

DHF

dilute hydrofluoric acid

dielectric isolation

DIBL

drain induced barrier lowering

DIET

dielectrically encapsulated trench capacitor

DIP

dual-in-line package

DLP

double layer polysilicon

DLTS

deep level transient spectroscopy

DMAH

dimethylaluminumhydride

DMD

(a) depletion mode device (also D-mode or D-type) or (b) deformable mirror device

DMOS

double diffused MOS

DMS

dilute magnetic semiconductor

DOES

doublehetero optoelectronic switch

DRAM

dynamic random-access memory

DSP

double stacked capacitor

DTL

diode-transistor logic

DUF

diffusion under film

DUT

device under test

DUV

deep ultraviolet

denuded zone

-E-

EAROM

electrically alterable read-only memory

(a) extrinsic base or (b) electron beam

EBES

electron beam exposure system

EBIC

electron beam induced current

EBL

electron beam lithography

ECL

emitter coupled logic

ECR

electron cyclotron resonance

EDP

ethylene-diamine-pyrocatechol etchant

EDTA

ethylenediaminotetraacetic acid

EELS

electron energy loss spectroscopy

EEPROM

electrically erasable programmable read-only memory

EFG

edge-defined film-fed growth (also EDFFG or EDFG)

extrinsic gettering

EGSi

electronic-grade silicon

electroluminescent

ELO

epitaxial lateral overgrowth

EMD

enhancement mode device (also E-mode or E-type)

EMI

electromagnetic interference

EMP

electron microprobe

EPB

epoxidated polybutadiene (an EB resist)

EPD

etch pit density

EPI

epitaxial (single crystalline) layer

EPP

ethylene-piperidine-pyrocatechol etchant

EPR

electron paramagnetic resonance

EPROM

erasable programmable read-only memory

EPS

effective punchthrough stopper

EPW

etchant mix of ethylenediamine, pyrocatechol, and water

ESCA

electron spectroscopy for chemical analysis

ESD

electrostatic discharge

ESR

(a) equivalent series resistance or (b) electron spin resonance

FAMOS

floating-gate avalanche-injection MOS

FASIC

folded bit-line adaptive sidewall isol. capacitor cell

FCT

field controlled thyristor

FEC

floating electrode capacitor

FED

field emission device

FET

field effect transistor

FIB

focused ion beam

FIPOS

full isolation by porous oxidized silicon

FLOTOX

floating gate tunnel oxide

FOX

field oxide

FPD

field programmable device

FPGA

field programmable gate array

FTIR

Fourier transform infrared spectroscopy

FUROX

fully recessed oxide isolation

GDMS

glow discharge mass spectroscopy

GILD

gas immersion laser doping

GRIN-SCH

graded index separate confinement heterostructure

GTO

gate turn-off

HBT

heterojunction bipolar transistor

HDC

high dielectric constant

HDI

high density interconnects

HDMI

high density multilayer interconnects

HEMT

high electron mobility transistor (Hetero MESFET)

HET

hot electron transistor (bipolar)

Hi-C

high capacitance

HIC

hybrid integrated circuit

HIMOS

(see COMFET)

HIPOX

high pressure oxidation

HMDS

hexamethyldisilizane

HNA

hetchant mix of hydrofluoric, nitric, and acetic acids

HPSC

half-V_ccsheath plate capacitor

HTO

high temperature oxide

HTSC

high temperature superconductor

(a) intrinsic base or (b) ion beam

IBD

ion beam deposition

integrated circuit

ICP

inductively coupled plasma

intrinsic gettering

IGBT

insulated gate bipolar transistor (e.g., COMFET, HIMOS)

IGFET

insulated gate field effect transistor

IID

impurity induced disordering

I²L

integrated injection logic

IJP

ink jet printhead

ILB

inner lead bonding

ILD

interlayer dielectric

IMMA

ion microprobe mass analysis

IMPATT

impact ionization avalanche transist time (diode)

INS

intrinsic nondoped semiconductor

infrared

ISFET

ion sensitive FET (i.e., CHEMFET)

ITO

indium tin oxide (a TCO)

IVEC

isolation vertical capacitor cell

JFET

junction field effect transistor (junction gate)

JOFET

Josephson junction field effect transistor

JTE

junction termination extension

KMER

Kodak metal etch resist

KPR

Kodak photo resist

KTFR

Kodak thin film resist

LAGB

low-angle grain boundary

LATID

large angle tilt implant drain

(a) Langmuir-Blodgett or (b) laser beam

LCCD

leadless ceramic chip carrier

LCD

liquid crystal display

LDCC

leaded ceramic chip carrier

LDD

lightly doped drain

LEC

liquid encapsulated Czoshralski

LED

light emitting diode

LEED

low-energy electron diffraction

LEK

liquid encapsulated Kyropoulus

LOCOS

local oxidation of silicon

LOPED

lift-off using edge detection

LPCVD

low-pressure chemical vapor deposition

LPE

liquid phase epitaxy

LRP

limited reaction processing

LSI

large scale integration

LSSL

lateral surface superlattice

LST

logic service terminal

LTCC

low temperature co-fired ceramic

LTG

low temperature growth

LTO

low temperature oxidation

MBE

molecular beam epitaxy

MCz

magnetic Czoshralski

MCM

multichip module

MCT

(a) MOS controlled thyristor or (b) HgCdTe

MEM

micro-electromechanical

MESFET

metal semiconductor FET (Schottky gate)

MF³R

modified fully-framed fully-recessed isolation

MGSi

metallurgical-grade silicon

MIM

metal-insulator-metal

MISFET

metal insulator semiconductor IGFET

MLEC

magnetic LEC

MLC

multilayer ceramic

MLO

multilayer oxide

MLR

multilayer resist

MMA

methyl methacrylate

MMIC

monolithic microwave integrated circuit

MNOS

metal nitride/oxide IGFET

MOCVD

metal organic chemical vapor deposition

MODFET

modulation doped MESFET (i.e., HEMT)

MOMOM

metal-oxide-metal (tunnelling device)

MOSFET

metal oxide semiconductor IGFET

MQW

multiquantum well

MTF

mean time to failure

MTL

merged transistor logic (i.e., I²L)

NDC

negative differential conductivity

NEA

negative electron affinity (e^-emitter)

NMA

N-methyl-acetamide

NMOS

n-channel MOSFET

NMP

n-methyl-pyrrolidone

novolak

Thermoplastic phenol-formaldehyde used as photoresist

NPN

(bipolar transistor)

NRD

nitridation retarded diffusion

NSAG

nonself-aligned gate

NTD

neutron transmutation doping

NVRAM

nonvolatile RAM

OBG

optical band gap

ODE

orientation dependent etching

OED

oxidation enhanced diffusion

OEIC

optoelectronic integrated circuit

orientation flat

OISF

oxidation induced stacking fault

OMCVD

organometallic CVD

OMCT

octamethylcyclotetrasiloxane

OMVPE

organometallic VPE

ORD

oxidation retarded diffusion

ORL

optical return loss

OSA

optical subassembly

OSF

(see OISF)

OTCR

over-the-cell routing

OTP

one-time programmable

OXSEF

oxygen-doped silicon epitaxial film

PAC

photoactive compound

PAP

peel apart

PBG

photonic band gap

PBL

polybuffered LOCOS

PBM

planarization blocking mask

PBN

pyrolytic boron nitride

PBT

permeable base transistor

PCB

printed circuit board

PCE

photoconductive element

PEB

postexposure baking

PECVD

plasma enhanced chemical vapor deposition

PEP

photo-engraving process

PFT

peeled film technology

PGA

(a) pin-grid array or (b) programmable gate array

PGMA

poly(glycidyl methacrylate) (an EB resist)

PHS

plated heat sink

PIC

photonic integrated circuit

PID

programmable interconnect device (fuse/antifuse)

PIN

P-type layer, intrinsic layer, N-type layer

PIQ

thermosetting polyimide resin

PLA

programmable logic array

PLCC

plastic leaded chip carrier

PLDD

profiled LDD

PLM

pad limiting metallurgy

PLZT

lead lanthanate zirconate titanate

PMMA

polymethylmethacrylate

PMOS

p-channel MOSFET

PNP

(bipolar transistor)

polycide

polycrystalline silicide

polySi

polycrystalline silicon

PPL

poly pad LOCOS

photoresist

PROM

programmable read only memory

PROPS

planarization with resist/oxide and polysilicon

PSD

photosensitive diode or dielectric

PSG

phosphosilica glass

PTC

positive temperature coefficient

PTH

plated through-hole

PUT

programmable unijunction transistor

PVD

physical vapor deposition

PWB

printed wiring board

PZT

lead zirconate titanate

quantum efficiency

QFP

quad flat package

QUIP

quad-in-line package

quantum well

QWIP

quantum well infrared photodetector

RAM

random access memory

RBS

Rutherford backscattering

RBT

resonant tunneling bipolar transistor

RCT

reverse conducting thyristor

RED

radiation enhanced diffusion

resurf

reduced surface field

RETT

resonant electron transfer triode

radiofrequency

RHEED

reflected high energy electron diffraction

RHET

resonant tunneling hot electron transistor (bipolar)

RIBE

reactive ion beam etching

RIE

reactive ion etching

RISC

reduced instruction set computing

RMS

refined metallurgical silicon

ROI

recessed oxide isolation

ROM

read only memory

ROX

recessed oxide

RTA

rapid thermal anneal

RTP

rapid thermal processing

salicide

self-aligned silicide

SAG

self-aligned gate

SAW

surface acoustic wave (pressure sensitive device)

SBD

Schottky barrier diode

SBH

Schottky barrier height

SBS

silicon bilateral switch

SCCM

standard cubic centimeter per minute

SCM

single chip module

SCR

silicon controlled rectifier

SDFL

Schottky diode FET logic

SDHT

selectively doped heterostructure transistor (e.g., HEMT)

S-DIP

shrink DIP

SEED

self-enhanced electro-optical devices

SEG

selective epitaxial growth

SEL

(a)surface emitting laser or (b)state excitation by light

SELFOX

selective epitaxial layer field oxidation

SEM

scanning electron microscopy

SEOT

self-aligned epitaxy over trench

SEPOX

selective polysilicon oxidation

SER

soft error rate

SFFT

superconducting flux flow transistor

SGT

surrounding gate transistor

silicon

semi-insulating

SICOS

sidewall base contact structure

SILO

sealed interface local oxidation

SIMOX

separation by implanted oxygen

SIMS

secondary ion mass spectrometry

SIP

single-in-line package

SIPOS

semi-insulating polycrystalline oxygen-doped silicon

SIT

(a)static induct. thyristor or (b)static induct. trans.

SLM

spatial light modulator

SLS

strained layer superlattice

SLT

solid logic technology

SMT

surface mount technology

SOG

spin-on glass

SOI

silicon on insulator

SOIC

small outline IC package

SOJ

small outline J-lead package

SOS

silicon on sapphire

SPE

solid phase epitaxy

SPOT

self-aligned planar oxidation technology

SPT

substrate plate trench capacitor

SQUID

superconductive quantum interference device

SRAM

static random access memory

SRO

stress relief oxide

SSDP

simultaneous single/polycrystalline deposition

SSI

small scale integration

SST

(a)super self-alignment tech. or (b)sealed sidewall tech.

STT

stacked transistor capacitor cell

SUBHET

superconducting base hot electron transistor

SUBSIT

superconducting base semiconductor isolated transistor

SWAMI

sidewall masked isolation

TAB

tape automated bonding

TAT

turn around time

TBES

tritertiarybutoxyethoxysilane

TBCO

thallium bismuth copper oxide (a HTSC)

TCE

trichloroethylene

TCM

thermal conduction module

TCO

transparent conductive oxide

TDDB

time dependent dielectric breakdown

TEC

thermoelectric cooler

TED

transient enhanced diffusion

TEG

(a) triethylgallium or (b) test element group

TEM

transmission electron spectroscopy

TEOS

tetraethylorthosilane

TFR

thin film resistor

TFT

thin film transistor

TGZM

temperature gradient zone melting

through-hole

TIBA

triisobutylaluminum

TLTR

transmission line tap resistor (test structure)

TMA

(a) trimethylaluminum or (b) trimethylantimony

TMAH

tetramethyl ammoniumhydroxide

TMAT

tetramethylamidotitanium

TMB

tetramethylborate

TMCTS

tetramethylcyclotetrasiloxane

TMG

trimethylgallium

TMOS

tetramethyloxysilane

TMP

trimethylphosphine

TMS

tetramethylsilane

TMT

tetramethyltin

TOFER

topos:graphic feature enhancement by RIE

TPF

thermoplastic film

TRAPPAT

trapped plasma avalanche tunnel transit (diode)

TSD

temperature sensing diode

TSOP

thin small outline package

TTL

transistor-transistor logic

UHV

ultrahigh vacuum

ultraviolet

VCNR

voltage controlled negative resistance

VGF

vertical gradient freeze (also VFG)

VHSIC

very high speed integrated circuit

VLE

vapor levitation epitaxy

VLSI

very large scale integration

VMOS

vertical MOS

VPE

vapor phase epitaxy

VSIS

V-channel substrate inner stripe

WSI

wafer scale integration

XRD

x-ray diffraction

YBCO

yttria barium copper oxide (a HTSC)

YSZ

yttria stabilized zirconia

ZDO

zero drain overlap

ZIP

zigzag-in-line package

ZMR

zone melt recrystallization

microcrystalline

high resistivity intrinsic semiconductor

ACCEPTOR IMPURITY

An atom or ion different from or foreign to, but present in, a semiconductor material and which has insufficient valence electrons to complete the normal bonding arrangement in the semiconductor crystal structure. An acceptor impurity (also referred to as p-type) accepts an electron from an adjacent atom to create a positive charge carrier (i.e., a hole). A donor impurity (also referred to as n-type) provides an electron to the conduction band of the semiconductor.

ACTIVE SOLID-STATE DEVICE

An electronic device or component that is primarily made up of solid materials, usually semiconductors, which operates by the movement of charge carriers - electrons or holes - which undergo energy level changes within the material and can modify an input voltage to achieve rectification, amplification, or switching action. Active solid-state electronic devices include diodes, transistors, thyristors, etc., but exclude pure resistors, capacitors, inductors, or combinations solely thereof. The latter category is characterized as passive.

ALLOY JUNCTION

A fused junction produced by combining one or more elemental impurity metals with a semiconductor. Typical alloyed junctions include indium-germanium and aluminum-silicon.

AUTODOPING

The introduction via the vapor phase of impurities from an existing substrate region (and adjacent supports, e.g., susceptors, etc.) into another substrate region, typically during growth of the same.

AVALANCHE BREAKDOWN

A sudden change from high dynamic electrical resistance to very low dynamic resistance in a reverse biased semiconductor device (e.g., a reverse biased junction between p-type and n-type semiconductor materials) wherein current carriers are created by electrons or holes which have gained sufficient speed to dislodge valence electrons. Avalanche breakdown can cause structural damage to a semiconductor device.

BAND GAP

The difference between the energy levels of electrons bound to their nuclei (valence electrons) and the energy levels that allow electrons to migrate freely (conduction electrons). The band gap depends on the particular semiconductor involved.

BARRIER REGION OR LAYER

A region which extends on both sides of a semiconductor junction in which all carriers are swept away from the junction region. The region is depleted of carriers. This is also referred to as a depletion region. Not to be confused with diffusion barrier layers associated with metallization schemes for active solid state devices.

BINARY COMPOUND

A substance that always contains the same two elements in a fixed atomic ratio.

BIPOLAR

An active solid-state electronic device in which both positive and negative current carriers are used to support current flow.

BIPOLAR TRANSISTOR

An active solid-state electronic device with a base electrode and two or more junction electrodes in which both positive and negative current carriers are used to support current flow.

BIRD"S BEAK

The lateral encroachment of the localized oxidation region associated with a recessed oxide isolation structure.

BONDING PAD

A metallized area to which an external electrical connection is to be made.

BREAKDOWN

A sudden change from high dynamic electrical resistance to a very low dynamic resistance in a reverse biased semiconductor device (e.g., a reverse biased junction between p-type and n-type semiconductor materials) wherein reverse current increases rapidly for a small increase in reverse applied voltage, and the device behaves as if it had negative electrical resistance.

CAPACITOR

A component used in electrical and electronic circuits which stores a charge of electricity, usually for very brief periods of time, with the ability to rapidly charge and discharge. A capacitor is usually considered a passive component since it does not rectify, amplify, or switch and because charge carriers do not undergo energy level changes therein, although some active solid state devices function as voltage variable capacitors.

CHANNEL

A path for conducting current between a source and drain of a field effect transistor.

CHANNEL STOP

Means for limiting channel formation in a semiconductor device by surrounding the affected area with a ring of highly doped, low resistivity semiconductor material. In a field effect transistor, it is a region of highly doped material of the same type as the lightly doped substrate used to prevent leakage paths along the chip surface from developing. Also referred to as "chanstop."

CHANNEL PINCH-OFF REGION

The location in a current channel portion of a field effect transistor (FET) where the current is reduced to a minimum value due to its diameter being reduced to a minimum.

CHARGE CARRIER

A mobile conduction electron or hole in a semiconductor.

CHARGE CONFINEMENT

Restriction of electrical charge carriers (e.g., electrons or holes) to specified locations (e.g., by quantum wells, gate electrode potentials, etc.).

CHARGE INJECTION DEVICE

A field effect device in which storage sites for packets of electric charge are induced at or below the surface of an active solid-state device by an electric field applied to the device and wherein carrier potential energy per unit charge minima are established at a given storage site and such charge packets are injected into the device substrate or into a data bus. This type device differs from a charge transfer device in that, in the latter, charge is transferred to adjacent charge storage sites in a serial manner, whereas, in a charge injection device, the charge is injected in a nonserial manner to the device substrate or to a data bus.

CHIP

A single crystal substrate of semiconductor material on which one or more active or passive solid-state electronic devices are formed. A chip may contain an integrated circuit. A chip is not normally ready for use until packaged and provided with external connectors.

CHIP CARRIER

A package with terminals, for solid-state electronic devices, including chips which facilitates handling of the chip during assembly of the chip to other electronic elements.

CLADDING BARRIER

A higher band gap material which encases a lower band gap material that defines the walls of a quantum well.

COHERENCE LENGTH

The typical distance an electron can travel before it is scattered (e.g., by a phonon, a defect, or an impurity, etc.).

COHERER

A term which encompasses both active and passive type devices, the passive type being a resistor whose resistance decreases when subjected to a high frequency signal, and the active type being a rectifier which is made up of active solid-state particles which conduct and rectify current when connected into a cohesive element but which loses that characteristic when the particles are separated (e.g., by shaking a container in which the particles are located, etc.).

COLLECTOR DIFFUSION ISOLATION (CDI)

An electrical isolation technology used for bipolar devices which employs an epitaxial layer, which forms transistor base regions, laid on a substrate of the same conductivity type (p or n) as the epitaxial layer, with an opposite conductivity type region, more heavily doped than the epitaxial base layer and located between the layer and the substrate, forming the collector and isolating the transistor from the substrate.

COMPOUND SEMICONDUCTOR

A semiconductor composed of a chemical compound formed of elements from two or more different groups of the chemical periodic chart (e.g., Group III (B, Al, Ga, In) and Group V (N, P, As, Sb) for the following compounds: AlP, AlAs, AlSb, GaP, GaAs, GaSb, InP, InAs, and InSb, or a compound of silicon and carbon (SiC)).

CONDUCTION BAND

A partially filled energy band in which electrons can move freely, permitting a material to carry electric current where electrons are the current carriers.

CONDUCTION ELECTRONS

In a conductor or n-type semiconductor, outer shell electrons that are bound so loosely that they can move freely in the conduction band of a solid material under the influence of an electric field.

CONNECTOR AREA

That portion of the electrical conductors (e.g., bonding pad, die bond, etc.) used for providing external electrical connections from a component to a chip or other component.

CONTACT

The point or part of a conductor which touches another electrical conductor or electrical component to carry electrical current to or from the conductor or electrical component.

CRYSTAL DEFECT

Any nonuniformity in a crystal lattice. There are four categories of crystal defects: (a) point defects, (b) line defects, (c) area defects, and (d) volume defects. Point defects include any foreign atom at a regular lattice site (i.e., substitutional site) or between lattice sites (i.e., interstitial site), antisite defects in compound semiconductors (e.g., Ga in As or As in Ga), missing lattice atoms, and host atoms located between lattice sites and adjacent to a vacant site (i.e., Frenkel defects). Line defects, also called edge or screw dislocations, include extra planes of atoms in a lattice. Area defects include twins or twinning (i.e., a change in crystal orientation across a lattice) and grain boundaries (i.e., a transition between crystals having no particular positional orientation to one another). Volume defects include precipitates of impurity or dopant atoms caused by volume mismatch between a host lattice and precipitates.

DEEP DEPLETION

The condition in which a depletion layer formed in a MOS active device due to voltage applied to the gate electrode of the device is deeper than the maximum depth at which inversion would normally be expected to occur at room temperature in a semiconductor device at the surface closest to the gate electrode, without formation of an inversion layer.

DEEP LEVEL CENTERS

Energy levels that can act as traps located in the forbidden band of a semiconductor material that are not near the conduction or valence band edges.

DEGENERATION

Doping of a semiconductor to such an extent that the Fermi level lies within the conduction band (i.e., N+ semiconductor) or within the valence band (i.e., P+ semiconductor). Also, in circuit applications, negative feedback between two or more active solid-state devices.

DEPLETION MODE

The operation of a field effect transistor having appreciable channel conductivity for zero gate-source voltage and whose channel conductivity may be increased or decreased according to the polarity of the applied gate-source voltage, by changing the gate-to-source voltage from zero to a finite value, resulting in a decrease in the magnitude of the drain current.

DEPLETION REGION

The region extending on both sides of a reverse biased semiconductor junction in which free carriers are removed from the vicinity of the junction. It is also called a space charge region, a barrier region, or an intrinsic semiconductor region.

DEVICE (ACTIVE)

The physical realization of an individual electrical element in a physically independent body which cannot be further divided without destroying its stated function. Examples are transistors, pnpn structures, and tunnel diodes.

DIE

A tiny piece of semiconductor material, separated from a semiconductor slice, on which one or more active electronic components are formed. Sometimes called a chip.

DIE BOND

Attachment of a semiconductor chip to a substrate or chip carrier or package, usually with an epoxy, eutectic, or solder alloy.

DIFFUSED JUNCTION

A junction between two different conductivity regions within a semiconductor and which is formed by diffusion of appropriate impurity atoms into the material.

DIFFUSION BARRIER

An obstacle to the diffusion of atoms in a metallization scheme for an active solid-state device.

DIODE ISOLATION

A technique in which a high electrical resistance between an integrated circuit element and its substrate is achieved by surrounding the element with a reverse biased pn junction.

DIP (DUAL IN-LINE PACKAGE)

A chip carrier or package consisting of a plastic or ceramic body with two rows of vertical leads in which a semiconductor integrated circuit is assembled and sealed. The leads are typically inserted into a circuit board and secured by soldering.

DIRECT BAND GAP SEMICONDUCTOR

A semiconductor in which an electron transition from the conduction to the valence band, or vice versa, does not require a change in crystal momentum for electrons. Gallium arsenide is an example of a direct band gap semiconductor.

DISORDERED

Crystalline arrangement in which the different constituent atoms of a compound semiconductor randomly occupy lattice sites.

DISLOCATION

A line defect in a crystal, either of the edge type or screw type, in which the atoms are not arranged in a perfect latticelike structure. See CRYSTAL DEFECT for other examples of crystalline defects.

DMOSFET

Depletion-type metal oxide semiconductor field effect transistor. Such devices are normally in the on condition with no applied gate voltage.

DONOR IMPURITY

An element which when added to a semiconductor provides unbound or free electrons to the semiconductor which may serve as current carriers. Typically, donors are atoms which have more valence electrons than the atoms of the semiconductor material into which they are introduced in small quantities as an impurity or dopant. Since such donor impurities have more valence electrons than the semiconductor, a semiconductor doped with donor impurities is an n-type semiconductor.

DOPANT

An impurity added from an external source to a material by diffusion, coating, or implanting into a substrate, such as changing the properties thereof. In semiconductor technology, an impurity may be added to a semiconductor to modify its electrical properties or to a material to produce a semiconductor having desired electrical properties. N-type (negative) dopants (e.g., such as phosphorus for a group IV semiconductor) typically come from group V of the periodic table. When added to a semiconductor, n-type dopants create a material that contains conduction electrons. P-type (positive) dopants (e.g., such as boron for a group IV semiconductor) typically come from group III and result in conduction holes (i.e., vacancies in the electron shells).

DOPING OF SEMICONDUCTOR

Adding controlled amounts of conductivity modifying material, referred to as electrically active dopant or impurity, to a semiconductor material or to a material to produce a semiconductor having desired electrical properties for this class.

DOPING PROFILE

The point to point concentration throughout a semiconductor of an impurity atom doped into the semiconductor.

DOUBLE-DIFFUSED MOS (DMOS)

A metal oxide semiconductor having diffused junctions in which successive diffusions of different impurity types are made in the same well-defined region of the semiconductor.

DRAIN

The electrode of a field effect transistor which receives charge carriers which pass through the transistor channel from the source electrode.

DUAL GUARD-BAND ISOLATION

A type of electrical isolation of functional elements of an integrated circuit comprised of two distinct unused areas of chip surface area adjacent to the elements desired to be electrically isolated.

DYNAMIC RANDOM ACCESS MEMORY (DRAM)

Solid-state memory in which the information decays over time and needs to be periodically refreshed.

ELECTROMIGRATION

Mass transport of ions (i.e., usually metal) in a material as a response to the passage of current through the material by momentum exchange between thermally activated ions and conduction electrons.

ELECTRON-HOLE PAIR

A positive charge carrier (i.e., hole) and a negative charge carrier (i.e., electron) considered together as being created or destroyed as part of one and the same event.

ENHANCEMENT MODE

The operation of a field effect transistor which has a channel formed therein between its source and drain regions and which normally does not conduct current through its channel with zero voltage applied to its gate electrode. Voltage of the correct polarity will accumulate minority carriers in the channel to permit conduction of current in the channel, thus turning on the transistor.

EPITAXIAL LATERAL OVERGROWTH

Process of epitaxial deposition through an exposed opening in an insulating layer with deposition continuing epitaxially over the insulating layer laterally from the opening.

EPITAXY

The controlled growth of a single crystal of one material on the surface of a crystal of the material (i.e., homo) or onto another substance (i.e., hetero) so that the crystal lattice of the base material controls the orientation of the atoms in the grown single crystal layer.

ESAKI DIODE

A heavily doped pn-junction diode where conduction occurs through the junction potential barrier due to a quantum mechanical effect even though the carriers which tunnel through the potential barrier do not have enough energy to overcome the potential barrier. Esaki tunneling involves a tunneling barrier formed by a macroscopic depletion layer between n-type and p-type regions. It does not involve a resonant tunneling barrier using controlled quantum confinement, a layer located between junctions, nor a thin superlattice layer.

EXTRINSIC SEMICONDUCTOR

A semiconductor whose charge carrier concentration and, therefore, electrical properties depend on impurity atoms introduced therein.

FACE BONDED

A chip mounting technique wherein semiconductor chips are provided with small mounting pads, turned face down, and bonded directly to conductors on a substrate.

FIELD EFFECT TRANSISTOR (FET)

A unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electric field applied to the semiconductor from a control electrode. There are two main types of FETs, a junction FET and an insulated-gate FET. In the junction FET, the gate is isolated from the channel by a pn-junction. In an insulated-gate FET, the gate is isolated from the channel by an insulating layer so that the gate and channel form a capacitor with the insulating layer as the capacitor dielectric.

FIELD OXIDE

A thin (on a macroscopic scale) film made of an oxide of a material which overlies a device substrate to reduce parasitic capacitive coupling between conductors overlying the oxide and the substrate or devices below the oxide layer (e.g., in the substrate). See bird"s beak.

FLIP-CHIP

A term which describes the situation wherein a semiconductor device which has all terminations on one side thereof in the form of bump contacts, has a passivated surface, and has been flipped over and attached to a matching substrate.

FLOATING DIFFUSION

A region of a semiconductor device in which impurity atoms have been doped and which is electrically floating, that is, has no direct electrical connection.

FLOATING GATE

A gate electrode that is electrically floating, that is, has no direct electrical connection.

FORBIDDEN ENERGY BAND

The energy band of a material which is located between a solid material"s conduction and valence bands. It is defined by the amount of energy that is needed to release an electron from its valence band to its conduction band. Electrons cannot exist in this gap. They are either below it, and bound to an atom, or above it, and able to move freely.

FRAME TRANSFER CCD

A charge coupled device area imager array with a separate image area, storage area, and read-out register area, the storage area being located between the image area and the readout area. This is distinguished from an interline- transfer CCD in which the sensing and storage/readout function areas are located next to each other.

GATE

The control electrode or control region that exerts an effect on a semiconductive region directly associated therewith, such that the conductivity characteristic of the semiconductor region is altered in a temporary manner, often resulting in an on-off type switching action. The control electrode or control region of a field effect transistor is located between the source and drain electrodes, and regions thereof.

GATE ARRAY

A repeating geometric arrangement of groups of active solid-state devices, each group being connectable into a logic circuit, in one integrated, monolithic semiconductor chip.

GATE CONTROLLED DIODE

A three terminal semiconductor diode with the ability to be turned on or off by a pulse applied to its gate electrode.

GETTERING

The elimination or reduction of unwanted constituents (i.e., impurities) or defects from a substrate.

GRAPHOEPITAXY

The growth of a single crystalline layer across the surface of a nonsingle crystalline substrate by commencing growth at a seeding portion/region thereof.

GUNN DIODE

A diode in which electrons under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the conduction band of the active semiconductor device material or holes under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the valence band of the active semiconductor device material. A Gunn diode does not normally have a pn junction and cannot be used as a rectifier.

GUNN EFFECT

An intervalley transfer effect wherein electrons under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the conduction band of the active semiconductor device material, or holes under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the valence band of the active semiconductor device material.

HALL EFFECT DEVICE

An active solid-state device in which a current is flowing and is in a magnetic field perpendicular to the current, and in which a voltage is produced that is perpendicular to both the current flow direction and the magnetic field direction.

HETEROJUNCTION/HETEROINTERFACE

An interface between two dissimilar semiconductor materials. For example, one material may by InAs and the other may be InAlAs, or one material may be GaAs and the other material may be GaAlAs.

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

A heterojunction field effect transistor with impurity ions located on the side of the heterojunction with lower affinity for the charge carriers (holes or electrons) injected at the source that pass to the drain via a channel adjacent the heterojunction.

HOLE

An empty energy level in the valence band of a semiconductor crystal which exhibits properties of a real particle and can act as a mobile positive-charge carrier.

HOMOJUNCTION

An interface between regions of opposite polarity in the same semiconductor material.

HOT CARRIER DIODE

A diode in which electrons (or holes) have energies greater than those that are in thermal equilibrium with the material of at least one of the regions forming the diode. Schottky barrier diodes typically have "hot carriers" (hot electrons) injected into the metal from the semiconductor.

HYBRID CIRCUIT

A small printed circuit having miniature components which may include passive components (resistors, capacitors, and inductors) deposited on a printed circuit board.

IMPURITY

A foreign material present in a semiconductor crystal, such as boron or arsenic in silicon, which is added to the semiconductor to produce either p-type or n-type semiconductor material, or to otherwise result in material whose electrical characteristics depend on the impurity dopant atoms.

INDIRECT BAND GAP SEMICONDUCTOR

A semiconductor material in which a change in semiconductor crystal momentum for an electron is required when it moves from the conduction band to the valence band and vice versa. Silicon and aluminum arsenide are examples of indirect band gap semiconductors.

INSULATED-GATE FIELD EFFECT TRANSISTOR (IGFET)

A unipolar transistor with source, gate, and drain regions and electrodes, in which conduction takes place in a channel controlled by action of the voltage applied to the gate electrode of the device, in which the gate electrode is separated from the channel by an insulator layer.

INSULATOR

A material which has a high resistance to the flow of electric current. It has such low electrical conductivity that the flow of current therethrough can usually be neglected.

INTRINSIC CONCENTRATION

The number of minority carriers in a semiconductor due to thermal generation of electron-hole pairs.

INVERSION

A condition in a semiconductor material in which the concentration of minority carriers exceeds the concentration of majority carriers.

INVERSION LAYER/CHANNEL

A region in a semiconductor material in which the concentration of minority carriers exceeds the concentration of majority carriers.

ISOELECTRONIC

A condition in which two constituents have the same number of valence electrons.

ISOLATION

The separation or surrounding of active semiconductor regions or components with electrically insulative regions to prevent the flow of electrical current between the active semiconductor regions or between electronic component parts of a solid-state electronic device.

ISOPLANAR CMOS

A semiconductor device in which relatively thick regions of silicon dioxide, recessed into the semiconductor surface, are used to electrically isolate device areas and prevent parasitic device formation. More commonly called LOCOS CMOS.

ISOPLANAR ISOLATION

A type of electric isolation in which relatively thick regions of silicon dioxide, recessed into the semiconductor surface, are used to electrically isolate device areas and prevent parasitic device formation. More commonly called LOCOS ISOLATION.

JUNCTION BARRIER

The opposition to the diffusion of majority carriers across a pn junction due to the charge of the fixed donor and acceptor ions.

JUNCTION CAPACITANCE

The capacitance across a pn junction. It depends on the width of the depletion layer, which increases with increased reverse bias voltage across the junction.

JUNCTION ISOLATION

Electrical isolation of devices on a monolithic integrated circuit chip using a reverse biased junction diode to establish a depletion layer that forms the electrical isolation between devices.

JUNCTION RESISTANCE

The electrical resistance across a semiconductor PN junction.

LAND

The conductive areas, normally metal patterns, on a semiconductor integrated circuit, which form part of the contacts and interconnections between components on the integrated circuit. See bonding pad, die bond.

LIFT-OFF

Process for the removal of unwanted deposited material from a substrate (and thus patterning the same) by the dissolution of an intermediate layer and the commitant physical separation of the overlying deposited material.

LUMINESCENCE

The emission of visible or invisible radiation unaccompanied by high temperature by any substance as a result of absorption of exciting energy in the form of photons, charged particles, or chemical change. It is a general term which includes fluorescence and phosphorescence. Types include hemiluminescence, bioluminescence, photoluminescence, electroluminescence, photoluminescence, and triboluminescence. Active solid-state luminescent devices are semiconductors which operate via injection luminescence. Active devices include pn junctions (including heterojunctions), Schottky barrier junctions, metal-insulator-semiconductor (MIS) structures, and high speed traveling domains (e.g., Gunn domain and acoustoelectric wave generated domains). Passive solid-state electroluminescent devices (phosphors) are insulators which operate in an intrinsic luminescence phenomena (i.e., where an applied electric field generates free carriers) to initiate the light emission mechanism, there being no free carriers in an insulator to be accelerated by an applied field unless the field also generates them.

MAJORITY CARRIER

The predominant charge carrier in a semiconductor. Electrons are majority carriers in n-type semiconductors. Holes are majority carriers in p-type semiconductors.

MASTERSLICE ARRAY/MASTERCHIP

A substrate that contains active and passive electronic components in a predetermined pattern which may be connected into different logic or analog circuits.

MBM JUNCTION

Active solid-state devices having metal-barrier-metal layer junctions.

METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)

See Insulated-gate Field Effect Transistor.

METALLIZATION

Process of coating (a) metal or (b) other material which is identified as having the conductive characteristic of a metal onto a semiconductor or a substrate containing semiconductor regions to form electrodes, contacts, interconnects, bonding pads, or heat sinks and also including formation of conductive material by doping of nonconductive material.

MIM DIODE

A junction diode with a thin insulating layer of material sandwiched between two metallic surface layers which operates as a tunneling (direct or Fowler-Nordheim type) diode.

MINORITY CARRIER

The less predominant charge carrier in a semiconductor. In a p-type semiconductor, minority carriers are electrons, whereas in n-type semiconductor material, minority carriers are holes.

MIS

Acronym for metal-insulator-semiconductor. Typically active solid-state devices with MIS technology have a silicon dioxide layer formed on a single crystal silicon substrate. A polysilicon conductor layer is formed on the oxide.

MOBILITY

The facility with which carriers move through a semiconductor when subjected to an applied electric field. Electrons and holes typically have different mobilities in the same semiconductor.

MODFET

Acronym for a modulation doped field effect transistor. A high speed semiconductor FET in which dopant atoms containing semiconductor layers alternate with nondoped semiconductor layers, so that the carriers (electrons or holes) resulting from the dopant atoms can travel in the undoped material, so that there is little scattering of carriers from dopant atoms. Typically, the dopant atoms are in semiconductor material having a lower carrier affinity than the undoped layers to facilitate carrier spill over into the undoped layers. Such a structure may typically constitute a superlattice. See also High Electron Mobility Transistor.

MONOLITHIC DEVICE (E.G., IC, ETC.)

A device in which all components are fabricated on a single chip of silicon. Interconnections among components are provided by means of metallization patterns on the surface of the chip structure, and the individual parts are not separable from the complete circuit. External connecting wires are taken out to terminal pins or leads.

MSM

Acronym for metal-semiconductor-metal semiconductor device. Active solid-state semiconductor devices having a semiconductor layer sandwiched between two layers of metal and forming back-to-back Schottky diodes.

NEGATIVE RESISTANCE REGION

An operating region of an active solid-state electronic device in which an increase in applied voltage results in a decrease in output current.

NEGATIVE TEMPERATURE COEFFICIENT

The amount of reduction in a device parameter, such as capacitance or resistance, for each degree of device operating temperature.

NMOS

N-channel metal oxide semiconductor devices which use electrons as majority carriers.

NONDOPANT

An impurity added from an external source which does not modify the electrical properties of a semiconductor.

NPN TRANSISTOR

A bipolar transistor with n-type emitter and collector regions separated by a p-type base.

N-CHANNEL FET

A field effect transistor that has an n-type conduction channel.

N-TYPE SEMICONDUCTOR

An extrinsic semiconductor having n-type dopant atoms (e.g., atoms with one or more valence electron than the host atoms). Electron density exceeds hole density.

ORDERED

Crystalline arrangement in which different constituent atoms of a compound semiconductor occupy specific lattice sites resulting in long range regularity of the resultant structure.

OUTDIFFUSION

The solid-state diffusion of impurities from the underlying substrate into a deposited layer during the growth thereof.

PACKAGE

A container, case, or enclosure utilized in the context of semiconductor art for protecting a solid-state electronic device from the environment and which is considered a part of a manufacture product (i.e., as opposed to a package utilized for passage of a product through the channels of trade in a safe, convenient, and attractive condition).

PAD

A. The portion of a conductive pattern on a solid-state electronic device for making external connection thereto. B. The portion of a conductive pattern on a chip or a printed circuit board designed for mounting or attaching a substrate or solid-state active electronic device. See also bonding pad, die bond, etc.

PARASITIC DEVICES/CHANNELS

A. Junctions forming unintended interconnection of intended active solid-state devices. B. Devices which were not designed to carry current flow and which result from unintended interconnection of intended active solid-state devices.

PASSIVE DEVICE

A solid-state electronic device or component in which charge carriers do not change their energy levels and that does not provide rectification, amplification, or switching, but which does react to voltage and current. Examples are pure resistors, capacitors, and inductors.

P-CHANNEL

A conduction path, made of p-type semiconductor material, located between source and drain of a field effect device.

PHOTODIODE

A diode in which charge carriers are created by light which illuminates the diode junction. It is a photovoltaic as well as a photoconductive device.

PINCH-EFFECT RESISTOR

A monolithic integrated circuit resistor having a layer of one conductivity type, typically a P-layer formed at the same time as integrated circuit bipolar transistor base regions, which is thinned by an inset region of opposite conductivity type, typically an N-layer formed at the same time as integrated circuit bipolar transistor emitter regions.

PIN DIODE/DEVICE

A diode having an intrinsic semiconductor (i.e., one with no dopants) sandwiched between a p-type layer and an n-type layer. The depletion region (the intrinsic semiconductor layer) thickness can be tailored to optimize quantum efficiency for use as a photo diode or frequency response for use as a microwave diode.

PIN-GRID ARRAY

A semiconductor chip package having leads in the form of pins arranged in columns and rows.

PLANAR TRANSISTOR

A bipolar transistor in which the emitter base and collector regions terminate at the same plane surface without indentations in or protrusions from the surface. Hence, the emitter and base regions form dish-shaped portions extending into the semiconductor from the common surface.

PN-JUNCTION

The interface and region of transition between p-type and n-type semiconductors. See also barrier layer.

PN-JUNCTION DIODE

A semiconductor device having two terminals connected to opposite-type semiconductor materials with a junction therebetween and exhibiting a nonlinear voltage-current characteristic, usually used for switching or rectification.

PNP TRANSISTOR

A bipolar transistor with p-type emitter and collector regions separated by an n-type base.

POINT DEFECT

A crystal defect occurring at a point in a crystal. Examples include (a) a foreign atom incorporated into the crystal lattice at either a substitutional (regular lattice) site or interstitial (between regular lattice sites) site, (b) a missing atom in the lattice, or (c) a host atom located between regular lattice sites and adjacent to a vacancy (called a Frenkel defect). See CRYSTAL DEFECT for other examples of crystalline defects.

POLYSILICON

A polycrystalline form of silicon.

POTENTIAL BARRIER

The difference in electrical potential across a pn junction in a semiconductor. See also barrier layer.

POTTING

An embedding process in which an electronic component is placed in a can, shell, or other container and buried in a fluid dielectric which subsequently is hardened material. Even though the container is not removed from the finished part, this is considered a molding operation since the fluid is confined to a definite shape during hardening.

PRINTED CIRCUIT BOARD

A structure formed on one or more layers of electrically insulating material having electrical terminals and conductive material deposited thereon, in continuous paths, from terminal to terminal, to form circuits for electronic apparatus such as chips or substrates.

P-TYPE

An extrinsic semiconductor in which the hole density exceeds the conduction electron density.

PUNCHTHROUGH

Expansion of a depletion region* from one junction to another junction in an active solid-state device.

QUANTUM TRANSISTOR

Transistors whose operation is based on the properties of electrons confined in quantum wells - semiconductor films only a hundred or so angstroms thick sandwiched between high confining walls made of a second semiconductor material.

QUANTUM WELL

Semiconductor films only a hundred or so angstroms thick sandwiched between high confining walls made of a second material.

RECOMBINATION

The process by which excess holes and electrons in a semiconductor crystal recombine and no longer function as charge carriers in the semiconductor. Basic recombination processes are band-to-band recombination which occurs when an electron in the conduction band recombines with a hole in the valence band, and trapping recombination which occurs when an electron or hole is captured by a deep energy level, such as produced by a deep level dopant, before recombining with an opposite conductivity-type carrier.

RESISTIVITY

A measure of the resistance of a material to electric current. Resistivity is a bulk material property measured in ohm-cm.

RESONANT TUNNELLING DEVICE

A device that works on the principle of resonant electron (or hole) tunneling through a pair of matched potential barriers. This occurs when the energy of the electrons (or holes) matches that of a quantum energy level in the quantum well formed between the barriers.

SEMICONDUCTOR

A. A generic term for (1) a substance or material whose electronic conductivity at ordinary temperature is intermediate between that of a metal and an insulator and whose conductivity is capable of being modified by the addition of a dopant or (2) an electronic device the main functioning parts are made from semiconductor materials.

B. For the purposes of Class 438, a semiconductor material (1) must have resistivity between that of an insulator and a conductor and (2) be intended for use in a solid state device for at least one of the following purposes: (a) conducting or modifying an electrical current, (b) storing electrical energy for subsequent discharge,or (c) converting electromagnetic wave energy to electrical energy or electrical energy to electromagnetic energy. The resistivity is commonly changed by light, heat, or electric or magnetic fields incident on the material.

SEMICONDUCTOR JUNCTION

The region of transition, which usually exhibits asymmetric conductivity, between two joined semiconductors of different electrical properties or of joined semiconductor and conductor (e.g., metal, etc.) and which is also referred to in the art as a barrier layer. Types of junctions include heterojunctions, Schottky barrier junctions, and PN junctions.

SILICON ON INSULATOR (SOI)

A semiconductor structure using an insulating substrate, instead of silicon as a substrate material, with an overlying active layer of single crystal silicon containing active solid state devices. The substrate may typically be of the form of an insulating layer which is itself formed on a single crystal substrate.

SILICON ON SAPPHIRE (SOS) CMOS

A complementary metal oxide semiconductor device (e.g., a transistor) wherein single crystal silicon is grown on a passive insulating base of sapphire (single crystal alpha phase aluminum oxide) with complementary MOS transistors formed in the silicon in one or more island portions.

SINGLE CRYSTAL

A body of material having atoms regularly located at periodic lattice sites throughout.

SINKER

A buried electrically conductive, low resistance path in an integrated circuit which connects an electrical contact to a conductive region buried in the integrated circuit. It may be made up of a heavily doped impurity region.

SOLID-STATE DEVICE

An electronic device or component that uses current flow through solid (as opposed to liquid), gas, or vacuum materials. Solid-state devices may be active or passive.

SOURCE

In a field effect transistor, the active region/electrode to which the source of charge carriers is connected.

SPACE CHARGE REGION

The region around a pn junction in which holes and electrons recombine to leave no mobile charge carriers and a net charge density due to the residual dopant ions.

SPIKING

Phenomena associated with electromigration wherein a fingerlike protrusion of a metallization layer is allowed to grow through a dielectric layer and eventually contact a further layer.

SUBSTRATE

A. A base upon which a coating is formed. See the class definition for the requirements for coating, per se, or etching, per se, when a base of semiconductor or containing a semiconductive region is the substrate. B. The supporting material on or in which the components of an integrated circuit are fabricated or attached.

SUPERLATTICE

A periodic sequence of variations in carrier potential energy in a semiconductor, of such magnitude and spacing that the current carrier wave function is spread out over many periods, so that carrier energy and other properties are determined in part by the periodic variations. The variation may be in chemical composition of the material, as in a sequence of heterojunctions, or in impurity concentration, forming a doping superlattice, or both.

SURFACE MOUNT DEVICES

Active or passive solid-state devices which are structured and configured to be mounted directly to a printed circuit board surface. This type of mounting is distinguished from "through-hole" mounting which involves the electrical and physical connection of devices to a printed circuit board using drilled and plated holes through the conductive pattern of the board.

SURFACE RESISTIVITY

The resistance of a material between two opposite sides of a unit square of its surface. Also called Sheet Resistance. Measured in ohms, often written as "ohms per square" in this case.

THERMISTOR

A thermoelectric device whose electrical resistance varies with temperature. Its temperature coefficient of resistance is high, nonlinear, and usually negative.

THIN-FILM

A material on a substrate with a thickness not greater than 10 microns and uniformity within 20% of it"s average value (Grant and Hackh"s Chemical Dictionary, 5th Edition, edited by Roger & Claire Grant, McGraw-Hill, Inc., 1987, page 235).

THICK-FILM DEVICES

Printed thin-film circuits. Silk screen printing techniques are used to make the desired circuit patterns on a ceramic substrate. Active devices may be added thereto as separate devices (see HYBRID CIRCUIT).

THIN-FILM DEVICES

Solid-state electronic devices which are constructed by depositing films of conducting material on the surface of electrically insulating bases.

THYRISTOR

A four layer p-n-p-n bistable switching device that changes from an off or blocking state to an on or conducting state which uses both electron and hole-type carrier transport.

TRANSFERRED ELECTRON DEVICE

See GUNN EFFECT. In such devices, advantage is taken of the negative differential mobility of electrons or holes in certain semiconducting compounds, particularly GaAs or InP.

TRANSISTOR

An active solid-state semiconductor device having three or more electrodes in which the current flowing between two specified electrodes is modulated by the voltage or current applied to one or more specified electrodes, and is capable of performing switching or amplification. May be of unipolar type (i.e., field effect transistor) or bipolar type.

TRAPATT DEVICE

An acronym for trapped plasma avalanche triggered transit diodes, which are biased into avalanche condition. As the diode breaks down, a highly conducting electron-hole plasma quickly fills the entire n-type region, and the voltage across the diode drops to a low value. The plasma is then extracted from the diode by the low residual electric field, thus causing a large current flow even though the voltage is low. Once extraction of the plasma is completed, the current drops and the voltage rises.

TRENCH ISOLATION

Electrical isolation of electronic components in a monolithic integrated circuit by the use of grooves or other indentations in the surface of the substrate, which may or may not be filled with electrically insulative (i.e., dielectric) material.

TUNNEL DIODE

A semiconductor diode in which the electrons penetrate a quantum barrier that is impenetrable in terms of classical physics, but which is penetrable in terms of quantum physics due to the quantum mechanical uncertainty in position of current carriers.

TWO-DIMENSIONAL ELECTRON GAS

A description of the motion of electrons which are confined in only one direction, such as electrons in the conducting channel of a MOSFET. In an electron gas, the electrons move around without apparent restriction. The behavior of electrons in conducting metals (e.g., copper) is an example of a three-dimensional electron gas. In a two dimensional electron gas, motion is restricted to a single plane (two dimensions). See also MODFET.

UNIPOLAR

An active solid-state electronic device in which only one type of charge carrier (i.e., positive holes or negative electrons) is used to support current flow.

VARACTOR

A semiconductor diode comprising a two terminal active device using the voltage variable capacitance of a pn junction or a Schottky junction that changes capacitance with a change in applied voltage.

VARISTOR

A varistor is a two-electrode active or passive semiconductor device with a voltage dependent nonlinear resistance which falls significantly as the voltage is increased. In an active device, the nonlinear property is due to the presence of one or more potential barriers. In a passive-type varistor, it is due to electrical heating of the material due to current flow therethrough. Varistors are to be contrasted with passive variable resistors such as rheostats or potentiometers.

VIA

A metallized or plated-through hole in an insulating layer, a semiconductor containing substrate or chip, or a printed circuit board which forms a conduction path itself without having a wire or lead inserted therethrough.

WAFER

A thin slice of semiconductor material with parallel faces used as the substrate for active solid-state devices in discrete or monolithic integrated circuit form.

WIRING CHANNEL

An area on an integrated circuit, such as a gate array, which is left free of active devices and in which interconnection metallization patterns are formed.

WORK FUNCTION

The minimum energy required to remove an electron from the Fermi level of a material and liberate it to free space outside the solid.

ZENER DIODE

A single pn junction, two terminal semiconductor diode reversed biased into breakdown caused by the Zener effect (i.e., by field emission of charge carriers in the device"s depletion layer). NOTE: True Zener breakdown occurs in silicon at values below 6 volts. It is to be distinguished from the avalanche breakdown mechanism that occurs in reverse biased diodes at higher (about 6 volts) voltages.

SUBCLASSES

[List of Patents for class 438 subclass 1]

HAVING BIOMATERIAL COMPONENT OR INTEGRATED WITH LIVING ORGANISM:

This subclass is indented under the class definition. Process for making an electrical device utilizing a semiconductor substrate which contains a component identical to material found in a living organism or is integrated with a living organism.

SEE OR SEARCH CLASS:

128,	Surgery, for a method of treatment of a living body or organism.
429,	Chemistry: Electrical Current Producing Apparatus, Product, and Process, subclass 2 for subject matter under the class definition having living matter (e.g., microorganism, etc.).

[List of Patents for class 438 subclass 2]

HAVING SUPERCONDUCTIVE COMPONENT:

This subclass is indented under the class definition. Process for producing an electrical device utilizing a semiconductor substrate having an electrically conductive component which at temperatures of less than or equal to 30K is able to conduct electricity in the absence of resistance.

SEE OR SEARCH CLASS:

29,	Metal Working, subclasses 25.01+ for manufacturing a nonsemiconductor-type barrier layer device and subclass 599 for a method of mechanical manufacture of a superconductor electrical device.
257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclasses 30+ for an active solid-state device in which the active layer through which carrier tunnelling occurs has a lower conductivity than the material adjacent thereto, especially subclasses 31+ for Josephson junction devices, and subclasses 661+ for a superconductive contact or lead.
331,	Oscillators, subclass 107 for superconductive element and tunnelling element oscillators.
427,	Coating Processes, subclasses 62+ for a process of coating, per se, wherein the product is a superconductive electrical device.
505,	Superconductor Technology: Apparatus, Material, Process, particularly subclass 330 for a process of manufacturing a semiconductor electrical device having a superconductive component possessing an operating temperature greater than 30K and subclass 923 for a process of making a semiconductor electrical device having a superconductive component possessing an operating temperature of less than 30K.

[List of Patents for class 438 subclass 3]

HAVING MAGNETIC OR FERROELECTRIC COMPONENT:

This subclass is indented under the class definition. Process for making an electrical device wherein the semiconductor substrate has integral therewith a component with recited magnetic or ferroelectric properties.

SEE OR SEARCH THIS CLASS, SUBCLASS:

48,	for a process of manufacturing an electrical device or circuit utilizing a semiconductor substrate, said device or circuit being responsive to an external magnetic signal.

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 295 for an insulated gate field effect transistor having a ferroelectric material layer.
427,	Coating Processes, subclasses 127+ for coating a magnetic base or coating a base with a magnetic material.

[List of Patents for class 438 subclass 4]

REPAIR OR RESTORATION:

This subclass is indented under the class definition. Process for the renewal, reconstruction, or refurbishment of the previously possessed electrical or mechanical properties of a semiconductor electrical device which have become degraded.

(1) Note. This subclass includes patents to a process of removing and replacing a defective chip from a package as well as a process of repair of defective electrical conduct paths (e.g., wirings).

[List of Patents for class 438 subclass 5]

INCLUDING CONTROL RESPONSIVE TO SENSED CONDITION:

This subclass is indented under the class definition. Process including the step of regulating an operation by detecting a characteristic or a change in a characteristic of the process or the semiconductor substrate acted upon and by implementing an action in the process based upon the detected characteristic or change therein.

(1) Note. There must be a positive action carried out in response to the detected characteristic or change therein which furthers the semiconductor substrate toward its subsequent indented utilization. Thus, the removal of defective devices or substrates from a manufacturing process flow (e.g., by sorting, etc.) or the identification of same (e.g., by inking, etc.) is not deemed to be a positive action proper for this subclass.

SEE OR SEARCH CLASS:

209,	Classifying, Separating, and Assorting Solids, especially subclasses 552+ for methods sensing a condition of an item and controlling the separation in accordance therewith.
340,	Communications: Electrical, for control responsive indicating systems not having structural details, especially subclass 653 for electronic circuit or component and subclasses 657+ for electrical characteristic.
365,	Static Information Storage and Retrieval, subclass 201 for testing of memory systems.
377,	Electrical Pulse Counters, Pulse Dividers or Shift Registers: Circuits and Systems, subclasses 28+ for error checking of pulse counters.
714,	Error Detection/Correction and Fault Detection/Recovery, appropriate subclasses for diagnostic testing, per se, particularly subclasses 100+ for reliability and availability, fault recovery, locating and avoidance, diagnostic testing or monitoring of a digital processing system for reliability purpose.

[List of Patents for class 438 subclass 6]

Interconnecting plural devices on semiconductor substrate:

This subclass is indented under subclass 5. Process for electrically connecting multiple electrical devices on a monolithic semiconductive substrate to establish a desired circuit pattern (e.g., wiring, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:

128,	for a process of forming an array of electrical devices and selectively interconnecting the devices to produce a desired electrical circuit.

[List of Patents for class 438 subclass 7]

Optical characteristic sensed:

This subclass is indented under subclass 5. Process wherein the sensed condition is an optical property of the device or an optical property of the process.

(1) Note. Optical aligning, per se, is not deemed to be a control responsive operation for the purposes of this subclass.

SEE OR SEARCH CLASS:

348,	Television, subclasses 86+ for manufacturing wherein a picture signal generator (i.e., television camera) is utilized for monitoring a manufacturing operation.
356,	Optics: Measuring and Testing, for optical alignment processes.
382,	Image Analysis, for methods for the automated analysis of an image or recognition of a pattern, including measuring significant characteristics of the image or pattern.

8	Chemical etching:
	This subclass is indented under subclass 7. Process having a step of chemically etching the semiconductor substrate in conjunction with the sensing of an optical property of the process or of the semiconductor device.

9	Plasma etching:
	This subclass is indented under subclass 8. Process wherein the chemical etching step utilizes an ionized chemically reactive gas to etch the semiconductor substrate.

[List of Patents for class 438 subclass 10]

Electrical characteristic sensed:

This subclass is indented under subclass 5. Process wherein the sensed condition is an electrical property of the device or an electrical property of the process.

SEE OR SEARCH CLASS:

209,	Classifying, Separating, and Assorting Solids, especially subclasses 571+ for methods of electrical testing thereby sensing a property of an item to facilitate subsequent separation.

[List of Patents for class 438 subclass 11]

Utilizing integral test element:

This subclass is indented under subclass 10. Process wherein the electrical property is sensed utilizing a specific test structure integral to the semiconductor substrate and which has no other function in the completed device.

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 48 for test or calibration structures provided on active solid-state devices to permit or facilitate the measurement, test, or calibration of the characteristics of the devices.

[List of Patents for class 438 subclass 12]

And removal of defect:

This subclass is indented under subclass 10. Process wherein a defect detected by the electrical sensing step is thereafter removed.

SEE OR SEARCH THIS CLASS, SUBCLASS:

4,	for a process of repairing or restoring the previously possessed electrical or mechanical properties of a semiconductor electrical device which have become degraded.

13	Altering electrical property by material removal:
	This subclass is indented under subclass 10. Process whereby following or as a result of the electrical sensing step, an electrical property of the semiconductor substrate is altered by a material removal step (e.g., by etching).

[List of Patents for class 438 subclass 14]

WITH MEASURING OR TESTING:

This subclass is indented under the class definition. Process having combined therewith a step of measuring or testing a condition of the process or of the device made thereby.

(1) Note. Processes having at least one step proper for the class and combined therewith a step of electrical aging or burn-in are classified herein.

SEE OR SEARCH CLASS:

209,	Classifying, Separating, and Assorting Solids, especially subclasses 571+ for methods of electrical testing thereby sensing a property of an item to facilitate subsequent separation.
250,	Radiant Energy, subclasses 306+ for inspection of solids or liquids by charged particles, and subclass 371 for invisible radiant energy responsive methods using semiconductor devices.
324,	Electricity: Measuring and Testing, for per se electrical measuring, especially subclass 71.5 for determining a nonelectrical property of a semiconductor by measuring an electrical property, subclass 451 for determining a material property using thermoelectric phenomenon, subclasses 500+ for fault detecting in electrical circuits and of electrical components, and subclass 719 for semiconductor materials quality determination using conductivity effects.
374,	Thermal Measuring and Testing, especially subclass 57 for thermal testing of susceptibility to thermally induced deterioration, flaw, etc., and subclass 178 for thermal measuring utilizing a barrier layer (e.g., semiconductive junction) sensing element.

15	Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:
	This subclass is indented under subclass 14. Process provided including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

[List of Patents for class 438 subclass 16]

Optical characteristic sensed:

This subclass is indented under subclass 14. Process wherein the sensed condition is an optical characteristic of the process or of the device made thereby.

(1) Note. Optical aligning per se is not deemed to be a measurement of an optical characteristic and as such would not bring original classification to this subclass solely based on that claimed feature.

SEE OR SEARCH CLASS:

348,	Television, subclasses 86+ for manufacturing wherein a picture signal generator (i.e., television camera) is utilized for monitoring a manufacturing operation.
356,	Optics: Measuring and Testing, for optical alignment processes.
382,	Image Analysis, especially subclasses 141+ , for a manufacturing process using image analysis, aligning images/masks, or pattern recognition.

[List of Patents for class 438 subclass 17]

Electrical characteristic sensed:

This subclass is indented under subclass 14. Process wherein the sensed condition is an electrical characteristic of the process or of the device made thereby.

SEE OR SEARCH CLASS:

324,

Electricity: Measuring and Testing, for per se electrical measuring, especially subclass 71.5 for determining a nonelectrical property of a semiconductor by measuring an electrical property, subclass 451 for determining a material property using thermoelectric phenomenon, subclasses 500+ for fault detecting in electrical circuits and of electrical components, and subclass 719 for semiconductor materials quality determination using conductivity effects.

[List of Patents for class 438 subclass 18]

Utilizing integral test element:

This subclass is indented under subclass 17. Process wherein the electrical property is sensed utilizing a specific test structure integral to the semiconductor substrate and which has no other function in the completed device.

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 48 for test or calibration structures provided on active solid-state devices to permit or facilitate the measurement, test, or calibration of the characteristics of the devices.

[List of Patents for class 438 subclass 19]

HAVING INTEGRAL POWER SOURCE (E.G., BATTERY, ETC.):

This subclass is indented under the class definition. Process for making a semiconductor electrical device having therewith an integral structure capable of chemically or radioactively generating electrical power.

SEE OR SEARCH CLASS:

136,	Batteries: Thermoelectric and Photoelectric, subclass 202 for apparatus wherein nuclear energy other than that resulting from an induced nuclear reaction is used as a heat source for the generator or comprising a thermoelectric device designed to be employed as an ancillary unit in a nuclear reactor system.
310,	Electrical Generator or Motor Structure, subclass 303 for the combination of a semiconductor junction and a radioactive source which radiates the semiconductor material and thus generates a source of current for an external load.
376,	Induced Nuclear Reactions: Processes, Systems, and Elements, subclasses 320+ for the direct conversion of the energy produced in a nuclear reaction into an electrical output by a one-step process or apparatus for accomplishing such one-step process.
429,	Chemistry: Electrical Current Producing Apparatus, Product, and Process, especially subclass 7 for a combination including a nonbattery electrical component electrically connected within a cell casing other than testing or indicating components.

[List of Patents for class 438 subclass 20]

ELECTRON EMITTER MANUFACTURE:

This subclass is indented under the class definition. Process for manufacturing a structure which gives off electrons into free space utilizing a semiconductor substrate.

(1) Note. Some materials may variously be conductive, semiconductive, or insulative. See section A. above for an expansion of what comprises a semiconductor substrate for the purposes of this class.

SEE OR SEARCH CLASS:

136,	Batteries: Thermoelectric and Photoelectric, subclass 254 for a photoemissive photoelectric cell.
257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclasses 10+ for devices having a low workfunction layer for electron emission.
313,	Electric Lamp and Discharge Devices, especially subclass 346 for cathodes containing or coated with electron emissive material, subclasses 499+ for subject matter under the class definition having semiconductor depletion layer-type luminescent material, and subclass 546 for photosensitive photocathodes.
427,	Coating Processes, subclasses 74+ for coating processes which result in a photoelectric or photovoltaic product (e.g., a photocathode) which is responsive to visible, infrared, or ultraviolet illumination by (a) emitting electrons, (b) generating an electromotive force, or by (c) varying electrical conductivity.
445,	Electric Lamp or Space Discharge Component or Device Manufacturing, for a process of manufacturing a nonsemiconductive-type space discharge device.

[List of Patents for class 438 subclass 21]

MANUFACTURE OF ELECTRICAL DEVICE CONTROLLED PRINTHEAD:

This subclass is indented under the class definition. Process for manufacturing from a semiconductor substrate an electrical device utilized for the transfer to another surface of an imprint or mark which transfer is regulated by the electrical device.

SEE OR SEARCH CLASS:

29,	Metal Working, subclass 890.1 for fluid pattern dispersion device manufacture (e.g., ink jet manufacture).
347,	Incremental Printing of Symbolic Information, subclasses 1+ for ink jet marking apparatus, subclasses 159+ for electrical discharge marking apparatus, subclasses 163+ for electrochemical marking apparatus, and subclasses 171+ for thermal marking apparatus.

[List of Patents for class 438 subclass 22]

MAKING DEVICE OR CIRCUIT EMISSIVE OF NONELECTRICAL SIGNAL:

This subclass is indented under the class definition. Process for making a semiconductor electrical device or circuit which is emissive of a nonelectrical output during operation.

(1) Note. The nonelectrical signal serving as input stimulus to the device or circuit may be described as an information carrying wave.

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclasses 13 , 79 through 103, and 918 for incoherent light emitting injection luminescent devices.
372,	Coherent Light Generators, for coherent light emissive devices, in particular subclasses 43.01+ for a semiconductive laser device and subclass 75 for semiconductor optical laser pump devices.
430,	Radiation Imagery Chemistry: Process, Composition, or Product Thereof, subclasses 311+ for electrical device manufacture involving photolithography, and subclass 321 for nonelectro-optic device manufacture involving photolithography.

23	Having diverse electrical device:
	This subclass is indented under subclass 22. Process for manufacturing a circuit composed of a plurality of electrical devices integrated on a common substrate or chip of monolithic construction, at least one of the devices being emissive of nonelectrical signal.

[List of Patents for class 438 subclass 24]

Including device responsive to nonelectrical signal:

This subclass is indented under subclass 23. Process for making a circuit comprising a combination of a device emissive of nonelectrical signal and a device responsive to nonelectrical signal integrated onto a common substrate or chip of monolithic or hybrid construction.

SEE OR SEARCH CLASS:

65,	Glass Manufacturing, especially subclasses 406+ for process of glass bonding an optical fiber to a substrate.
250,	Radiant Energy, subclass 551 for signal isolators, including optically coupled light emitters and semiconductor light receivers.
257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclasses 80 through 85for an incoherent light emitter coupled to an active solid-state light responsive device, per se.
372,	Coherent Light Generators, for coherent light emissive devices, in particular subclasses 43.01+ for a semiconductive laser device and subclass 75 for semiconductor optical laser pump devices.
385,	Optical Waveguides, subclass 14 for a laser in integrated optical circuit, subclasses 129+ for a planar optical waveguide, and subclasses 141+ for a waveguide having a particular optical characteristic modifying chemical composition.

25	Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:
	This subclass is indented under subclass 24. Process including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

[List of Patents for class 438 subclass 26]

Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:

This subclass is indented under subclass 22. Process including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:

64,	for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device responsive to electromagnetic radiation.
106,	for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device.

[List of Patents for class 438 subclass 27]

Having additional optical element (e.g., optical fiber, etc.):

This subclass is indented under subclass 26. Process for making a semiconductor device wherein the device has combined therewith one or more separate optical elements to transmit or modify electromagnetic radiation incident from the semiconductor device and wherein the optical element is affixed or joined to the semiconductor device.

SEE OR SEARCH CLASS:

65,	Glass Manufacturing, especially subclass 406 for processes which involve assembling at least two individually distinct optical fibers, waveguides, or preforms directly to each other (e.g., coupling, etc.)
323,	Electricity: Power Supply or Regulation Systems, subclass 902 for optical coupling to a semiconductor.

28	Plural emissive devices:
	This subclass is indented under subclass 26. Process for making a collection or grouping of multiple devices emissive of a nonelectrical signal in a single coherent monolith.

29	Including integrally formed optical element (e.g., reflective layer, luminescent material, contoured surface, etc.):
	This subclass is indented under subclass 22. Process for making a semiconductor device wherein the device has combined therewith one or more optical elements to transmit or modify electromagnetic radiation incident from the semiconductor device.

[List of Patents for class 438 subclass 30]

Liquid crystal component:

This subclass is indented under subclass 29. Process for making a semiconductor device wherein the additional optical element is a substance, usually organic with at least one polarizable group, capable of unidirectional molecular alignment in layers, giving rise to optical bifringement.

(1) Note. Liquid crystals, on variation in pressure, temperature, electric current passing therethrough, etc., change their colors or light transmitting ability, the cholesteric type changing colors while the nematic-type changes between transparency and opacity.

SEE OR SEARCH CLASS:

345,	Computer Graphics Processing and Selective Visual Display Systems, subclasses 87+ for a display element control system for liquid crystal display elements arranged in a matrix configuration.
349,	Liquid Crystal Cells, Elements and Systems, particularly subclasses 187+ for nominal manufacturing methods or postmanufacturing processing of liquid crystal cells.

31	Optical waveguide structure:
	This subclass is indented under subclass 29. Process for making a semiconductor device wherein the additional optical element is an optical conduit for the transmission of light energy.

32	Optical grating structure:
	This subclass is indented under subclass 29. Process for making a semiconductor device wherein the additional optical element is a periodic latticework or screen composed of lines producing a series of spectra by the dispersion of the radiation emitted from the device.

[List of Patents for class 438 subclass 33]

Substrate dicing:

This subclass is indented under subclass 22. Process having a step of dividing the semiconductor substrate into plural separate bodies.

(1) Note. The dicing may be done by any manner, such as abrading, sawing, etching, cleavage, or a combination thereof.

SEE OR SEARCH CLASS:

83,	Cutting, for generic processes of cutting a substrate into discrete individual units.
225,	Severing by Tearing or Breaking, subclasses 1+ for methods.
451,	Abrading, for a process of dicing by abrading.

[List of Patents for class 438 subclass 34]

Making emissive array:

This subclass is indented under subclass 22. Process for making a collection or grouping of multiple devices emissive of nonelectrical signal in a single semiconductor substrate.

SEE OR SEARCH THIS CLASS, SUBCLASS:

28,	for a process of packaging (e.g., with mounting, encapsulating, etc.) plural emissive devices into a coherent monolith.

35	Multiple wavelength emissive:
	This subclass is indented under subclass 34. Process wherein the array is emissive of plural electromagnetic wavelengths.

36	Ordered or disordered:
	This subclass is indented under subclass 22. Process for making a semiconductor device wherein a compound semiconductor region is ordered or disordered.

37	Graded composition:
	This subclass is indented under subclass 22. Process wherein the chemical composition of a semiconductor region of the substrate varies with location within the semiconductive region.

38	Passivating of surface:
	This subclass is indented under subclass 22. Process having a step of making the surface of the semiconductor substrate less chemically or optically active.

39	Mesa formation:
	This subclass is indented under subclass 22. Process having a step of removing material from the semiconductor substrate to form a raised feature relative to the surrounding regions of the substrate.

40	Tapered etching:
	This subclass is indented under subclass 39. Process wherein the material removal step is by etching the substrate to form a mesa with nonparallel sides.

41	With epitaxial deposition of semiconductor adjacent mesa:
	This subclass is indented under subclass 39. Process including a step of epitaxial growth of semiconductor material on the portion of the substrate adjacent the mesa.

42	Groove formation:
	This subclass is indented under subclass 22. Process having a step of removing material from the semiconductor substrate to form a recessed feature (e.g., trench, notch, etc.) relative to the surrounding regions of the substrate.

43	Tapered etching:
	This subclass is indented under subclass 42. Process wherein the material removal step is by etching the substrate to form a groove with nonparallel sides.

44	With epitaxial deposition of semiconductor in groove:
	This subclass is indented under subclass 42. Process including a step of epitaxial growth of semiconductor material in the groove.

45	Dopant introduction into semiconductor region:
	This subclass is indented under subclass 22. Process having a step of introducing a dopant into a semiconductive region of the substrate.

46	Compound semiconductor:
	This subclass is indented under subclass 22. Process for making a device emissive of electromagnetic radiation having a compound semiconductor.

47	Heterojunction:
	This subclass is indented under subclass 46. Process for making a device emissive of electromagnetic radiation having a interface between two dissimilar semiconductor materials, at least one of which is a compound semiconductor, to constitute a junction.

[List of Patents for class 438 subclass 48]

MAKING DEVICE OR CIRCUIT RESPONSIVE TO NONELECTRICAL SIGNAL:

This subclass is indented under the class definition. Process for making a semiconductor electrical device or circuit which is responsive to a nonelectrical input or stimuli during operation.

(1) Note. The nonelectrical signal serving as input stimulus of the device or circuit may be described as an information carrying wave.

SEE OR SEARCH CLASS:

136,	Batteries: Thermoelectric and Photoelectric, for active solid-state device structures with a specified usage of generating electricity, especially subclasses 200+ for batteries which generate electricity under the action of heat and subclasses 243+ for batteries which generate electricity under the action of light; some of these batteries utilize potential barrier layers.
250,	Radiant Energy, subclass 338.4 for infrared responsive semiconductor devices for signaling, subclasses 370.01 through 370.15 for invisible radiant energy responsive semiconductor devices, subclasses 552 through 553 for photocell circuits and apparatus involving solid-state light sources, and subclasses 208.1 through 208.6 for plural photosensitive elements, including arrays.
257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclasses 53 through 56, 108, 414, and 467 through 470 for such devices used as temperature responsive devices; subclasses 108, 414, and 421 through 427 for devices responsive to an external magnetic field; subclasses 10, 11, 21, 53 through 56, 72, 113 through 118, 184 through 189, 225 through 234, 257, 258, 290 through 294, 414, and 431 through 466 for light responsive active semiconductor devices.
338,	Electrical Resistors, especially subclass 2 for electrical resistors of the strain gage type and subclass 22 for semiconductor thermistors.
427,	Coating Processes, subclasses 74+ for coating processes which result in a photoelectric or photovoltaic product (e.g., photocathode) which is responsive to visible, infrared, or ultraviolet illumination by (a) emitting electrons, (b) generating an electromotive force, or (c) varying electrical conductivity.

[List of Patents for class 438 subclass 49]

Chemically responsive:

This subclass is indented under subclass 48. Process for making a semiconductor device responsive to a chemical reaction or the presence of a particular chemical or concentration thereof (e.g., pH level, etc.) in close proximity to the device.

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 225 , 253, and 414+ for an active solid-state device responsive to a nonelectrical signal.

[List of Patents for class 438 subclass 50]

Physical stress responsive:

This subclass is indented under subclass 48. Process for making a semiconductor device or circuit responsive to physical deformation (e.g., pressure, strain, etc.).

(1) Note. Processes for making semiconductor electrical device based surface acoustic wave devices, accelerometers, and strain gages are proper for this subclass.

SEE OR SEARCH CLASS:

73,	Measuring and Testing, particularly subclass 777 for a semiconductor-type stress/strain sensor, subclass 514.16 for a semiconductor-type accelerometer, and subclass 754 for semiconductor-type fluid pressure sensors.
257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclasses 415+ for a solid-state active device responsive to physical deformation.
333,	Wave Transmission Lines and Networks, subclasses 193+ for electromechanical filter using surface acoustic waves.
338,	Electrical Resistors, subclass 2 for electrical resistors of the strain gage type.

[List of Patents for class 438 subclass 51]

Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:

This subclass is indented under subclass 50. Process including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:

106,	for process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device.

[List of Patents for class 438 subclass 52]

Having cantilever element:

This subclass is indented under subclass 50. Process for making a physical stress responsive device or circuit which has a projecting beam or horizontal member supported at only one end.

SEE OR SEARCH CLASS:

216,	Etching a Substrate: Processes, subclass 2 for a process of making a cantilever mechanical structure using semiconductive material wherein no electrical function is attributable to the cantilever element produced.

[List of Patents for class 438 subclass 53]

Having diaphragm element:

This subclass is indented under subclass 50. Process for making a physical stress responsive device or circuit which has a thin deflectable membrane.

SEE OR SEARCH CLASS:

216,	Etching a Substrate: Processes, subclass 2 for a process of making a diaphragm mechanical structure using semiconductive material wherein no electrical function is attributable to the structure produced.

[List of Patents for class 438 subclass 54]

Thermally responsive:

This subclass is indented under subclass 48. Process for making a device or circuit responsive to the temperature proximate the device.

(1) Note. Processes of making devices which vary in electrical properties at various temperatures of operation are not deemed to be responsive to thermal stimuli for the purposes of this subclass.

SEE OR SEARCH CLASS:

136,	Batteries: Thermoelectric and Photoelectric, subclass 200 for a process of using a thermoelectric device for generating electrical current.
257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclasses 108 , 225, 252, and 467 through 470 for a device responsive to temperature.

[List of Patents for class 438 subclass 55]

Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:

This subclass is indented under subclass 54. Process provided including (a) multiple operations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multiple operations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:

106,	for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device.

[List of Patents for class 438 subclass 56]

Responsive to corpuscular radiation (e.g., nuclear particle detector, etc.):

This subclass is indented under subclass 48. Process for making a device or circuit responsive to atomic or subatomic discrete particles (e.g., alpha, neutron, fission fragment or fissionable isotope).

SEE OR SEARCH CLASS:

250,

Radiant Energy, subclass 371 for invisible radiant energy responsive methods using semiconductor devices. Also see subclasses 370.01+ for invisible radiant energy responsive electric signaling means of the semiconductor type, particularly subclass 370.02 for an alpha particle detection system, subclass 370.03 for a fission fragmentor fissionable isotope detection system, and subclass 370.05 for a neutron detection system.

[List of Patents for class 438 subclass 57]

Responsive to electromagnetic radiation:

This subclass is indented under subclass 48. Process for making a device or circuit responsive to ultraviolet, visible, or infrared light, x-rays, or gamma rays.

(1) Note. Processes of making devices in which (a) stored electrical charges are erased by exposure to electromagnetic radiation or (b) the device is switched from a nonconducting state to a conducting state or vice versa (e.g., optical turn-on type), are not considered to be responsive to a nonelectrical signal for placement in this and its indented subclasses.

SEE OR SEARCH THIS CLASS, SUBCLASS:

257,	for a process of manufacturing a field effect transistor which has a floating gate structure capable of having electrical charge stored therein erased upon the application of electromagnetic radiation.

SEE OR SEARCH CLASS:

427,	Coating Processes, subclasses 74+ for a process of coating with a photoelectric material to produce an electrical product.
430,	Radiation Imagery Chemistry: Process, Composition, or Product Thereof, subclasses 31+ for an electric or magnetic imagery process employing a photoconductive semiconductive component.

[List of Patents for class 438 subclass 58]

Gettering of substrate:

This subclass is indented under subclass 57. Process having a step of gettering the semiconductor substrate.

SEE OR SEARCH THIS CLASS, SUBCLASS:

471,	for a process of gettering a semiconductor substrate per se.

59	Having diverse electrical device:
	This subclass is indented under subclass 57. Process for making an electrical device responsive to electromagnetic radiation in combination with an additional electrical device which is not responsive to electromagnetic radiation.

[List of Patents for class 438 subclass 60]

Charge transfer device (e.g., CCD, etc.):

This subclass is indented under subclass 59. Process for making a charge transfer device having combined therewith another electrical device or element, either of which being responsive to electromagnetic radiation.

(1) Note. A charge transfer device is a structure in which storage sites for packets of electrical charge are induced at or below the semiconductor surface by an electric field applied by serially arranged gate electrodes formed thereupon and wherein carrier potential energy per unit charge minima are established at a given storage site and such minima are transferred in a serial manner via an active channel region to one or more adjacent storage sites.

61	Continuous processing:
	This subclass is indented under subclass 57. Process for making a semiconductor device responsive to electromagnetic radiation wherein a series of processing steps are performed in a uninterrupted manner.

[List of Patents for class 438 subclass 62]

Using running length substrate:

This subclass is indented under subclass 61. Process whereby the continuous processing is affected using an elongate substrate of indeterminate length having a semiconductive layer thereon.

SEE OR SEARCH THIS CLASS, SUBCLASS:

484,	for a process of depositing amorphous active semiconductor onto a substrate of indeterminate length.
490,	for a process of depositing polycrystalline active semiconductor onto a substrate of indeterminate length.

[List of Patents for class 438 subclass 63]

Particulate semiconductor component:

This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation wherein the substrate contains particulate semiconductive material.

(1) Note. "Particulate" is defined as a mass of discrete units of matter so small (generally of largest dimension <<1000 microns) that they are not ordinarily handled as individual units, and whose shape and length-to-diameter ratio are such that in the dry state the particles will not hold together as a coherent article without the application of pressure or heat.

SEE OR SEARCH CLASS:

136,	Batteries: Thermoelectric or Photoelectric, subclass 250 for a photoelectric device having a particulate or spherical semiconductor component.

[List of Patents for class 438 subclass 64]

Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor:

This subclass is indented under subclass 57. Process provided including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

(1) Note. The term packaging connotes the integration/assembly of the semiconductive substrate/chip/die with a preformed housing, capsule, or support.

SEE OR SEARCH THIS CLASS, SUBCLASS:

106,	for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device.

[List of Patents for class 438 subclass 65]

Having additional optical element (e.g., optical fiber, etc.):

This subclass is indented under subclass 64. Process for packaging a semiconductor device responsive to electromagnetic radiation wherein the device has combined therewith one or more optical elements to transmit or modify electromagnetic radiation incident upon the semiconductor device and the optical element is fixed or attached to the device or the housing or support thereof.

SEE OR SEARCH CLASS:

65,	Glass Manufacturing, especially subclass 406 for processes which involve assembling at least two individually distinct optical fibers, waveguides, or preforms directly to each other (e.g., coupling, etc.).
323,	Electricity: Power Supply or Regulation Systems, subclass 902 for optical coupling to a semiconductor.

[List of Patents for class 438 subclass 66]

Plural responsive devices (e.g., array, etc.):

This subclass is indented under subclass 64. Process for packaging a multiplicity of devices or elements responsive to electromagnetic radiation into a coherent monolith.

(1) Note. The plural responsive devices may be combined via a hybrid construction or secured onto a common support.

67	Assembly of plural semiconductor substrates:
	This subclass is indented under subclass 66. Process having a step of joining multiple semiconductor substrates into a coherent monolith in which plural devices responsive to electromagnetic radiation are formed.

[List of Patents for class 438 subclass 68]

Substrate dicing:

This subclass is indented under subclass 57. Process having a step of dividing the semiconductor substrate into multiple separate bodies.

(1) Note. The dicing may be done by any manner, such as abrading, sawing, etching, cleavage, or a combination thereof.

SEE OR SEARCH CLASS:

83,	Cutting, for generic processes of cutting a substrate into discrete individual units.
225,	Severing by Tearing or Breaking, subclasses 1+ for methods.
451,	Abrading, for a process of dicing by abrading.

69	Including integrally formed optical element (e.g., reflective layer, luminescent layer, etc.):
	This subclass is indented under subclass 57. Process for making a semiconductor device responsive to electromagnetic radiation wherein the device has combined therewith one or more integrally formed optical elements to transmit or modify electromagnetic radiation incident upon the semiconductor device

70	Color filter:
	This subclass is indented under subclass 69. Process for making a semiconductor device responsive to electromagnetic radiation having combined therewith structural means functioning as a color filter element.

71	Specific surface topography (e.g., textured surface, etc.):
	This subclass is indented under subclass 69. Process having a surface of specified topography incorporated into an electromagnetic sensitive device or utilized during manufacture thereof.

72	Having reflective or antireflective component:
	This subclass is indented under subclass 69. Process for making a semiconductor device responsive to electromagnetic radiation having a component which has reflective or antireflective properties with respect to electromagnetic radiation incident thereupon.

[List of Patents for class 438 subclass 73]

Making electromagnetic responsive array:

This subclass is indented under subclass 57. Process for making a collection or grouping of electromagnetically responsive devices on a single, coherent, semiconductor substrate.

(1) Note. Individual detectors of the array may alternatively be referred to as elements, pixels, or cells.

74	Vertically arranged (e.g., tandem, stacked, etc.):
	This subclass is indented under subclass 73. Process wherein the array of electromagnetic responsive devices is configured with one responsive device residing at a position over another such device.

75	Charge transfer device (e.g., CCD, etc.):
	This subclass is indented under subclass 73. Process for making a structure in which storage sites for packets of electrical charge are induced at or below the semiconductor surface by an electric field applied by serially arranged gate electrodes formed thereupon and wherein carrier potential energy per unit charge minima are established at a given storage site and such minima are transferred in a serial manner via an active channel region to one or more adjacent storage sites.

76	Majority signal carrier (e.g., buried or bulk channel, peristaltic, etc.):
	This subclass is indented under subclass 75. Process for making a charge transfer device wherein the transfer of such charge minima is by majority carriers of the semiconductive material (i.e., by electrons in n-type material or by holes in p-type semiconductive material) and such transfer is in response to electromagnetic radiation incident to the device.

77	Compound semiconductor:
	This subclass is indented under subclass 75. Process for making a charge transfer device in which the storage sites are composed of a compound semiconductor material.

[List of Patents for class 438 subclass 78]

Having structure to improve output signal (e.g., exposure control structure, etc.):

This subclass is indented under subclass 75. Process for making a charge transfer device which contains structural means to improve the electrical signal it generates in response to the electromagnetic radiation.

(1) Note. The structural means to improve the output signal may serve to control the amount of light incident on the device which is transferred as output signal charge.

[List of Patents for class 438 subclass 79]

Having blooming suppression structure (e.g., antiblooming drain, etc.):

This subclass is indented under subclass 78. Process for making a charge transfer device wherein the structural means to improve the output signal prevents spill over of a large amount of signal charge generated at a storage site which receives an electromagnetic radiation responsive input signal of very high intensity to adjacent storage sites.

(1) Note. The antiblooming suppression structure may include a drain structure for removing charge from storage sites.

(2) Note. The antiblooming drain structure may be located in the device beneath storage sites rather than on its surface.

80	Lateral series connected array:
	This subclass is indented under subclass 73. Process wherein the array of electromagnetically responsive devices is laterally arranged and serially electrically connected.

[List of Patents for class 438 subclass 81]

Specified shape junction barrier (e.g., V-grooved junction, etc.):

This subclass is indented under subclass 80. Process wherein the junction barrier interface (i.e., between adjoining semiconductor regions of opposite conductivity type) has a specified geometrical configuration.

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 465 for a light-responsive active solid-state device having a barrier junction of specified geometrical configuration and subclasses 653+ for an active solid-state device having a specified shape PN junction.

[List of Patents for class 438 subclass 82]

Having organic semiconductor component:

This subclass is indented under subclass 57. Process wherein the semiconductor substrate contains a semiconductive compound in which the molecule is characterized by two or more carbon atoms bonded together, one atom of carbon bonded to at least one atom of hydrogen or halogen (i.e., chlorine, fluorine, bromine, iodine) or one atom of carbon bonded to at least one atom of nitrogen by a single or double bond.

(1) Note. Exceptions to this rule include HCN, CN-CN, HNCO, HNCS, cyanogen halides, cyanamide, fulminic acid, and metal carbides. These are not regarded as organic materials. Also, note that graphite and diamond are not regarded as organic semiconductors, since they are not compounds; silicon carbide is not regarded as organic.

83	Forming point contact:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation including forming a potential barrier between an electrode of small contacting or cross-sectional area in touching relationship with a substantially larger area of the semiconductor substrate, thus forming a potential barrier junction at the single point therebetween.

84	Having selenium or tellurium elemental semiconductor component:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation utilizing a semiconductor substrate containing semiconductive selenium or tellurium in elemental form (i.e., notin a compound) or an alloy (i.e., mixture) thereof.

85	Having metal oxide or copper sulfide compound semiconductive component:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation utilizing a semiconductor substrate containing a metal oxide or copper sulfide compound semiconductor.

86	And cadmium sulfide compound semiconductive component:
	This subclass is indented under subclass 85. Process wherein the semiconductor substrate containing a metal oxide or copper sulfide compound semiconductor additionally contains a cadmium sulfide compound semiconductor.

87	Graded composition:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation wherein the chemical composition of a semiconductor region of the substrate varies with location within the semiconductive region.

88	Direct application of electric current:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation having a step of directly applying electrical current to the semiconductor substrate.

89	Fusion or solidification of semiconductor region:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation having a step of fusing or solidifying a semiconductive region of the substrate.

[List of Patents for class 438 subclass 90]

Including storage of electrical charge in substrate:

This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation having a step of storing electrical charge in a region of the semiconductor substrate.

SEE OR SEARCH THIS CLASS, SUBCLASS:

19,	for a process of making a semiconductor electrical device having formed therewith an integral battery or power source.

[List of Patents for class 438 subclass 91]

Avalanche diode:

This subclass is indented under subclass 57. Process for making a device which is configured to operate in a manner in which an external voltage applied in the reverse-conducting direction of the device junction with sufficient magnitude causes the potential barrier at the junction to breakdown due to electrons or holes gaining sufficient speed to dislodge valence electrons and thus create more hole-electron current carriers resulting in a sudden change from high dynamic electrical resistance to very low dynamic resistance.

(1) Note. The terms Zener diode and Zener breakdown voltage are used rather loosely in that the breakdown mechanism above about 6 volts is thought to be due to avalanching and that below about 6 volts is thought to be due essentially to tunnelling.

SEE OR SEARCH THIS CLASS, SUBCLASS:

380,	for a process of making an avalanche diode which is not responsive to electromagnetic radiation.

SEE OR SEARCH CLASS:

257,

Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 199 for an avalanche diode in a noncharge transfer device having a heterojunction, subclass 438 for a light-responsive avalanche junction device, subclass 481 for an avalanche diode having a Schottky barrier, subclass 551 for an avalanche diode used as a voltage reference element combined with pn junction isolation means in an integrated circuit, and subclasses 603+ for avalanche diodes in general.

92	Schottky barrier junction:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation having a Schottky rectifying junction.

93	Compound semiconductor:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation having a compound semiconductor.

94	Heterojunction:
	This subclass is indented under subclass 93. Process for making a device responsive to electromagnetic radiation having a interface between two dissimilar semiconductor materials, at least one of which is a compound semiconductor, to constitute a junction.

95	Chalcogenide (i.e., oxygen (O), sulfur (S), selenium (Se), tellurium (Te)) containing:
	This subclass is indented under subclass 93. Process wherein the compound semiconductor contains an element from the group of oxygen, sulfur, selenium, and tellurium.

96	Amorphous semiconductor:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation having an amorphous semiconductor component.

97	Polycrystalline semiconductor:
	This subclass is indented under subclass 57. Process for making a device responsive to electromagnetic radiation having a polycrystalline semiconductor component.

[List of Patents for class 438 subclass 98]

Contact formation (i.e., metallization):

This subclass is indented under subclass 57. Process for making a semiconductor device responsive to electromagnetic radiation having a step of coating the device with electrically conductive material forming an electrical connect or conductor thereto.

(1) Note. The electrically conductive material may additionally be transparent to electromagnetic radiation.

[List of Patents for class 438 subclass 99]

HAVING ORGANIC SEMICONDUCTIVE COMPONENT:

This subclass is indented under the class definition. Process for making a semiconductor electrical device wherein the semiconductor substrate contains a semiconductive compound in which the molecule is characterized by two or more carbon atoms bonded together, one atom of carbon bonded to at least one atom of hydrogen or halogen (i.e., chlorine, fluorine, bromine, iodine) or one atom of carbon bonded to at least one atom of nitrogen by a single or double bond.

SEE OR SEARCH THIS CLASS, SUBCLASS:

82,	for a process of making a device having an organic semiconductive component which is responsive to electromagnetic radiation.

SEE OR SEARCH CLASS:

29,	Metal Working, subclass 25.03 for a process of making an electrolytic capacitor using a solid organic semiconductor.
136,	Batteries: Thermoelectric and Photoelectric, subclass 263 for photoelectric cells containing organic active material.
252,	Compositions, subclass 62.3 for organic barrier layer device compositions.
257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 40 for an active solid-state device having an organic semiconductor.

[List of Patents for class 438 subclass 100]

100

MAKING POINT CONTACT DEVICE:

This subclass is indented under the class definition. Process for making a semiconductor electrical device having a potential barrier between an electrode of small contacting or cross-sectional area in touching relationship with a substantially larger area of the semiconductor substrate, thus forming a potential barrier junction at the single point of contact therebetween.

SEE OR SEARCH THIS CLASS, SUBCLASS:

83,	for a process of making a point contact device which is responsive to electromagnetic radiation.

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 41 for a point contact device.

101	Direct application of electrical current:
	This subclass is indented under subclass 100. Process including a step of directly applying electrical current to the point contact semiconductor electrical device.

[List of Patents for class 438 subclass 102]

102

HAVING SELENIUM OR TELLURIUM ELEMENTAL SEMICONDUCTOR COMPONENT:

This subclass is indented under the class definition. Process for making a semiconductor electrical device wherein the semiconductor substrate is comprised of semiconductive selenium or tellurium in elemental form (i.e., not in a compound) or an alloy (i.e., mixture) thereof.

SEE OR SEARCH THIS CLASS, SUBCLASS:

84,	for a process of making a device responsive to electromagnetic radiation comprised of semiconductive selenium or tellurium in elemental form or an alloy thereof.

SEE OR SEARCH CLASS:

252,	Compositions, subclass 62.3 for barrier layer device compositions containing free elemental selenium or tellurium.
257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 42 for a device having elemental selenium or tellurium semiconductor.
420,	Alloys or Metallic Compositions, subclass 579 for selenium or tellurium base alloy containing metal.

103	Direct application of electrical current:
	This subclass is indented under subclass 102. Process having a step of directly applying electrical current to the selenium or tellurium elemental semiconductor component substrate.

[List of Patents for class 438 subclass 104]

104

HAVING METAL OXIDE OR COPPER SULFIDE COMPOUND SEMICONDUCTOR COMPONENT:

This subclass is indented under the class definition. Process for making a semiconductor electrical device wherein the semiconductor substrate contains a metal oxide or copper sulfide compound semiconductor.

SEE OR SEARCH THIS CLASS, SUBCLASS:

85,	for a process of making a device responsive to electromagnetic radiation having a metal oxide or copper sulfide compound semiconductor component.

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 43 for a semiconductor solid-state device having a metal oxide or copper sulfide compound semiconductor component.
264,	Plastic and Nonmetallic Article Shaping or Treating: Processes, subclass 61 for methods of vitrifying or sintering an inorganic preform to make a discrete passive device (e.g., multilayer ceramic capacitor, etc.).

[List of Patents for class 438 subclass 105]

105

HAVING DIAMOND SEMICONDUCTOR COMPONENT:

This subclass is indented under the class definition. Process for making a semiconductor electrical device wherein the semiconductor substrate contains a diamond semiconductor component.

(1) Note. The utilization of a diamond component for other than its semiconductor properties (e.g., as a thermal heat sink) is not proper for this subclass.

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), subclass 77 , for a solid-state device having a diamond semiconductor component.

[List of Patents for class 438 subclass 106]

106

PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR:

This subclass is indented under the class definition. Process provided including (a) multipleoperations having a step of permanently attaching or securing a semiconductive substrate to a terminal, elongated conductor, or support (e.g., a mounting, housing, lead frame, discrete heat sink, etc.), (b) multipleoperations having a step of shaping flowable plastic or flowable insulative material about a semiconductive substrate, or (c) a step of treating an already mounted or packaged semiconductor substrate (e.g., coating of flowable plastic or flowable insulative material about a semiconductor substrate by dipping, etc.).

(1) Note. Packaging is a semiconductor art manufacturing term for integration, assembly, or surrounding of a semiconductor substrate (e.g., chip, die, etc.) with a permanent encasement, housing, capsule, or support. This is distinguished from package making found in Class 53 which is directed to preparing a manufactured product for passage through the channels of trade in a safe, convenient, and attractive condition, usually wrapped in a cover or in a container which is intended to be removed when the manufactured product is used.

(2) Note. See References to Other Classes in the class definition, for a listing of various related classes providing for unit or combined operations.

(3) Note. See References to Other Classes in the class definition, for a listing of various related classes providing for electrical connectors, electrical device housing or packaging, etc.

SEE OR SEARCH THIS CLASS, SUBCLASS:

26,	for a process of packaging (e.g., with mounting, encapsulating, etc.)or treating a packaged semiconductor device or circuit emissive of a nonelectrical signal.
51,	for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device responsive to physical stress.
55,	for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a thermally responsive semiconductor electrical device.
64,	for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a semiconductor device or circuit responsive to electromagnetic radiation.
100,	for a process of manufacturing a point-contact-type semiconductor device.
616,	for a process of transcribing bump electrodes which substantially do not retain their contour following transfer from a carrier substrate (e.g., template, etc.) to a semiconductor substrate.

SEE OR SEARCH CLASS:

29,	Metal Working, especially subclass 827 for lead frame or beam lead device manufacture, subclasses 829+ for the assembly of an electrical component to an insulative base having a conductive path applied thereto, or formed thereon or therein (e.g., a printed circuit board), subclasses 854+ for the assembly of an electrical component directly to terminal or elongated conductor, and subclasses 729+ for an electrical device manufacturing apparatus.
53,	Package Making, subclasses 396+ for methods of encompassing, encasing, or completely surrounding goods or materials with a cover made from sheet material stock, and for methods of assembling or securing a separate closure (hood, cap, capsule, crown, seal, etc.) to the aperture of a preformed receptacle so as to complete the encasement of contents.
65,	Glass Manufacturing, especially subclasses 36+ for a process of fusion bonding of glass to a formed part, and subclass 155 for electronic device making means involving fusion bonding.
148,	Metal Treatment, for a process of treating metal to modify or maintain the internal physical structure (i.e., microstructure) or chemical properties of metal.
156,	Adhesive Bonding and Miscellaneous Chemical Manufacture, subclasses 60+ for a single step process of adhesively bonding and for certain multistep processes having a step of adhesively bonding a nominal semiconductive chip or wafer.
216,	Etching a Substrate: Processes, especially subclasses 13+ for processes of manufacturing a printed circuit board or thick film circuit board involving an etching step.
219,	Electric Heating, subclasses 78.01+ for process and apparatus for bonding by electrical current and pressure.
228,	Metal Fusion Bonding, appropriate subclasses, for a process of fusion bonding and additional operations which are considered to be ancillary to the bonding (preheating, positioning, pretinning, etc.) of a semiconductive substrate, especially subclass 123.1 and 179.1+.
264,	Plastic and Nonmetallic Article Shaping or Treating: Processes, for a process (and steps perfecting same) of shaping plastic or nonmetallic material and uniting it to a preform (e.g., encapsulating), said preform being a semiconductive substrate.
324,	Electricity: Measuring and Testing, for a process of temporarily affixing a semiconductor substrate to a support during the electrical testing thereof.
427,	Coating Processes, subclasses 96.1 through 99.5for a process of coating a nonsemiconductive substrate to produce an integrated or printed circuit or circuit board (e.g., coating an insulative substrate to form a printed or thick film circuit board, etc.).

[List of Patents for class 438 subclass 107]

107

Assembly of plural semiconductive substrates each possessing electrical device:

This subclass is indented under subclass 106. Process wherein plural semiconductive substrates are combined into a hybrid construction or secured onto a common support.

SEE OR SEARCH THIS CLASS, SUBCLASS:

455,	for a nonpackaging process of joining or bonding plural semiconductive substrates wherein none of the semiconductive substrates are intended to function as a terminal, elongated conductor, or support.

108	Flip-chip-type assembly:
	This subclass is indented under subclass 107. Process wherein a semiconductive substrate which has electric contacts on the top side thereof is flipped to juxtapose the contacts in face-to-face orientation with a substrate which has matching electrical contacts prior to bonding.

109	Stacked array (e.g., rectifier, etc.):
	This subclass is indented under subclass 107. Process for making a semiconductor device wherein a multiplicity of semiconductive substrates are juxtaposed in face-to-face orientation.

110	Making plural separate devices:
	This subclass is indented under subclass 106. Process for making a semiconductor device wherein a multiplicity of separate semiconductive devices are obtained.

[List of Patents for class 438 subclass 111]

111

Using strip lead frame:

This subclass is indented under subclass 110. Process for making plural separate semiconductor devices utilizing a plurality of support structures or positions arranged on an elongated continuum prior to separation.

(1) Note. The continuum may either be the material of the lead frame (e.g., metal strip) or the lead frame may be mounted serially on another continuum (e.g., plastic strip).

112	And encapsulating:
	This subclass is indented under subclass 111. Process including a step of surrounding the semiconductor substrate with an electrically insulating material which forms a sealed encasement therefor.

[List of Patents for class 438 subclass 113]

113

Substrate dicing:

This subclass is indented under subclass 110. Process wherein a semiconductive substrate is divided into discrete individual units.

(1) Note. The dicing may be done by any manner, such as abrading, sawing, etching, cleavage, or a combination thereof.

SEE OR SEARCH THIS CLASS, SUBCLASS:

460,	for a process under the class definition of dicing a semiconductor substrate into multiple separate bodies.

SEE OR SEARCH CLASS:

83,	Cutting, for generic processes of cutting a substrate into discrete individual units.
225,	Severing by Tearing or Breaking, subclasses 1+ for methods.
451,	Abrading, for a process of dicing by abrading.

114	Utilizing a coating to perfect the dicing:
	This subclass is indented under subclass 113. Process including a step of coating the semiconductive substrate to enhance the dicing operation.

115	Including contaminant removal or mitigation:
	This subclass is indented under subclass 106. Process including the step of removing undesirable material through the use of a getter, desiccant, etc.

[List of Patents for class 438 subclass 116]

116

Having light transmissive window:

This subclass is indented under subclass 106. Process wherein the housing contains light transmissive means allowing light to reach the enclosed semiconductive device.

SEE OR SEARCH THIS CLASS, SUBCLASS:

64,	for a process of packaging (e.g., with mounting, encapsulating, etc.) or treating a packaged semiconductor device responsive to electromagnetic radiation.

117	Incorporating resilient component (e.g., spring, etc.):
	This subclass is indented under subclass 106. Process for packaging a semiconductor substrate wherein the resulting structure includes an elastically compressible component.

[List of Patents for class 438 subclass 118]

118

Including adhesive bonding step:

This subclass is indented under subclass 106. Process for packaging a semiconductor substrate including a step of joining the semiconductor substrate to a another body by nonmetallic bonding.

(1) Note. See Lines With Other Classes, "Packaging (e.g., With Mounting, Encapsulating, etc.) or Treatment of Packaged Semiconductor" above. Also see the search notes below.

SEE OR SEARCH CLASS:

156,	Adhesive Bonding and Miscellaneous Chemical Manufacture, subclasses 60+ for a step of surface bonding or assembly therefor, and the Class 156 definition for special lines to Class 29, Metal Working.

[List of Patents for class 438 subclass 119]

119

Electrically conductive adhesive:

This subclass is indented under subclass 118. Process wherein the nonmetallic bonding material is electrically conductive.

(1) Note. The nonmetallic bonding material may possess particulate metal dispersed in the nonmetallic adhesive binder to render the composition electrically conductive.

120	With vibration step:
	This subclass is indented under subclass 106. Process for packaging a semiconductor substrate including a step of applying vibratory energy.

121	Metallic housing or support:
	This subclass is indented under subclass 106. Process for mounting, packaging, or encapsulating a semiconductor device wherein a semiconductive substrate is supported or enclosed by joining the substrate to a metallic body.

[List of Patents for class 438 subclass 122]

122

Possessing thermal dissipation structure (i.e., heat sink):

This subclass is indented under subclass 121. Process wherein the metallic body joined to the semiconductor substrate possesses structure for the dissipation of thermal energy generated during operation of the electrical device.

SEE OR SEARCH THIS CLASS, SUBCLASS:

584,	for a process of coating a semiconductor substrate with a thermally conductive material (e.g., plated heat sink, etc.)

123	Lead frame:
	This subclass is indented under subclass 121. Process wherein the metallic body joined to the semiconductor device is in the form of a metallic support with electrically conductive leads depending therefrom.

124	And encapsulating:
	This subclass is indented under subclass 121. Process including a step of surrounding the semiconductor substrate or the metallic housing or support with an electrically insulating material which forms a sealed encasement therefor.

[List of Patents for class 438 subclass 125]

125

Insulative housing or support:

This subclass is indented under subclass 106. Process for making a structure wherein the semiconductive device is supported or enclosed by preformed insulative body.

(1) Note. An encapsulant, per se, is not considered to be a supporting structure proper for this and indented subclasses.

126	And encapsulating:
	This subclass is indented under subclass 125. Process including a step of surrounding the semiconductor substrate or insulative housing or support with an electrically insulating material which forms a sealed encasement therefor.

[List of Patents for class 438 subclass 127]

127

Encapsulating:

This subclass is indented under subclass 106. Process including a step of surrounding the semiconductor substrate with an electrically insulating material which forms a sealed encasement therefor.

SEE OR SEARCH CLASS:

65,	Glass Manufacturing, for a per se process of shaping glass material about an electrical device to encapsulate same.
264,	Plastic and Nonmetallic Article Shaping or Treating: Processes, especially subclasses 272.11+ for per se electrical component encapsulating by molding of insulative material about the electrical component.

[List of Patents for class 438 subclass 128]

128

MAKING DEVICE ARRAY AND SELECTIVELY INTERCONNECTING:

This subclass is indented under the class definition. Process for forming an array of active devices on a semiconductor substrate and electrically interconnecting the devices into a designated circuit arrangement.

(1) Note. The processes found in this and its indented subclasses result in circuits which are alter-natively referred to as personalized, customized, or application specific.

(2) Note. This and its indented subclasses do not take processes of producing a shorted or shunted structure as an integral part of a single device.

SEE OR SEARCH THIS CLASS, SUBCLASS:

6,	for processes of interconnecting plural devices wherein at least one operation is responsive to a sensed condition.
587,	for process of forming an array of gate electrodes upon a semiconductor substrate.
598+,	for a process of metallizing a semiconductor substrate wherein the electrically conductive metallization contains a portion which is alterable from the conductive to nonconductive condition or vice-versa (e.g., a fuse or antifuse).

SEE OR SEARCH CLASS:

257,	Active Solid-State Devices (e.g., Transistors, Solid-State Diodes), particularly subclasses 202+ for gate arrays.

[List of Patents for class 438 subclass 129]

129

With electrical circuit layout:

This subclass is indented under subclass 128. Process including a step of designing the topological arrangement of arrayed device components or electrical conductors therebetween in combination with making the semiconductor device array.

SEE OR SEARCH CLASS:

369,

Dynamic Information Storage or Retrieval, for processes of storing or retrieving dynamic information, subclasses 99+ for a particular detail of the information handling portion of a system, especially subclasses 100+ for radiation beam modification of or by a storage medium and subclass 126 for electrical modification or sensing of a storage medium (e.g., capacitive, resistive, or electrostatic discharge)

130	Rendering selected devices operable or inoperable:
	This subclass is indented under subclass 128. Process wherein selected devices located on a sem