CPC Definition - Subclass H01L
This place covers:
in general
- discrete and integrated semiconductor devices and
- other electric solid state devices (as far as not provided for in another subclass) and
- details thereof.
This includes the following kind of devices:
- integrated circuit devices, e.g. CMOS integrated devices, DRAM, EPROM or CCD;
- semiconductor devices (e.g. field-effect, bipolar) adapted for rectifying, amplifying, oscillating or switching, e.g. diodes, transistors or thyristors;
- semiconductor devices sensitive to radiation, e.g. photo diodes, photo transistors or solar cells;
- incoherent light emitting diodes, e.g. LED;
- solid state devices using organic materials as the active part or using a combination of organic materials with other materials as the active part, e.g. organic LED or polymer LED;
- electric solid state devices using thermoelectric, superconductive, piezoelectric, electrostrictive, magnetostrictive, galvano-magnetic or bulk negative resistance effects, e.g. thermo couples, Peltier elements, Josephson elements, piezo elements;
- photo-resistors, magnetic field dependent resistors or field effect resistors;
- capacitors having potential barriers or resistors having potential barriers;
- thin-film or thick-film circuits;
- processes and apparatus adapted for the manufacture or treatment of such devices, except where such processes relate to single step processes for which provision exists elsewhere.
Microstructural devices or systems are classified in subclass B81B, and the processes and apparatus specially adapted for the manufacture or treatment thereof are classified in subclass B81C. So, by way of example, microelectro-mechanical devices (MEMS), containing microelectronic and mechanical components, are classified in group B81B 7/02, and their manufacture, treatment or assembling in the relevant groups of B81C. Microstructural devices or systems working purely electrically or electronically, or related processes or apparatus for the manufacture or treatment thereof are, however, not covered by B81B or B81C and are classified in section H, for example in the groups of the current subclass H01L.
Microstructural devices or systems being of other than purely electrical or electronically type, and apparatus or processes for the manufacture or treatment thereof, which are normally classified in the subclasses B81B and B81C, may be also classified in those groups of H01L providing for their structural or functional features, whenever such features are of interest per se.
This place does not cover:
Use of semiconductor devices for measuring | |
Non-adjustable resistors from semiconductor material | |
Magnets, inductors, transformers | |
Capacitors in general | |
Electrolytic devices | |
Batteries, accumulators | |
Waveguides, resonators or lines of the waveguide type | |
Line connectors, current collectors | |
Lasers, stimulated emission devices, e.g. semiconductor laser | |
Electromechanical resonators; impedance networks | |
Loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers | |
Electric light sources in general | |
Printed circuits, hybrid circuits, casings or constructional details of electric apparatus, manufacture of assemblages of electrical components |
Attention is drawn to the following places, which may be of interest for search:
Containers merely intended for transport or storage of wafers except during manufacture or finishing devices thereon | |
Conveying systems for semiconductor wafers except during manufacture or treatment of semiconductor or electric solid state devices or components thereon | |
Micromechanical Devices (MEMS) | |
Processes and apparatus specially adapted for the manufacture or treatment of microstructural devices or systems | |
Coating Material | |
Non-mechanical removal of metallic material from surface | |
Measurement of Mechanical Vibrations or Ultrasonic, Sonic or Infrasonic Waves | |
Measurement of Intensity, velocity, Spectral, Content, Polarization, Phase or Pulse Characteristic of Infrared, Visible or Ultraviolet Light | |
Measuring Electrical or Magnetic Variables | |
Details of scanning-probe apparatus, in general | |
Radio Direction-Finding; Radio Navigation; Determining Distance or Velocity by Use of Radio Waves; Locating or Presence-Detecting by Use of the Reflection or Reradiation of Radio Waves; Analogous Arrangements Using Other Waves | |
Measuring Nuclear or X-Radiation | |
Electro photography | |
Systems for Regulating Electrical or Magnetic Variables | |
Digital Computers | |
Static Stores | |
Conductive and Insulating Materials | |
Electric discharge tubes or discharge lamps | |
Amplifiers | |
Pictorial Communication, e.g. Television |
In this subclass, Indexing Codes are mainly attributed with a view to allow retrieval of documents comprising a combination of technical characteristics, some of them being unimportant per se, and, hence, identified as additional information rather than invention information.
In this subclass, both the process and apparatus for the manufacture or treatment of a device and the device itself are classified, whenever both of these are described sufficiently to be of interest.
In this place, the following terms or expressions are used with the meaning indicated:
assembly of a device | the "assembly" of a device is the building up of the device from its component constructional units and includes the provision of fillings in containers. |
complete device | a "complete device" is a device in its fully assembled state which may or may not require further treatment, e.g. electro-forming, before it is ready for use but which does not require the addition of further structural units. |
component | a "component" is one electric circuit element of a plurality of elements formed in or on a common substrate. |
container | a "container" is an enclosure forming part of the complete device and is essentially a solid construction in which the body of the device is placed, or which is formed around the body without forming an intimate layer thereon. |
device | the term "device" refers to an electric circuit element; where an electric circuit element is one of a plurality of elements formed in or on a common substrate it is referred to as a "component". |
electrodes | "electrodes" are regions in or on the body of the device (other than the solid-state body itself), which exert an influence on the solid-state body electrically, whether or not an external electrical connection is made thereto. An electrode may include several portions and the term includes metallic regions which exert influence on the solid-state body through an insulating region (e.g. capacitive coupling) and inductive coupling arrangements to the body. The dielectric region in a capacitive arrangement is regarded as part of the electrode. In arrangements including several portions only those portions which exert an influence on the solid-state body by virtue of their shape, size or disposition or the material of which they are formed are considered to be part of the electrode. The other portions are considered to be "arrangements for conducting electric current to or from the solid-state body" or "interconnections between solid state components formed in or on a common substrate", i.e. leads. |
encapsulation | an "encapsulation" is an enclosure which consists of one or more layers formed on the body and in intimate contact therewith. |
integrated circuit | an "integrated circuit" is a device where all components, e.g. diodes, resistors, are built up on a common substrate and form the device including interconnections between the components. |
integration process | processes for the manufacture of at least two different components where the process is especially adapted to their integration, e.g. to take advantage of the integration or to reduce their manufacturing cost. Example: in a CMOS process, the same ion implant dopes the p-MOS gate and the n-MOS source and drain. Consequently, a process for the manufacture of a component per se is not considered as an integration process, even though that component will be part of an integrated circuit. |
interconnection | refers to the arrangement of conductive and insulating regions aimed at electrically connecting the respective electrodes of at least two device units, e.g. two transistors. |
parts | the term "parts" includes all structural units which are included in a complete "device". |
solid state body | the expression "solid state body" refers to the body of material within which, or at the surface of which, the physical effects characteristic of the device occur. In thermoelectric devices it includes all materials in the current path. |
wafer | a "wafer" means a slice of semiconductor or crystalline substrate material, which can be modified by impurity diffusion (doping), ion implantation or epitaxy, and whose active surface can be processed into arrays of discrete devices or integrated circuits. |
In patent documents, the following words/expressions are often used with the meaning indicated:
package | container, encapsulation. |
This place covers:
Processes and apparatus that are specially adapted for the manufacturing of semiconductor or solid state devices belonging to the type:
- Integrated circuit devices, e.g. CMOS integrated devices, DRAM, EPROM, CCD;
- Semiconductor devices (e.g. field-effect, bipolar) adapted for rectifying, amplifying, oscillating or switching, e.g. diodes, transistors, thyristors;
This main group includes;
- Manufacture or treatment of the above semiconductor devices or of parts thereof
- Manufacture or treatment of solid state devices other than semiconductor devices, or of parts thereof
- Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
- Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof
Attention is drawn to the following places, which may be of interest for search:
Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in groups H01L 31/00, H01L 33/00, H10K 30/00, H10K 50/00, H10K 59/00, H10K 71/00, H10K 85/00, H10K 99/00, H10N 10/00, H10N 30/00, H10N 35/00, H10N 50/00, H10N 52/00, H10N 60/00H10K 99/00 or of parts thereof, see these groups | H01L 31/00, H01L 33/00, H10K 30/00, H10K 50/00, H10K 59/00, H10K 71/00, H10K 85/00, H10K 99/00, H10N 10/00, H10N 30/00, H10N 35/00, H10N 50/00, H10N 52/00, H10N 60/00H10K 99/00 |
Processes for applying liquids or other fluent materials | |
Liquid cleaning (in general) | |
Machines, Devices, or Processes for Grinding or Polishing | |
Containers, packaging elements or packages specially adapted for particular articles or materials | |
Shaped ceramic Products | |
Polishing compositions | |
Cleaning Compositions | |
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material | |
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating (CVD) | |
Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds,without leaving reaction products of surface material in the coating | |
Etching metallic material by chemical means | |
Processes for the Electrolytic or Electrophoretic Production of Coatings | |
Single Crystal Growth; Epitaxy | |
Testing individual semiconductor devices | |
Preparation of originals for the photomechanical production of textured or patterned surfaces | |
Photolithographic, production of textured or patterned surfaces | |
Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces | |
Discharge tubes with provision for introducing objects or material to be exposed to the discharge (plasma etching; ion implantation) | |
Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components |
Single mono-steps for which a provision exists elsewhere in ECLA need not to be classified in H01L 21/00, except if they are specific to the fabrication of semiconductor devices as defined under H01L 21/00. E.g., apparatuses which are not specific to the fabrication of these devices, e.g. apparatuses for depositing layers, are classified in C23C or C30B.
Direct pre-treatment or direct post-treatment of a specific step is classified under the specific step if no other place exists in H01L 21/00. Example: annealing after layer coating is classified together with the coating. Exception: cleaning, see H01L 21/02041
In H01L 21/00, poly-silicon is generally considered as a conductive material for classification purposes, except for its deposition (H01L 21/02365) where it is considered as semiconducting.
Polishing or chemical-mechanical polishing are not distinguished for classification.
Machines and apparatuses for which a provision exists somewhere else in CPC are not classified In H01L 21/00. For example apparatus for deposition of materials are classified in C23C or C30B.
Machines and apparatuses for which no particular provision exists in CPC are classified in H01L 21/67 and subgroups. See also the notes under H01L 21/67.
Processes mainly consisting of features of the use of the elements of the apparatus and which are necessary to operate said apparatus (like for example rotating the turntable of a polisher, evacuating the chamber of a plasma appraratus etc...) need not to be classified in H01L 21/00.
Subject matter relating to processes and apparatus which are clearly suitable for manufacture or treatment of devices whose bodies comprise elements of the fourth group of the Periodic System (silicon, germanium), and where the material used is not explicitly specified, is classified in the subgroups relating to semiconductors of the fourth group of the Periodic System (silicon, germanium).
For multistep processes, a junction between two regions of the same material but in a different crystalline state, e.g. amorphous silicon or polysilicon emitters on single crystalline silicon, is not considered as a heterojunction.
In this place, the following terms or expressions are used with the meaning indicated:
Dry Process | refers to processes wherein only gases or vapours are provided on the surface of a substrate, e.g. a wafer, irrespective of the physical state of the reaction products, gaseous, liquid or solid. |
Wet Process | refers to processes wherein only liquids are provided at the surface of a wafer, including the condensation on the surface of a wafer of gaseous components. |
Pre-, post-treatment | direct, for example in situ, treatment, preceding or following a main technological step, aimed at improving said main technological step or its result. Not considered as a technological step per se. Examples: - annealing or crystallisation after deposition of insulating layers, - cleaning before or after a technological step, - modifying an insulating layer just after its formation, e.g. implantation after deposition |
After treatment | Subsequent main technological step. Examples: - patterning or polishing of a layer after deposition- modifying an insulating layer after a step which is not the formation of the insulating layer |
In patent documents, the following abbreviations are often used:
CVD | Chemical vapour deposition |
PECVD | Plasma enhanced CVD |
LPCVD | Low pressure CVD |
PVD | Physical Vapour Deposition |
ALD | Atomic layer deposition |
ALE | Atomic layer epitaxy |
CMP | Chemical mechanical polishing |
ECMP | Electrochemical CMP |
SOI | Silicon on Insulator |
BESOI | Bonded and Etched-Back Silicon-On-Insulator |
SOS | Silicon on Sapphire |
HSG | Hemispherical grain |
RIE | Reactive ion etching |
BSG | boron silicate glass |
PSG | phosphorous silicate glass |
BPSG | boron phosphorous silicate glass |
USG | Undoped silicate glass |
FSG | Fluorine silicate glass |
PZT | Lead zirconate titanate |
BST | Barium strontium titanate |
HSQ | Hydrogen silsesquioxane |
MBE | Molecular beam epitaxy |
ELO | Epitaxial lateral overgrowth |
MIS | Metal-insulator-semiconductor |
MOS | Metal-oxide-semiconductor |
CMOS | Complementary MOS |
DMOS | Double diffused MOS |
VDMOS | Vertical DMOS |
LDMOS | Lateral DMOS |
IMPATT | Impact Ionization Avalanche Transit Time |
TRAPATT | Trapped Plasma Avalanche Triggered Transistor |
SITh | Static induction thyristor |
FCTh | Field controlled thyristor |
IGBT | Insulated Gate Bipolar Transistor |
HET | Hot electron transistor |
SET | Single electron transistor |
SIT | Static Induction Transistor |
MBT | Metal base transistor |
RHET | Resonant tunnelling hot electron transistor |
RTT | Resonant tunnelling transistor |
BBT | Bulk barrier transistor |
PBT | Permeable Base Transistor |
HFET | Heterostructure FET |
HIGFET | Heterostructure Insulated Gate FET |
SISFET | Semiconductor-insulator-semiconductor FET |
HJFET | Hetero Junction FET |
MISFET | Metal-insulator-semiconductor FET |
JFET | Junction FET |
FinFET | FET with Fin-type channel |
MuGFET | Multi Gate FET |
HEMT | High Electron Mobility Transistor |
PDBT | Planar doped barrier transistor |
CHINT | Charge injection transistor |
LDD | lightly doped drain |
DDD | Double diffused drain |
EPIC | Epitaxial Passivated Integrated Circuit |
LOCOS | Local Oxidation of Silicon |
SWAMI | Side Wall Masked Isolation |
SILO | Sealed Isolation LOCOS |
SIMOX | Separation by Implantation of Oxygen |
FIPOS | Full Isolation by porous oxidized silicon |
ELTRAN | Epitaxial Layer Transfer |
SEG | Selective Epitaxial Growth |
DRAM | Dynamic RAM |
CCD | Charge Coupled Device |
This place covers:
Multi-step processes for the manufacture of semiconductor wafers for the fabrication of semiconductor devices as defined under H01L 21/00, prior to the fabrication of any device or part of device, i.e. between the sawing of ingots (covered by B28D) and the cleaning of the wafers (H01L 21/02041), e.g. grinding followed by lapping and polishing.
Covers the preparation of bulk semiconductor wafers (e.g. bulk silicon wafers).
See also H01L 21/8258, which has been used for classifying the fabrication of substrates containing parts of Group-IV and Group AIII-BV semiconductors.
See also C30B 33/00.
This place does not cover:
Thermal smoothening | |
The fabrication of inhomogeneous wafers, like SOI | |
Marking of wafers | |
The fabrication of wafers comprising portions of different materials | |
Forming flats |
Wafers per se are classified in H01L 29/06
This place covers:
Bulk, homogeneous wafers:
- Group IV, Si, Ge,
- Group III-V, GaAs, InP,
This place covers:
Multistep process for preparing wafers where the accent is put on a specific step.
This place covers:
Multistep process for preparing wafers where the accent is put on the grinding or lapping, e.g. multiple grinding steps.
This place covers:
Multistep process for preparing wafers where the accent is put on the backside treatment.
Includes backside treatment for recognition purposes
This place covers:
Multistep process for preparing wafers where the accent is put on the chemical etching step or steps.
Attention is drawn to the following places, which may be of interest for search:
Chemical or electrical treatment, e.g. electrolytic etching |
This place covers:
Multistep process for preparing wafers where the accent is put on the edge treatment, e.g. chamfering.
This place does not cover:
Does not cover the processing of edges of Smart Cut donor substrates, classified in reclaiming/reprocessing |
This place covers:
Multistep process for preparing wafers where the accent is put on the mirror polishing.
In case a mechanical mirror polishing is completed by a chemical flattening step, e.g. a gaseous flattening step, the latter is classified independently.
This place covers:
Multistep processes for preparing wafers having a specific orientation planes as useful plane, or a specific orientation plane in a plane parallel to the surface.
Attention is drawn to the following places, which may be of interest for search:
Single-crystal growth by pulling from a melt characterised by the seed, e.g. its crystallographic orientation |
This place covers:
Making a surface of the wafer porous. Includes formation of internal porous regions.
This place does not cover:
Localized formation (using e.g. masks) of porous regions |
This place covers:
Multistep processes for reclaiming or re-processing, a wafer containing more than a cleaning process. Also contains the re-processing of Smart-Cut donor substrates.
Attention is drawn to the following places, which may be of interest for search:
Specific cleaning for reclaiming or reprocessing |
This place covers:
Processes adapted to change the shape of a wafer, either in the surface plane (e.g. square, rectangular wafers), or in cross section (bone cross section).
This place does not cover:
The provision of flats, classified with the fabrication of the ingot |
This place covers:
Cleaning of wafers before or during manufacturing;
Cleaning is the removal of entities which were always unwanted, like particles, impurities, stringers, fences etc. Also includes the removal of edge beads or unwanted coatings on edges or backside of the wafers etc., except photoresist edge beads and photoresist on backside.
Removal of entities which have had a use or a function (sidewalls, resists etc.) is not considered to be a cleaning.
Includes the removal of natural oxide, see also the section "Special rules for classification within this group" below.
Starts with the deep cleaning carried out before first fabrication step (Piranha-RCA) up to cleaning after singulation.
Rinsing and drying are seen as a post-treatment of a wet cleaning, classified together with wet cleaning in H01L 21/02052.
This place does not cover:
Does not cover the transformation of an impurity or contaminant in something else remaining on the device, e.g. passivation, classified with passivation in general | |
Processes for the removal of only photoresists, classified in | |
Removal of excess metal after silicidation, classified in | |
Does not cover processes for the removal of photoresists edge beads after coating |
Attention is drawn to the following places, which may be of interest for search:
Cleaning apparatus | |
Cleaning by methods involving the use of tools, brushes, or analogous members, the use or presence of liquid or steam, the use of air flow or gas flow; Cleaning by electrostatic means | |
Detergent compositions, e.g. cleaning solutions or liquids |
Removal of only natural oxide is also classified in H01L 21/311 if the process is of special relevance for thick oxides.
Removal of impurities, e.g. side walls after RIE, together with the photoresist is classified in H01L 21/02041, and additionally in H01L 21/311, if the resist removal method is peculiar.
In patent documents, the following abbreviations are often used:
RCA | standard clean composed of SC-1 and SC-2 at least, with piranha and HF or DHF |
SC-1 | standard clean 1: NH4OH-H2O2 |
SC-2 | standard clean 2: HCl, H2O2 |
DHF | diluted HF |
Piranha | H2SO4-peroxide |
This place covers:
Cleaning of the wafer before any manufacturing step for the device is carried out.
Attention is drawn to the following places, which may be of interest for search:
Does not cover the transformation of an impurity or contaminant in something else remaining on the device, e.g. passivation | |
Processes for the removal of only photoresist | |
Removal of excess metal after silicidation | |
Does not cover processes for the removal of photoresist edge beads after coating |
This place covers:
All cleaning steps are dry, or when the invention is focussed on a dry cleaning aspect, the cleaning also containing more classical wet steps, like RCA.
This place does not cover:
Cleaning of diamond |
This place covers:
Wet cleaning.
This place does not cover:
Cleaning of diamond |
Rinsing and drying are seen as a post-treatment of a wet cleaning, classified together with wet cleaning in H01L 21/02052.
This place covers:
The sequence of combining wet and dry steps.
This place does not cover:
Cleaning of diamond |
Rinsing and drying are seen as a post-treatment of a wet cleaning, classified together wet cleaning in H01L 21/02052.
This place covers:
Cleaning when at least a fabrication step for a device (for example, first oxidation) has been carried out.
This place covers:
- Cleaning after etching gate sidewalls and etching of gate oxide.
- Cleaning after formation of a resist pattern
This place covers:
Reclaiming of semiconductor wafers as well as donor semiconductor wafers, e.g. donors in Smart-Cut®
This place does not cover:
Etching for reclaiming |
This place covers:
Special products to be cleaned, including particular materials as well as substrates comprising particular features, like vertical features, isolated sidewalls, etc.
This place covers:
Removal of edge beads.
This place covers:
Removal of impurities or unwanted materials on backside, including parasitic coatings.
This place covers:
The group covers inventions wherein the mechanical aspect is of particular importance. Does not exclude some enhancement by chemical means.
This place covers:
Covers processes wherein the laser action has a primary function, with or without chemical, mechanical or electrical assistance.
Attention is drawn to the following places, which may be of interest for search:
Cleaning using a laser per se |
This place covers:
Covers processes wherein the supercritical fluid has a primary function, with or without chemical, mechanical or electrical assistance.
This place covers:
Processes for the formation of inorganic and organic layers on a substrate, except photoresist layers (see H01L 21/027), for the fabrication of semiconductor devices as defined under H01L 21/00.
In situ pre- and post-treatments of these processes.
Processes for the formation of a multiplicity of these layers.
Processes for coating materials in general: C23C
Processes for the electrolytic coating of materials in general: C25D
Processes for the single-crystal growth of materials in general: C30B
This place does not cover:
Processes for forming photoresist layers, covered in | |
Processes for forming conductive layers, covered by |
Attention is drawn to the following places, which may be of interest for search:
- Multistep processes for fabricating laminates of insulating and conductive layers, for example insulated gates or capacitors, are classified in the corresponding application, H01L 21/28 for the insulated gates, H01L 28/40 for the capacitors etc. and do not need to be systematically classified in H01L 21/02107. However a group symbol in H01L 21/02107 may be given in case the process for forming the insulating layer is considered of general interest.
In this place, the following terms or expressions are used with the meaning indicated:
ALD | atomic layer deposition |
ALE | atomic layer epitaxy |
MBE | molecular beam epitaxy |
PECVD | plasma enhanced chemical vapour deposition |
PVD | physical vapour deposition |
CVD | chemical vapour deposition |
This place covers:
Processes for the formation of inorganic and organic insulating layers on a substrate, except photoresist layers (see H01L 21/027), for the fabrication of semiconductor devices as defined under H01L 21/00.
In situ pre- and post-treatments of these processes.
Processes for the formation of a multiplicity of these layers.
Includes fabrication of insulating
- porous layers,
- organic layers, like polyimide, cyclobutenes etc.
- Spin On Glass layers,
- silicate layers,
- inorganic layers, like SiO2, Si3N4, Al2O3, high-k layers, perovskites etc.
Processes for coating materials in general, including insulating materials: C23C
Processes for the electrolytic coating of materials in general: C25D
Organic or polymer layer composition: see C08G
This place does not cover:
Processes for forming photoresist layers |
Attention is drawn to the following places, which may be of interest for search:
Photoresist per se |
The process must be adapted or specific to the fabrication of semiconductor devices as defined under H01L 21/00. The mere mentioning of an intended use in semiconductor fabrication does not require that the document being given a group symbol in H01L 21/02107.
If the deposition is specifically adapted to a specific application, with details as to this specific application, e.g. the fabrication of a MIS or MOS electrode or interconnections, the document should additionally be classified in this specific application, for example in H01L 21/28 for the MIS or MOS aspect.
Attention is drawn to the following places, which may be of interest for search:
Layers comprising sub-layers, i.e. multi-layers, are additionally classified in | |
Porous layers are additionally classified in |
This place does not cover:
Carbon Nitride. |
Attention is drawn to the following places, which may be of interest for search:
Halogen doped silicon oxides, e.g. fluorine, containing BPSG, PSG, BSG |
Halogen containing materials, e.g. fluorine, containing BPSG, PSG, BSG, are additionally classified in H01L 21/02131
This place covers:
The formation of silicon oxide layers is classified in this group regardless of the precursor or of the process of formation.
Attention is drawn to the following places, which may be of interest for search:
In case of explicit statements on doping, on rest-groups, or on material components, see | |
Deposition of silicon oxide from organic precursors without further statements on film composition is classified here and in |
This place does not cover:
The formation of material containing Si, O and C, with or without additional elements | |
The formation of material containing Si, O and N, with or without additional elements |
This place does not cover:
The formation of material containing Si, N and C, with or without additional elements | |
The formation of material containing Si, O and N, with or without additional elements |
This place does not cover:
Materials containing silicon | |
Metal silicates |
This place does not cover:
Materials having a perovskite structure, e.g. BaTiO3 |
Perovskites are not classified in H01L 21/02175 and subgroups thereof.
Attention is drawn to the following places, which may be of interest for search:
Adhesion or buffer layers |
This place does not cover:
Mixtures of silane and oxygen |
In this place, the following terms or expressions are used with the meaning indicated:
Alkoxysilane | siloxane |
This place does not cover:
Mixtures of silane and oxygen |
Subject matter classified in the range H01L 21/0223 - H01L 21/02249 is additionally classified in H01L 21/02252, H01L 21/02255, and H01L 21/02258 depending on the type of reaction.
This place does not cover:
After treatment of an insulating film by plasma |
Attention is drawn to the following places, which may be of interest for search:
Formation of an insulating film by introduction of substances into an already existing insulating film is covered by |
This place does not cover:
Formation of insulating layers by plasma treatment, e.g. plasma oxidation of the substrate | |
After treatment of an insulating film by plasma |
This place covers:
Deposition methods in which the gas or vapour is produced by physical means, e.g. ablation from targets or heating of source materials.
This place covers:
Deposition methods in which the gas or vapour is produced by physical means, i.e. by ablation from targets.
This place covers:
- Deposition methods in which the gas or vapour is produced by heating of source materials.
- Molecular beam epitaxy
Attention is drawn to the following places, which may be of interest for search:
Formation of epitaxial insulating films by a deposition method also under |
This place does not cover:
Deposition by physical ablation of a target, like sputtering, reactive sputtering, physical vapour deposition, pulsed laser deposition |
Attention is drawn to the following places, which may be of interest for search:
Deposition by decomposition or reaction of gaseous or vapour phase compounds in the presence of a plasma (PECVD) |
Subject matter relating to cyclic plasma CVD is additionally classified in H01L 21/02274
Attention is drawn to the following places, which may be of interest for search:
Printing in general |
This place does not cover:
Formation of non-epitaxial layers by MBE | |
Atomic layer epitaxy [ALE] |
Attention is drawn to the following places, which may be of interest for search:
Epitaxial growth in general |
This place covers:
Treatments, carried out just before or just after the formation of an insulating layer, which do not participate in the formation of the layer itself, but which are directly linked to the layer formation.
This place does not cover:
Processes participating to the formation of a layer, for example oxidation or nitridation of silicon to form an oxide or nitride layer | |
After treatments like - etching - cleaning - planarising |
Pre- or post treatments of general nature (pre-, post-cleaning, pre-, post conditioning etc.) without details or routine annealing steps, i.e. thermal treatment without further features as to a special atmosphere, presence of a plasma, thermally induced chemical reactions, change of phase or crystal structure, need not to be given this group symbol.
This place covers:
- Treatments to improve adhesion or change the surface termination
This place does not cover:
Treatments by etching |
This place does not cover:
Ex situ cleaning, covered by |
This place covers:
The definition should read "post-treatment" instead of after-treatment.
Only covers processes that are part of the layer formation.
This place does not cover:
After- treatments performed after completion of the insulating layer |
Functionalization just after formation should be classified here.
In case the process would also be of interest as an after treatment (H01L 21/3105), both group symbols should be given.
This place covers:
Processes for introducing substances into the formed insulating layer e.g. introduction of phosphorus into silicon oxide, or introduction of nitrogen into silicon nitride to change stoichiometry.
Attention is drawn to the following places, which may be of interest for search:
For the method of introduction of the dopant |
Introduction of substances into the formed insulating layer is classified both here and in H01L 21/3115
This place covers:
Oxidation of silicon nitride to form silicon oxynitride.
This place covers:
Nitridation of silicon oxide to form silicon oxynitride.
Attention is drawn to the following places, which may be of interest for search:
Subject matter relating to cleaning processes for semiconductor device fabrication | |
Cleaning in general | |
Cleaning compositions in general | C30D |
This place covers:
Processes for the formation of inorganic semiconductors on a substrate.
Processes for forming doped inorganic semiconductors.
In situ pre-and post-treatments of inorganic semiconductor materials.
Processes for the formation of multiple layers of inorganic semiconductors, comprising heterostructures.
The formed semiconductor layer may be crystalline (mono-, poly-, microcrystalline) or amorphous.
This place does not cover:
Nanosized carbon materials, e.g. fullerenes, carbon nanotubes | |
Processes for forming layers only characterized by the purely chemical aspects of the used precursors |
Attention is drawn to the following places, which may be of interest for search:
Formation of inorganic semiconductors for light | |
Processes specially adapted for the manufacture or treatment of organic semiconductor or solid state devices or of parts thereof | |
Fullerenes used in semiconductor or solid state devices |
This place does not cover:
Carbon nanotubes used in semiconductor or solid state devices |
This place does not cover:
Ex situ cleaning |
This place does not cover:
After-treatments for improving the planarity of the layers, e.g. thermal smoothening of layers |
This group is not used for classification; subject matter relating to the formation of conductive material on a semiconductor substrate is classified in H01L 21/283 - H01L 21/288, H01L 21/3205 and H01L 21/768.
This place covers:
Formation of masks to be used for etching or patterning, formed out of a layer formed or deposited on the wafer. Includes inorganic masks (metallic or insulating materials) as well as organic masks.
Composition of photosensitive polymers, see G03F 7/00.
Photographic masks of the stencil tape or originals per se: G03F 1/00
Registration or positioning of photographic masks or originals: G03F 9/00
Photographic cameras G03B
Control of position G05D 3/00
This place does not cover:
masks for selective growth | |
masks for implantation | |
masks for forming insulating layers | |
Formation and use of stencil masks | |
Masks per se, e.g. free standing mask, stencil mask | |
Formation of photoresist masks per se | |
Formation of masks for non patterning purposes: |
Attention is drawn to the following places, which may be of interest for search:
In main group H01L 21/00 and subgroup thereof, a mask is defined as a layer, which is coated directly onto the surface of the wafer.
A free standing mask (stencil mask) laid on the wafer is not considered as a mask in the sense of H01L 21/00.
Masks are classified in H01L 21/00 only under the condition that its treatment or structure has been specially adapted to the fabrication of a device covered by H01L 21/00. Examples are:
- masks used for more than one technological step during device fabrication,
- masks whose structure, formation or treatment are adapted to the nature of the layers or materials used in the fabrication of semiconductor device, or to the device itself
This place covers:
Covers polymeric masks, including photo-sensitive masks (photoresist) as well as non photo-sensitive masks, e.g., wax, polyimide etc.
This place covers:
Treatment of photoresist layers peculiar to fabrication of electronic devices.
H01L 21/0273 covers the treatment of photoresist which is not peculiar to the type of resist (UV, e-beam, ion beam resist), for example:
- method of reflowing the resist,
- method of hardening the resist
Attention is drawn to the following places, which may be of interest for search:
Photoresists and processing of photoresists in general |
- If the treatment is peculiar to the resist type (light, e-beam or ion-beam resist), then it is classified in the corresponding subgroup. If not, remains in H01L 21/0273.
- Chemical amplification is considered to be peculiar to the resist type.
- fabricating masks by irradiating a resist with different types of radiation, e.g. photons and electrons, the document is classified in H01L 21/0273.
This place covers:
Anti-reflective coatings specially adapted for devices as defined under H01L 21/00.
Covers organic as well as inorganic anti-reflective coatings
Attention is drawn to the following places, which may be of interest for search:
Antireflective coatings for lithography in general |
This place covers:
Multilayer structures and special structures adapted to evacuate charges, e.g. multilayer resists with a conductive layer.
Multilayer resists for electrolithography should additionally be classified in G03F 7/00.
This place covers:
Includes multilayer structures.
Multilayer resists for Röntgenlithography should additionally be classified in G03F 7/00
This place covers:
Processes for forming masks comprising inorganic layers.
This group H01L 21/033 acts as a head group for inorganic masks for patterning layers. Multiple classification with H01L 21/31144 (masks for etching insulating layers), H01L 21/32139 (masks for etching conductive layers and polysilicon layers) and H01L 21/308 (masks for etching semiconductors) is possible.
This place covers:
Processes for forming masks to be used for lifting off another layer (for example having a multilayer structure or special profile) irrespective of their fabrication process
Example:
EP2132770
This place does not cover:
Lifting off for obtaining the mask |
This place does not cover:
Masks having an orientation or shape adapted to the requirements of an orientation dependent etching |
This place covers:
Mask having a shape being directly affected by and during the patterning process, e.g. erosion or re-deposition, such that the shape of the mask changes during the patterning process.
This place covers:
Processes for forming masks involving special processes, like lift-off, or sidewall formation, e.g. deposition on a step followed by anisotropic etching, or to modify the mask, e.g. oxidation of an Aluminium layer, hardening, before etching step.
This place covers:
Process specially adapted to provide a mask below the lithographic resolution limit.
Sidewall masks may also be classified in H01L 21/0337. As a sidewall spacer has inherently a sub lithographic size, it does not require an automatic group symbol here.
This place covers:
The group range from H01L 21/04 - H01L 21/326 covers processes for fabrication of semiconductor devices on substrates belonging to the semiconductors of
- group IV: Si, Ge,
- group IV: carbon, diamond,
- group III-V: GaAs, GaN, InP etc.
- group IV-IV: Silicon Carbide,
- inorganic semiconductors other than the above mentioned materials, e.g. II-VI semiconductors,
- bonding or joining semiconductor bodies
- diffusion, and alloying of impurities in these semiconductor materials
- bombardment of these semiconductor materials with radiation,
- Manufacture of electrodes on these semiconductor materials,
- special treatments of these semiconductor materials, like
thermal treatments, e.g. gettering
electroforming
mechanical treatments of these semiconductor materials
hydrogenation of these materials
treatments of insulating layers formed on these materials, including planarisation, etching,
deposition conductive or resistive layers on these semiconductor materials
treatment of these conductive layers, like planarisation, oxidation, etching, doping,
treatment of the insulating or conductive layers formed thereon,
planarisation of these semiconductor materials, or of the insulating and conductive layers formed thereon
Attention is drawn to the following places, which may be of interest for search:
Formation of insulating layers on semiconductor wafers and the direct post-treatment of this formation | |
Formation of SOI | |
Multistep manufacturing processes for semiconductor bodies of said devices | |
Multistep manufacturing processes for electrodes of said devices | |
Multistep manufacturing processes for said devices |
The presence of a potential jump barrier need not to be specified. Inventions intended to be used in the fabrication of devices having a potential barrier may be classified under H01L 21/04.
This place covers:
Passivation of semiconducting carbon, e.g. diamond
This place does not cover:
Fullerenes, e.g. C60, C70 | |
Carbon nanotubes |
Processes for fabricating devices having bodies of diamond not covered by H01L 21/041 - H01L 21/0425 are classified in H01L 21/18 - H01L 21/326 and are also mandatoril y classified in H01L 29/1602 as invention information or additional information whenever appropriate.
This place does not cover:
Preparation of SiC wafers | |
Etching, polishing of semiconducting SiC |
Processes for fabricating devices having bodies comprising crystalline silicon carbide not covered by H01L 21/045 - H01L 21/048 are classified in H01L 21/18 - H01L 21/326 and are also mandatorily classified in H01L 29/1608 as invention information or additional information whenever appropriate.
This place covers:
Processes where ion implantation of boron and subsequent annealing does produce a p-doped region in a silicon carbide.
Processes where ion implantation of boron and subsequent annealing does not produce a p-doped region are classified elsewhere, e.g. H01L 21/0445
This place does not cover:
Reduction of the copper oxide or treatment of the oxide layer |
This place covers:
Processes and apparatus which, by using the appropriate technology, are clearly suitable for manufacture or treatment of devices whose bodies comprise elements of the fourth group of the Periodic Table or AIII-BV compounds, even if the material used is not explicitly specified.
This place does not cover:
Making n- or p-doped regions for devices having semiconductor bodies of diamond; Changing their shape; Making electrodes | |
Making n- or p-doped regions for devices having semiconductor bodies comprising crystalline silicon carbide; Changing their shape; Making electrodes; Passivating silicon carbide surfaces |
This place covers:
Joining through a metal layer or eutectic layer.
This place does not cover:
Joining/bonding of semiconductor bodies through an oxide layer |
This place covers:
Direct bonding of semiconductor bodies without intermediate layer
Groups H01L 21/20 - H01L 21/2085 are no longer used for classification of documents, see H01L 21/02365 and subgroups.
This place covers:
Plasma doping.
Plasma doping is considered as doping from a gas phase, as is the case in Plasma Immersion Ion Implantation. Nevertheless, plasma doping can have ion implantation aspects like the type of ions. These aspects should be classified in ion implantation, H01L 21/265. But a group symbol e.g. H01L 21/2236 or an index code e.g. H01L 21/2236 should always be allocated to track the fact it uses a plasma.
This place does not cover:
Diffusion of killers | |
Lithium-drift |
Attention is drawn to the following places, which may be of interest for search:
Diffusion through an applied layer |
This place does not cover:
Diffusion of killers | |
Lithium-drift |
In the range H01L 21/2254 - H01L 21/2257 the main compositional part of the applied layer just before the diffusion step has to be considered for classification
This place does not cover:
Diffusion of killers | |
Lithium-drift |
This place does not cover:
Intermixing, interdiffusion or disordering of AIII-BV heterostructures |
This place does not cover:
Bombardment with radiation as post-treatment of an insulating layer |
This place does not cover:
High energy radiation creating a nuclear transmutation |
There is no exact border defining high energy. It is meant to cover alpha, beta, gamma, Röntgen... rays. The sub group H01L 21/2633 is incorrectly placed as a subgroup.
Attention is drawn to the following places, which may be of interest for search:
Thermal treatment for modifying the properties of semiconductor bodies per se | |
Ion beam tubes for localised treatment |
This place does not cover:
Crystal planes or main crystal surface and ion beam present an angle |
This place covers:
Includes processes for forming
- conductor-semiconductor,
- conductor-insulator-semiconductor, or
- conductor-insulator-conductor-insulator-semiconductor structures.
Multistep processes for manufacturing electrodes on semiconductor bodies characterized by
- a sequence of single steps, possibly including steps like deposition conductive material, alloying, silicidation,
- the structure or the shape of the electrode,
This place does not cover:
Etching for patterning the electrodes | |
Multistep manufacturing processes for data storage electrodes |
Attention is drawn to the following places, which may be of interest for search:
Mono-step processes: single diffusion of dopants, alloying of electrode materials, implantation of dopants | |
Multistep processes for forming capacitor electrodes |
Formation of electrodes only involving an etching of conductive materials, including silicide on polysilicon: H01L 21/3213 and subgroups
Information peculiar to single-step processes should also be classified in the corresponding group, e.g.
- H01L 21/311 or H01L 21/3213 for etching,
- H01L 21/3105 or H01L 21/321 for planarising
This place covers:
Processes for the fabrication of conductor-insulator-semiconductor structure, e.g. wherein the conductor is part of the interconnect (gate level interconnect).
This place does not cover:
Monosteps for forming insulators or conductors for which the application to gate electrodes is mentioned without further details. |
This place covers:
Deposition of the insulators, using epitaxiy
Deposition of the conductor and the insulator within the same process chamber.
This place does not cover:
Annealing, after the formation of the definitive gate conductor |
When the final conductor comprises a superconductor, subject matter is not classified according to H01L 21/28035 - H01L 21/28097, but instead it is classified in H01L 21/28026.
This place does not cover:
the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step |
A very thin, e.g. silicon, adhesion or seed layer is not considered as the one next to the insulator
Attention is drawn to the following places, which may be of interest for search:
Silicide formed by metal ion implantation |
To assess the coverage of groups H01L 21/28052 and H01L 21/28061, barrier layers, e.g. TaSiN, are not considered]
This place does not cover:
Conductors comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer |
To assess the coverage of groups H01L 21/28052 and H01L 21/28061, barrier layers, e.g. TaSiN, are not considered]
Documents are also classified in groups H01L 21/28035 - H01L 21/28105 when the composition is also relevant
This place does not cover:
Fabrication of lithographic masks for electrodes |
Attention is drawn to the following places, which may be of interest for search:
Lift-off aspects involving multilayer masks |
Attention is drawn to the following places, which may be of interest for search:
Forming insulating materials on a substrate |
In case the formation of the insulator would be of general interest, a group symbol should be given in H01L 21/02107.
In this place, the following terms or expressions are used with the meaning indicated:
RTN | Rapid Thermal Nitridation |
RPN | Rapid Plasma Nitridation |
This place does not cover:
Evaporation, ALD, CVD, sputtering, laser deposition | |
Nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN |
Thin oxidation layers used as a barrier layer or as a buffer layer, e.g. before the fomation of a high-k insulator, are classified here only if important per se.
In case the transformation would be of general interest it should be classified in
This place covers:
H01L 21/283 - H01L 21/2885 cover the deposition of conductive layers directly in contact with the semiconductor for forming electrodes.
This place does not cover:
Formation of electrodes of capacitors, resistors, inductors |
Application to contacts must be mentioned with details. Moreover, details of deposition processes of conductive layers covered by H01L 21/3205 are additionally classified in this group and subgroups thereof. If a document discloses information relevant for any of the groups H01L 21/768 - H01L 21/76898, one or more of these groups should also be assigned.
This place covers:
Methods for depositing conductive layers using gases or vapours of metals or metal-containing precursors.
This place does not cover:
Deposition of polysilicon in contact with a semiconductor | |
Formation of electrodes of capacitors, resistors, inductors |
Attention is drawn to the following places, which may be of interest for search:
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes |
The deposition process (PVD, CVD, ALD etc.) must be specially adapted for forming contacts or interconnects within semiconductor devices and must be disclosed in detail, i.e. include details on deposition parameters, precursor materials, particular apparatus details etc.
If a document discloses information relevant for any of the groups H01L 21/768 - H01L 21/76898, one or more of these groups should also be assigned.
This place does not cover:
Conductive layers comprising silicides | |
Deposition of Schottky electrodes |
Deposition of polysilicon on silicon classified there only if application to contacts is mentioned. Otherwise H01L 21/02365
Deposition of polysilicon on silicon classified there only if application to contacts is mentioned. Otherwise H01L 21/02365
This place covers:
The deposition of conductive layers directly in contact with semiconductors for forming electrodes using liquid deposition techniques, e.g. electroless plating.
This place does not cover:
Formation of electrodes of capacitors, resistors, inductors |
Attention is drawn to the following places, which may be of interest for search:
Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating |
The deposition process must be specially adapted for forming contacts or interconnects within semiconductor devices and must be disclosed in detail, i.e. include details on deposition parameters, precursor materials, particular apparatus details etc.
If a document discloses information relevant for any of the groups H01L 21/768 - H01L 21/76898, one or more of these groups should also be assigned.
This place covers:
- mechanical treatments, like grinding, sand blasting etc.
- hydrogenation of these semiconductors
- chemical treatments, like etching,
- formation of insulating layers and after treatment of these layers, like planarisation, etching, formation of conductive layers on these insulating layers and after treatment of these conductive layers and their doping.
This place does not cover:
the treatment of II-VI compounds | |
the treatment of insulating layers | |
the treatment of metallic |
Attention is drawn to the following places, which may be of interest for search:
Manufacture of electrodes thereon |
This place covers:
Mechanical treatment of semiconductor wafers or semiconductor layers, except the mechanical treatment of insulating or conductive layers on semiconductor wafers.
This place does not cover:
Polishing of semiconductor wafers | |
Polishing of epitaxial layers on semiconductor wafers | |
Mechanical treatment of insulating | |
Conductive layers on wafers | |
Single step mechanical operations, like sawing, polishing, breaking etc. classified in the corresponding group in section B |
The mere use of a machine is classified with the machine only.
Process for the mechanical treatment, enhanced by chemical treatment, is classified in chemical treatment, but may be given a group symbol in mechanical treatment if the mechanical treatment itself is of importance for the invention.
Purely mechanical polishing is considered as chemical-mechanical polishing, and is classified accordingly.
This place covers:
Making grooves, which may result in cutting
This place does not cover:
Singulation of wafers into dies |
This place covers:
- Chemical or electrical treatment of group IV or III-V semiconductors.
- Formation of porous semiconductors,
- Functionalisation of semiconductor surfaces
This place does not cover:
Chemical or electrical treatment to form insulating layers |
This place covers:
Anisotropic liquid etching, i.e. "crystal orientation dependant" etching, using basic (pH>7) compositions. The etch composition is often composed of KOH, amines, azines, quaternary ammonium compounds
This place does not cover:
Electrolytic etching | |
Anisotropic etching for tartarising surfaces |
Attention is drawn to the following places, which may be of interest for search:
Etching for fabrication of MEMs. |
This place covers:
Reactive Ion Etching [RIE] of III-V
This place covers:
Processes for polishing semiconductors not being part of the sequence for preparing wafers from an ingot (H01L 21/02013 or H01L 21/02024).
Covers polishing or CMP of semiconductor layers deposited on a substrate, like epitaxial layers.
This place does not cover:
Polishing or CMP of bulk wafers, wherein the polishing is part of the sequence for preparing wafers from an ingot | |
Polishing or CMP of insulating layers | |
Polishing or CMP of conductive layers |
Chemical-mechanical polishing also includes purely mechanical polishing.
This place does not cover:
formation of porous materials by electrolysis |
Attention is drawn to the following places, which may be of interest for search:
Electrolytic etching in general |
This place covers:
- sputter etching,
- particle (electron, ion, photon) beam enhanced etching
- light assisted etching.
- plasma etching
- dry etching, i.e. using an etching gas without plasma
This place does not cover:
Reactive ion etching of III-V materials |
Attention is drawn to the following places, which may be of interest for search:
Laser etching without reactive atmosphere per se |
This place covers:
- Masks used for patterning semiconductors of group IV or III-V, including masks used for plasma etching/patterning, excepted masks for electrolytic etching.
- The fabrication of masks to be used for etching or patterning semiconductors (non-monocrystalline semiconductors being excluded).
This place does not cover:
Formation of masks for non patterning purposes, which are classified with the step in question: - masks for implantation - masks for forming insulating layers, - masks for selective growth, - masks for patterning semiconductors belonging to groups other than group IV and group III-V. | |
Electrolytic etching | |
Formation and use of stencil masks | |
Free standing masks, e.g. stencil masks | |
Formation of photoresist masks per se, except if the formation of the photoresist mask is specific to the device to be fabricated or semiconductor substrate |
Attention is drawn to the following places, which may be of interest for search:
General masks for patterning in the fabrication of semiconductor device | |
Masks for patterning insulating layers | |
Masks for patterning conductors, including polycrystalline or amorphous silicon |
A mask in H01L 21/00 is formed of a layer coated directly onto the surface of the wafer.
A free standing mask (stencil mask) laid on the wafer is not considered as a mask in the sense of H01L 21/00.
Masks are classified in H01L 21/308 only under the condition that its treatment or structure has been specially adapted to the fabrication of a device covered by H01L 21/00. Examples are:
- masks used for more than one technological step during device fabrication,
- masks whose structure, formation or treatment are adapted to the nature of the layers or materials used in the fabrication of semiconductor device, or to the device itself
The takes precedence rule (stemming from IPC) pointing to H01L 21/3065 is not valid for CPC: masks for etching by plasma or reactive ion etching are given a group symbol here.
Masks for electrolytic etching are classified with the electrochemical etching in H01L 21/3063.
Using stencil masks for ion implantation is classified in H01L 21/266.
This place covers:
Masks having a specific behaviour during etching process. e.g. erodible mask, shrinking mask etc.
This place does not cover:
Processes wherein the etching is interrupted to modify the mask (sequential etching), e.g. etching, followed by modifying the mask, followed by re-etching, with possible cycling of the above steps |
This place covers:
Covers pre-treatment for the formation of a mask, post treatment of the mask before etching, treatments to modify the mask before use, e.g. hardening, formation of sidewalls, multiple sidewalls etc.
This place does not cover:
Modification of the mask during etching | |
Removal of the mask after use |
Attention is drawn to the following places, which may be of interest for search:
Photoresist for lift | |
Inorganic masks for lift-off |
This place covers:
Process specially adapted to go below resolution limit of lithography.
This place covers:
Processes for forming insulating layers and their direct post-treatment.
To be used in any process, formation of interconnects, isolation oxides etc.when the invention is focussed on the insulator.
Attention is drawn to the following places, which may be of interest for search:
Insulating layers forming part of electrodes | |
Encapsulating layers |
This place covers:
Covers special treatments of insulating layers, wherein the special treatment is not a post-treatment as defined under H01L 21/00, i.e. the classical annealing of the insulating layer to improve its characteristics, but is for example
planarisation, patterning, functionalization after etching.
This place does not cover:
Classical annealing after formation of the insulator, classified together with the formation |
Functionalization just after formation should be classified with the formation.
In case the process would also be of interest as a post treatment, both classes should be given.
This place covers:
- Planarisation of insulating layers.
- Atomic scale planarisation (smoothening) of the insulating layers.
- Reflow of insulating layers.
This place does not cover:
After treatment, e.g. planarisation, of organic layers |
This place covers:
Planarisation involving a removal step not being a chemical etch step: this is the group for polishing and chemical-mechanical polishing (CMP) of insulating materials.
This place covers:
Planarisation by non selective etching, e.g. by a blanket etching reducing the protrusions.
Attention is drawn to the following places, which may be of interest for search:
Etching per se |
This place covers:
Processes where protrusions are selectively etched through a mask.
Attention is drawn to the following places, which may be of interest for search:
Etching glass |
This place covers:
Etching by wet process, or by processes wherein gaseous reactants are condensed on the surface.
Gaseous etch with HF is classified in H01L 21/31116
This place covers:
Removal of organic layers or polymers, including photoresists peculiar to semiconductor wafers or devices.
This place does not cover:
The removal of silicon-containing compounds having an organic nature. |
Attention is drawn to the following places, which may be of interest for search:
Removal of photoresist not peculiar to semiconductor wafers |
Removal of photoresist being not peculiar to semiconductors is classified in G03F 7/42.
Peculiar to semiconductor devices means that particular precautions are taken to avoid influence of the removal of the photoresist on the semiconductor wafer or device.
This place covers:
Etching by wet process, or by processes wherein gaseous reactants are condensed on the surface.
This place covers:
Etching involving a specially adapted mask
In case the mask would be of general interest, it should also be classified in H01L 21/033
Attention is drawn to the following places, which may be of interest for search:
See also after treatment of insulating layers | |
Doping with the purpose to alter resistivity or increase conductivity |
Implantation or diffusion into insulating layers is also classified under H01L 21/02318 and subgroups.
Attention is drawn to the following places, which may be of interest for search:
Photoresists per se |
H01L 21/312 - H01L 21/3128 are no longer used for classification of new documents, see H01L 21/02112.
H01L 21/314 - H01L 21/3185 are no longer used for classification of new documents. See H01L 21/02112.
This place covers:
Deposition of conductive layers exclusively on insulating layers, when the process of deposition is relevant.
This place does not cover:
Deposition of conductive layers on semiconductor |
When the technique of deposition is particular (CVD, PVD or electroplating), also classify in H01L 21/283, H01L 21/285 or H01L 21/288. When an interconnection is concerned, see also H01L 21/768 and subgroups.
This place covers:
Treatment of formed conductive layers. Includes:
- etching by chemical or physical means,
- planarisation, including chemical-mechanical polishing,
- oxidation, nitridation, or surface treatment,
- doping.
Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups.
Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. After treatment of layers of these materials is thus classified here.
For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.
This place covers:
Oxidation of non-monocrystalline silicon, e.g. polycrystalline, microcrystalline or amorphous silicon.
This place does not cover:
Oxidation of monocrystalline silicon |
Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Oxidation of layers of these materials is thus classified here.
For classifying in the group range H01L 21/321 - H01L 21/3215, the presence of an insulating layer below the conductive or resistive layers is not mandatory.
This place covers:
Nitridation of non-monocrystalline silicon, e.g. polycrystalline, microcrystalline or amorphous silicon.
This place does not cover:
Nitridation of monocrystalline silicon |
Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Nitridation of layers of these materials is thus classified here.
For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.
This place covers:
Planarisation of conductive or resistive layers.
Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Planarisation of these layers is thus classified here.
For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.
Attention is drawn to the following places, which may be of interest for search:
CMP slurries |
This place covers:
Physical or chemical etching of conductive or resistive layers.
Etching of polysilicon layers
Etching of amorphous silicon layers
Attention is drawn to the following places, which may be of interest for search:
Machines or apparatus for liquid etching | |
Machines for plasma etching |
Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Etching of layers of these materials is thus classified here.
For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.
This place covers:
Etching processes, where no chemical reaction is involved, e.g.
sputtering, ion milling, laser ablation, pure ion beam etching.
For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.
This place covers:
Silicides and silicon alloys.
This place covers:
Use of Plasmas, e.g. RIE, and chemically assisted particle (ion or electron, photon) beam etching
For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.
This place covers:
Etching with supercritical fluids
This place covers:
Etching assisted by electrons, ions and laser beams.
This place covers:
Polysilicon, amorphous, silicides, multilayers containing silicon
This place covers:
Pre-treatments before etching, including removal of natural oxide.
Anti-corrosion post-treatments.
This place does not cover:
Post-treatment after etching, e.g. RIE |
In case the pre-treatment is a removal of natural oxide and is of general interest, a group symbol in H01L 21/02041 should be given.
In case the post treatment is a passivation by oxidation or nitridation this step should be classified independently.
For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.
This place covers:
Etching involving a mask specifically adapted to the etching operation.
This place does not cover:
Classical photoresist masks, except if submitted to a special treatment, for example hardening, fluorination, etc. |
In case the mask would be of general interest, it should also be classified in H01L 21/033.
For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.
Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Doping of these layers is thus classified here.
For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.
This place covers:
- Treatments aimed at modifying the intrinsic properties of the crystals not otherwise provided for in H01L 21/00, like crystallographic defect rate.
- Formation of defects for intrinsic or extrinsic gettering
This place does not cover:
Modification of conductivity type |
This place covers:
Extrinsic gettering
Gettering using both extrinsic and intrinsic gettering techniques is classified in both H01L 21/3221 and H01L 21/3225.
This place covers:
Intrinsic gettering
This place does not cover:
Treatment of semiconductor bodies to modify their internal properties of silicon on insulator |
Gettering using both extrinsic and intrinsic gettering techniques is classified in both H01L 21/3221 and H01L 21/3225.
This place covers:
Processes for fabricating devices having semiconductor bodies not belonging to group IV, IV-IV, III-V materials, or to Se, Te, CuO.
Processes for fabricating devices having semiconductor bodies based on II-VI materials.
This place does not cover:
Inorganic semiconducting materials used for light detecting devices, e.g. I-III-VI materials, like CuInSe | |
Processes peculiar to the fabrication of light sensitive devices | |
Processes peculiar to the fabrication of inorganic light emitting devices |
As already evident from the limiting reference in the main group title of H01L 21/00, only fabrication processes relating to devices covered by main groups H01L 21/00 - H01L 29/00 should be classified under H01L 21/34.
- A single mention of an application in manufacturing devices covered by main groups H01L 21/00 - H01L 29/00, e.g. a junction FET, is sufficient to give a group symbol.
- at the other hand processes wherein the type of fabricated device is not mentioned at all will be considered to refer to devices not belonging to those covered by H01L 21/00 - H01L 29/00, and will consequently be classified together with the most probable application, e.g. H01L 31/00 for II-VI for light-sensitive devices.
This place covers:
Doping of II-VI materials.
Attention is drawn to the following places, which may be of interest for search:
Semiconductor bodies composed of II-VI compounds for light sensitive devices |
This place covers:
Radiation covers corpuscular as well as electromagnetic radiation
This place does not cover:
Bombardment with radiation for deposition purposes | |
Bombardment with radiation for etching purposes |
Attention is drawn to the following places, which may be of interest for search:
Ion beam tubes for localized treatment |
This place covers:
Processes for implantation wherein the invention is focused on the mask aspect, e.g. mask having a specific topography.
Attention is drawn to the following places, which may be of interest for search:
Masks in general |
This place covers:
Electrodes on semiconductor materials as defined under H01L 21/34.
Covers the direct deposition of conductive materials on the semiconductor and on an insulating layer overlying the semiconductor (e.g. Tunnel contact).
The group H01L 21/44 includes specific treatments of the semiconductor before formation of the contact (e.g. degenerescence by bombardment etc.).
This place does not cover:
semiconductor materials of group IV or III-V |
This place covers:
Insulating materials, only if the contact is a tunnelling contact.
This place covers:
- Electrolytic deposition
- Electroless deposition
Classification is made in this group only if specific to the semiconductor material, or adapted to the type of device.
Classification is made in this group only if specific to the semiconductor material, or adapted to the type of device.
This place covers:
The treatment of semiconductor bodies including
- mechanical treatments, like grinding, sand blasting etc.
- chemical treatments, like etching,
- after-treatments of these semiconductors, like formation of insulating layers, planarisation or etching of these insulating layers, formation of conductive layers on these insulating layers and after treatment of these conductive layers and their doping.
Attention is drawn to the following places, which may be of interest for search:
Manufacture of electrodes thereon |
Attention is drawn to the following places, which may be of interest for search:
Chemical or electrical treatment to form insulating layers thereon |
This place does not cover:
Masks used for patterning group IV and group III-V semiconductors |
This place does not cover:
Encapsulating layers |
Attention is drawn to the following places, which may be of interest for search:
Layers forming electrodes |
This place does not cover:
Forming insulating layers using masks | |
After-treatment |
Attention is drawn to the following places, which may be of interest for search:
Formation of photoresist masks |
Attention is drawn to the following places, which may be of interest for search:
Manufacture of electrodes |
This place does not cover:
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups |
Attention is drawn to the following places, which may be of interest for search:
Insulating sealing of leads in bases | |
Apparatus therefor | |
Containers, encapsulations, fillings or mountings per se | |
Marking of parts | |
Arrangements for connecting or disconnecting semiconductor or other solid-state bodies, or methods related thereto, other than those |
In this group, the expression "treatment" also covers the removal of leads from parts.
This place does not cover:
Arrangements for connecting or disconnecting semiconductor or other solid state bodies, or methods related thereto, other than those |
This place covers:
the apparatus of the title and also the use of those apparatus
This place does not cover:
Welding apparatus | |
Polishing apparatus | |
Apparatus for cutting semiconductor ingot | |
Coating apparatus | |
Electroplating apparatus | |
Optical measuring apparatus | |
Testing apparatus | |
Lithographic apparatus |
Attention is drawn to the following places, which may be of interest for search:
Cleaning in general | |
Cutting in general | |
Robots in general | |
Conveying in general | |
Electrostatic holders in general |
In this place, the following terms or expressions are used with the meaning indicated:
Substrate | a substrate suitable for semiconductor or electric solid state devices or semiconductor or electric solid state components, e.g. a wafer |
This place covers:
- Fluid delivery or exhaust systems (like plumbing, heat exchanger, valves systems, flow regulations means, pumping means) in direct connection with semiconductor manufacture or handling systems.
- Atmosphere control systems in relation with semiconductor industry
This place does not cover:
Apparatus for sealing, encapsulating, glassing, decapsulating | |
Apparatus for applying a liquid, a resin, an ink | |
Details relating to the exhausts (e.g. pumps, filters, scrubber) of coating apparatus |
Attention is drawn to the following places, which may be of interest for search:
Containers with atmosphere control |
This place covers:
- Apparatus dealing with at least two processing steps taking place successively (like cleaning, drying, rinsing, stripping or blasting) are classified in this group.
- Systems for only dry cleaning.
This place covers:
- apparatus for dividing wafers into a plurality of parts (dicing),
- apparatus for exerting a pressure on a substrate (like apparatus for bonding two wafers together),
- apparatus for separating two bonded wafers.
This place does not cover:
Cutting apparatus per se | |
Polishing apparatus | |
Apparatus for cutting semiconductor ingot |
Attention is drawn to the following places, which may be of interest for search:
Division of the substrate into plural individual devices |
This place covers:
- Apparatus where the substrate is in direct contact with the heating element
- Heating elements with specific thermal properties (like thermal conductivity), e.g. materials of the heating element.
This place covers:
- Apparatus where the substrate is not in direct contact with the heating element
- Thermal apparatus with cooling means, e.g. for temperature regulation
This place covers:
Thermal apparatus comprising lamps, infrared light irradiation means or ultraviolet light irradiation means
This place covers:
- Sealing arrangements (like O-ring) for a process chamber, a holding or transporting device
- Slit valves or gates for closing the opening of a chamber
Attention is drawn to the following places, which may be of interest for search:
Containers; Seals for semiconductor devices | |
Encapsulations, e.g. encapsulating layers, coatings for protection |
This place covers:
- All apparatus dealing with tapes (tape removal apparatus, tape placing apparatus)
- Apparatus for removing dies from an adhesive tape (on which a severed wafer is placed).
This place covers:
Pick and Place apparatus (picking a die from a wafer and placing it on a different location).
This place does not cover:
Apparatus for sealing, encapsulating, glassing, decapsulating |
This place does not cover:
Coating by ion implantation |
Attention is drawn to the following places, which may be of interest for search:
Ion or electron beam tubes |
This place does not cover:
Polishing apparatuses per se |
This place does not cover:
Lithographic apparatuses per se |
This place does not cover:
Electrical testing individual semiconductor devices |
Attention is drawn to the following places, which may be of interest for search:
Testing or measuring | |
Marks per se |
Attention is drawn to the following places, which may be of interest for search:
Program-control systems per se | |
Total factory control |
Attention is drawn to the following places, which may be of interest for search:
Holders for supporting a complete device in operation |
Attention is drawn to the following places, which may be of interest for search:
Magazine for components |
Attention is drawn to the following places, which may be of interest for search:
Containers and packaging elements for glass sheets | |
Transporting of glass products during their manufacture |
This place does not cover:
Closed carriers specially adapted for containing chips, dies or ICs | |
Closed carriers specially adapted for containing masks, reticles or pellicles |
Attention is drawn to the following places, which may be of interest for search:
Materials relating to an injection moulding process | |
Chemical composition of macromolecular compounds |
This place does not cover:
Conveying using magnetic elements |
This place does not cover:
Conveying cassettes, containers or carriers |
Attention is drawn to the following places, which may be of interest for search:
Robots in general |
This place does not cover:
The workpieces being stored in a carrier, involving loading and unloading |
Attention is drawn to the following places, which may be of interest for search:
Robots in general |
This place covers:
Apparatus for moving substrates on a liquid track
This place does not cover:
Conveying with angular orientation of the workpieces | |
Conveying with orientating and positioning by means of a vibratory bowl or track |
Attention is drawn to the following places, which may be of interest for search:
Conveying |
Attention is drawn to the following places, which may be of interest for search:
Conveying | |
Positioning, orientation or alignment |
This place does not cover:
Temporary protection of the devices or parts of the devices during manufacture |
Attention is drawn to the following places, which may be of interest for search:
Adhesive tapes in general |
This place does not cover:
Using electrostatic chucks |
This place covers:
- Process for the integration of a plurality of solid state devices in or on a common substrate.
- Processes for making isolation regions between components (e.g. LOCOS, STI etc.)
- Processes for fabricating SOI substrates.
- Processes for making interconnections between the solid state devices, on the surface of the substrate, or buried in the substrate, including specific treatments of these interconnections.
- Processes for cutting wafers to singulate the devices, dicing.
- Processes to fabricate devices consisting of a plurality of solid state components or integrated circuits of the bipolar, Field-Effect type and memories.
- Process for the assembly on a common substrate of two or more components.
Attention is drawn to the following places, which may be of interest for search:
Manufacture of assemblies consisting of preformed electrical components |
This place covers:
- Multistep processes for the fabrication of buried regions, also used as buried connections between zones,
- Multistep processes for the fabrication of zones providing electrical isolation between adjacent components,
- Multistep processes for the fabrication of SOI wafers, for which the fabrication of devices has not started yet,
- Multistep processes for the fabrication of interconnections between devices,
- Multistep, processes for the fabrication of integrated circuits, bipolar technology, field-effect technology, CMOS, memories, IC based on combinations of these technologies,
- Multistep processes for dicing wafers into individual devices.
This place does not cover:
Processing of parts of devices based on carbon or diamond | |
Processing of parts of devices based on crystalline Silicon Carbide | |
Multistep processes for the manufacture of electrodes | |
Manufacture or treatment of parts prior to assembly of the devices, like leads, heat-sinks, etc. |
Attention is drawn to the following places, which may be of interest for search:
Wire-like connections |
This place covers:
Multistep processes for the fabrication of buried regions, like buried collector layers, buried connections between zones, substrate contacts, as part of a component, e.g. formation of buried silicides.
Attention is drawn to the following places, which may be of interest for search:
Diffusing impurities | |
Implanting impurities |
This place covers:
Fabrication of buried metallic or near metallic regions, like buried silicides, buried eutectic conductors.
This place covers:
- Fabrication of zones aimed at providing electrical isolation between adjacent components, i.e. dielectric regions (LOCOS, trench, shallow trench), air gaps, p-n junction or field effect.
- Fabrication of SOI wafers, for which the fabrication of devices has not started yet.
For subject matter classified in the range H01L 21/76 - H01L 21/765, when the isolation combines several techniques, both techniques are given a group symbol.
When the combination of several techniques involves the fabrication of SOI, a group symbol within the range H01L 21/76264 - H01L 21/76291 is given.
Single steps, like etching a trench, when they present a general interest or are specifically disclosed, should be given a group symbol in the corresponding single step covered by H01L 21/02 and sub groups.
In this place, the following terms or expressions are used with the meaning indicated:
horizontal | in the plane of the wafer |
vertical | in a direction perpendicular to the plane of the wafer |
This place covers:
Covers the formation of dielectric regions by
- Oxidation of the substrate, or
- Deposition of a dielectric, for example in a trench.
- Formation of dielectric regions buried in the substrate, SOI
Attention is drawn to the following places, which may be of interest for search:
Trench filling with vertical isolation, e.g. trench refilling in a SOI substrate | |
Trench filling with polycrystalline silicon |
This place covers:
The groups H01L 21/7624 - H01L 21/76291 cover the fabrication of a buried isolation region
This place does not cover:
Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit |
Attention is drawn to the following places, which may be of interest for search:
Manufacture of integrated circuits on insulating substrates | |
Silicon on sapphire (SOS) technology |
This place covers:
Multi-steps processes for manufacturing interconnections on the surface of a device or through the wafer.
This place does not cover:
Fabrication of contacts | |
Internal interconnections | |
Fabrication of fuses and anti-fuses |
Attention is drawn to the following places, which may be of interest for search:
Cleaning | |
Formation of insulating layers | |
Formation or use of masks | |
Planarising insulating or conductive layers | |
Etching of insulating or conductive layers |
Information peculiar to single-step processes should also be classified in the corresponding sub group of H01L 21/02 (see informative references below).
Processes for fabricating fuses and anti-fuses are classified with the fuses and anti-fuses in H01L 23/525.
This place covers:
Methods specially adapted for forming via or contact holes having a wider top or bottom region, e.g. "cup-shaped" vias
Attention is drawn to the following places, which may be of interest for search:
Etching insulating layers per se |
This place covers:
Methods of forming via or contact holes including a step of etching the conductor at the bottom of the hole so as to form e.g. a gouging feature;
methods of forming contact holes having a portion reaching into conductive regions (e.g. source and drain) of the semiconductor substrate
This place covers:
Methods of dual damascene processing involving intermediate temporary filling of the opening first formed in the process with material, e.g. planarisation to facilitate lithography of the second opening
Examples:
- After formation of the via, the via is filled with a resin film 12 to provide for planarisation:::
US2006094221.
- The dual damascene structure of a lower metal level 200 is filled with a sacrificial material 140 (see the figure below), then another metal level 202 having dual damascene structures 232 is fabricated. Finally, the sacrificial layer 140 is removed and all metal levels are metalized simultaneously:
US2005110145
This place does not cover:
Conventional trench-first dual damascene methods in which the photoresist for forming the via hole fills the trench |
This place covers:
Methods of dual damascene processing involving one or more buried masks, i.e. one or more pre-patterned mask or etch stop layers are fabricated prior to deposition of the trench-level dielectric.
Examples:
- The etch stop 114 is pre-patterned and buried under ILD 118 (see the figure below):
WO2005109473
This place covers:
Methods of dual damascene processing involving multiple stacked pre-patterned masks on the trench-level dielectric, i.e. mask stacks pre-defining the trench and via patterns before the actual etching process
Examples:
Layers 135, 140, 150 are hardmask layers, layer 180 is a photoresist for patterning layer 150. The dual damascene structure is transferred into the ILD 130 with the help of the stack of pre-patterned hardmasks 135, 140, 150:
US2003207207
This place covers:
All dual damascene processes in which in an early stage a via is formed partially through the dielectric stack. The via etch is completed later in the process, e.g. during the etching step for forming the trench.
Examples:
US2006166482
First, the via is partially etched into the dielectric stack. In a later step, the via etch is completed together with the trench etch.
Dual damascene processing also involving a stack of pre-patterned hard mask layers, the group symbol H01L 21/76811 is also assigned.
If the partial via process also includes a step of intermediate filling the partial via with a planarising material, the document needs to be classified in H01L 21/76808, too.
This place covers:
Particular method steps designed for improving the result of a process of forming an interconnect opening in a dielectric, e.g. removal of oxides from the surface of a conductor at the bottom of a via hole, removal of etching residues, or treatments restoring the dielectric at the sidewalls.
Examples:
After formation of the opening 10, the photoresist mask and etch residues are removed using a reducing plasma. During this treatment an undesired coating layer 14 forms on the sidewalls of opening 10. Layer 14 is eventually removed by the directional beam of charged oxidizing particles having its main axis 20 parallel to the sidewalls of opening 10:
US6673721
Note that in this case the sidewall layer 14 is an undesired by-product of a plasma treatment process. The document should therefore not be classified in H01L 21/76831.
After forming an opening in a low-k dielectric, a degassing treatment and a plasma treatment are carried out in order to remove methyl groups from the dielectric and an oxide from the underlying conductor 22A:
US2005272247
This place does not cover:
After-treatment steps leading to the formation of modified sidewall layers |
If the method of after-treatment comprises aspects which are classified in any one of the subgroups H01L 21/76822+ (see below), the corresponding group should also be given. If the after-treatment leads to the formation of a sidewall layer in the opening comprising modified dielectric material, the group H01L 21/76831 should also be assigned (note, however, that if the sidewall insulation is formed by a conventional deposition step, H01L 21/76831 is the only relevant group).
H01L 21/76814 is essentially a multistep group, i.e. the after treatment step is only one of several steps to be carried out in order to form an interconnection. If a document exclusively relates to cleaning of openings in dielectrics (in a single-step fashion), the main group symbol is H01L 21/02063.
This place covers:
The geometrical "aspects" to be classified in this group are mainly methodological aspects, e.g. step sequences leading to a reduction of the pitch between via holes, step sequences for incorporating a plurality of vias of different depth, methods of forming vias having a particular cross-sectional shape.
Examples:
Layer 230 is introduced into the structure to enable the simultaneous formation of a deep and a not-so-deep via. Although the formation of the vias themselves contains no special features at all, there is an aspect related "to the size of the vias":
US2006281290
Method for decreasing the pitch between adjacent contact holes by using a sequence of steps involving among other things a sacrificial pattern (13 in the figure below) and a conformal hardmask layer (14') to create an array of vias having a pitch below what is possible by standard lithography:
EP1818977
This place does not cover:
Geometrical aspects relating to "tapered" vias, i.e. vias having a wider part somewhere |
This place covers:
Imprinting or stamping techniques for forming openings in dielectrics.
Methods using a stamp either to pattern a mask, e.g. a resist mask, for forming the opening or to imprint the opening directly into a dielectric
Example:
US7148142
Attention is drawn to the following places, which may be of interest for search:
Planarisation of insulating materials per se |
This place covers:
All aspects related to forming or after-treatment steps which lead to a modification of the material of a dielectric layer within an interconnection structure.
Manufacture of "graded" dielectric layers having a varying composition throughout its thickness, no matter if said grading is achieved by a modified deposition process or an after-treatment.
Examples:
Graded dielectric layer: density and permittivity characteristics vary uniformly from a top portion to a bottom portion of the layer. The variation is achieved through varying deposition parameters such as flow rate of constituent process gases or deposition chamber pressure, or through a post deposition treatment, such as plasma treatment or curing:
US2006003598
The surface of the PSG layer 704 is made hydrophilic by a "scrubbing treatment" 710:
US2006003582
It is not important whether the various treatment steps are conducted on a "main" interlevel or intralevel dielectric or on a "thin functional dielectric layer" as defined in H01L 21/76829 and subgroups.
If the treatment involves a patterned layer including an opening, the group H01L 21/76814 should also be given.
This place covers:
Processes designed for rendering a dielectric layer of an interconnect stack conductive
Examples:
A diamond etch-stop layer (66 in the figure below) is rendered conductive by implanting Ti followed by thermal treatment.
US5990493
A document classified in this group is additionally classified in H01L 21/76822 and subgroups thereof, whenever appropriate, the method of conversion involves a plasma treatment, or an ion implantation.
This place covers:
After-treatment or post-treatment process of dielectric layers of the interconnect stack involving particle radiation, e.g. removal of moisture etc. by UV or e-beam radiation, processes for modifying the dielectric constant of the layer, introduction of dopants into the dielectric by particle irradiation.
Examples:
A layer of silane is deposited onto a polymer dielectric layer 16. This layer is then exposed to UV light to initiate polymerization of the silane molecules to form an adhesion promoter layer 18 (or an etch stop or hard mask layer), and to react the adhesion promoter layer with low dielectric constant polymer layer 16:
US2005221606
The upper surface of the porous MSQ film 105 is treated by electron beam irradiation or by UV irradiation to reinforce the upper portion in the film 105:
US2006211235
This place does not cover:
Removal of porogens for manufacturing porous dielectrics | |
Plasma treatment |
If the treatment is performed to form or modify a "thin functional" dielectric layer, e.g. an etch stop, one of the groups H01L 21/76829 is additionally assigned.
Curing of a dielectric precursor material is generally not considered an "after-treatment" but characterizes the formation of the dielectric layer per se, covered by H01L 21/02348.
This place covers:
Processes involving contacting a dielectric of an interconnect stack with gases, liquids or plasmas in order to modify the internal structure and/or properties of the dielectric, e.g. nitridation, removal of organic groups from the layer, introduction of dopants into the dielectric using gases, liquids or plasmas.
Examples:
a low-k dielectric is treated in a supercritical fluid after deposition, after via etching, to improve mechanical strength or repair plasma damage:
US2006073697
Plasma treatment 130 is carried out in order to decrease the C- or F- concentration in an upper layer 120a of the ILD 120:
US2006286793
Plasma treatment is carried out in order to modify the sidewalls of a damascene opening 218:
US6013581
Attention is drawn to the following places, which may be of interest for search:
Supercritical fluid treatment after a via hole formation | |
Plasma treatment is carried out to form a modified sidewall layer in an opening |
If the plasma treatment is carried out to form a modified sidewall layer in an opening, the group symbol H01L 21/76831 must also be assigned.
This place covers:
Thermal treatment for modifying the internal structure and/or properties of the dielectric of an interconnect stack, e.g. removal of moisture.
Example:
After completion of the deposition, the low-k dielectric layer 206 is subjected to a heat treatment in a nitrogen-free atmosphere to promote the out-gassing of the volatile materials 220 and especially of nitrogen and nitrogen compounds:
US2004121265
Attention is drawn to the following places, which may be of interest for search:
Plasma annealing |
If the heat treatment is carried out in reactive atmospheres, i.e. inevitably involves modification of the dielectric material by e.g. introducing a further chemical element into the layer, e.g. plasma annealing, the group symbol H01L 21/76826 is additionally assigned.
This place covers:
All aspects related to the formation and the geometry of so-called "thin functional dielectric layers", e.g. etch-stop films or dielectric barrier or liner layers.
Examples:
Fabrication of an oxygen-doped low-k SiC etch-stop layer 230:
US2003085408
Nitride liner 130 imparts tensile stress in the underlying semiconductor to improve carrier mobility:
US2005233514
Silicon oxide layer 224 is formed on top of a low-k dielectric. Layer 224 serves as a sacrificial cap layer:
US2004121265
If a document dealing with a thin functional dielectric layer also contains after-treatment aspects as defined in H01L 21/76822+, one (or more) of the latter groups should also be assigned to this document.
In this place, the following terms or expressions are used with the meaning indicated:
"Thin" layer as used herein means thin compared with the "main" interlevel or intralevel dielectric. In cases of doubt as to whether the layer is "thin" in the above sense, the criterion "functional layer" takes precedence, i.e. documents relating to layers, which may not exactly be "thin" in the above sense but serve some particular purpose except from merely isolating conductors, should also be classified here.
This place covers:
Sidewall layers that are formed by direct deposition
Sidewall liners obtained by treatment of the sidewalls of the opening.
Examples:
Sidewalls of a porous dielectric are plasma-treated in order to form a carbon sealing layer 24 on via sidewalls 22:
US2006046472
Non-metallic layer 15, e.g. silicon carbide or boron carbide is deposited in a dual damascene opening and etched back to form sidewall spacers 19:
US6284657
If the treatment has characteristics relating to any of the groups H01L 21/76822+, one (or more) of the latter groups should also be assigned.
This place covers:
Stacks of two or more thin "functional" dielectric layers, e.g. multiple etch stop layers, multiple trench liners.
Examples:
Composite adhesion/etch-stop multilayer (SiC layer 104 and SiOC layer 106) is formed; layer 104 is for improving adhesion between layers 100 and 106:
US2006110912
Multiple dielectric capping layers 616/622 and 620/624 are formed by gas cluster ion beam "infusion":
WO2006052958
In this place, the following terms or expressions are used with the meaning indicated:
"multiple" | two or more layers in direct contact with each other. |
This place covers:
Insulating film covering some part of the conductor regardless of whether the conductor is "free-standing" or an inlaid conductor.
Example:
Dielectric film 107 covers the top and part of the sidewalls of inlaid conductors 105:
US2005087871
Temporary sacrificial encapsulation layer (206 in fig. 5, 306 in fig. 6) is formed in a dual damascene opening and covering an exposed underlying conductor in order to form a protective layer for subsequent cleaning steps:
US2006292863
This place does not cover:
Dielectric sidewall liners in openings |
This place covers:
Dielectric layer stacks in which e.g. the via-level dielectric and the trench-level dielectric comprise different low-k materials or in which e.g. the structure contains a low-k etch-stop or adhesion layer separating two dielectrics of which at least one must be a low-k dielectric.
Examples:
Trench-level dielectric (spin-on low-k dielectric 24) and via-level dielectric (CVD SiOC layer 10) are different low-k materials:
US2005130407
Via-level and trench-level dielectrics (204 and 212) are made of the same low-k material, but the etch-stop layer 206 is made of a different low-k material:
US2005263876
Posts (40) are made of a non-porous low-k dielectric whereas the material filling the spaces between the posts is a porous low-k dielectric:
US2005227480
This place does not cover:
Middle etch-stop layer being a multilayer system |
This place covers:
Special measures for improving the gap-filling properties of a dielectric, wherein said "gap" is formed between conductive structures. The term "gap" is also intended to include vertical gaps.
Example:
US2005186796:
a first dielectric (213) is deposited over conductive structures 207 and etched back (the figure above shows the layer 213 after etch-back) so as to partially fill the gap and reduce its aspect ratio, a second dielectric (217) fills the remaining gap.
Attention is drawn to the following places, which may be of interest for search:
When the interconnect is also used as the conductor part of a conductor-insulator-semiconductor electrode (gate level interconnections) | |
Etching for patterning conductors |
Information peculiar to single-step processes should also be classified in the corresponding group, e.g.
- H01L 21/02041 for cleaning
- H01L 21/3213 for etching,
- H01L 21/321 for planarising, etc.
This place covers:
Thin conductive film being formed in an opening in a dielectric, e.g. barrier, adhesion, nucleation, seed or liner layers.
Example:
a barrier layer comprising e.g. Ru, Ir etc. or one of their (conducting) oxides is deposited in a trench or a dual damascene opening:
US2005206000
Attention is drawn to the following places, which may be of interest for search:
Thin films serving as seed layer for electroplating |
All documents dealing with the formation of thin conductive films in openings should be classified in this group or one of its subgroups even if the fact that the thin film is formed in an opening is not an important aspect of the disclosure under consideration.
If the deposition method of the thin functional layer is disclosed in some detail (PVD, CVD, ALD, plating etc.), the corresponding groups H01L 21/28512 - H01L 21/2885 should also be assigned.
This place covers:
At least one of the conductive thin films in the opening does not cover the bottom of the opening in its entirety, i.e. even when the thin film is removed from only a part of the bottom of the openings.
Examples:
a set of conductive barrier layers is deposited over the sidewalls of a porous dielectric and subsequently removed from the via floor by sputtering:
US6528409
Barrier layers covering only part of the sidewalls:
US2006246699
Multiple liner layers (30, 31, 33, 35) are deposited in a via of which only the outermost layers (30, 31) are removed from the via bottom:
US6555461
This place covers:
Layer combinations, i.e. arrangements of more than one layer, in the openings, e.g. combinations of particular materials other than the "standard" barrier combinations Ti/TiN, TaN/Ta or W/WN.
Superlattices comprising a multitude of layers comprising "standard" materials (Ti/TiN, TaN/Ta or W/WN), e.g. a TaN/Ta/TaN/Ta... superlattice.
Graded layers, e.g. a stack of infinitely thin multiple layers with varying composition.
Conductive thin film having a graded composition
Layer combinations formed on top of an inlaid conductor
In these cases the thin film is still considered as being formed "in an opening of a dielectric", see the further explanation and example (i) under point 1.4 below).
Examples:
43 is a TaN layer, 44 is a TaN layer having a graded content of N, 45 is an alpha-Ta layer:
US7033940
TaN/W/TaN/W/... nanolaminates, fabricated by ALD:
US2006079090
TaN/Ta/TaN/Ta stack:
US2005255691
Different barrier materials on the sidewalls and on the bottom of the via hole (α-phase Ta layer 24 is provided on the via bottom, while the sidewalls are covered with a β-phase Ta layer 29):
US 2004131878
This place covers:
Conductive thin film formed within the "main" conductor filling the opening or where the opening is filled by a sequence of thin films. It is important, however, that said thin film does not comprise the same material as the main fill material.
Examples:
Barrier layer 54s, 54d separates two layers of fill metal:
US6028362
Trench filled by alternating layers 322, 324, comprising e.g. Co and Ni:
US2006264043
This place does not cover:
Multistep plating forming a sequence of thin Cu films |
This place covers:
Conductive thin films, e.g. barrier, liner or adhesion layers, formed on top of an inlaid (i.e. damascene) conductor
Manufacture of electroless Co(Ni)WP capping layers on damascene conductors
CuSiN by siliciding and nitriding the surface of a Cu damascene conductor
Examples:
Cap layer 30 (CoWP layer) comprises multiple layers having periodic variations in the concentration of chemical elements:
WO2006020566
Electromigration barrier formed by depositing a metal layer 11, diffusing the metal into the underlying conductor and removing the remainder of layer 11:
WO03052798
This place covers:
Thin functional conductive films covering interconnects not formed in an opening of a dielectric, e.g. on subtractive metal lines, e.g. a Ti/TiN adhesion/barrier stack on Al wiring.
Example:
Formation of a TiN layer (141) on an Al conductor (110). The method of fabrication avoids the formation of an unintentional Ti layer (140):
US2006099800
This place does not cover:
Barrier or adhesion layers being positioned on top of the main fill metal, e.g. thin films formed on top of inlaid conductors |
This place covers:
Barrier, adhesion or other liner layers on the sidewalls or on top and on the sidewalls of a freestanding, e.g. subtractive, interconnect.
Examples:
US2005230262
US 2006180920
This place covers:
Conductive thin film treated in some way after it has been deposited. The resulting film must still be a conductive film.
Attention is drawn to the following places, which may be of interest for search:
Methods of formation of barrier layers other than PVD, CVD or deposition from a liquids | |
Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances |
This place covers:
All methods introducing a new chemical element into the thin film, e.g. the reaction of the layer with the semiconductor substrate to form a silicide.
Example:
a titanium layer (black circles in the figure below) is deposited on the sidewalls of a dielectric layer, the Ti layer reacts with the oxygen (cross-hatched circles) contained in the dielectric during a later thermal step:
US2006214305
This place covers:
Contacting the thin film with a gas or a plasma so as to modify the composition of the layer, e.g. plasma nitriding.
Examples:
Refractive metal cap layer 303 is plasma nitrided to form a refractive metal nitride layer 305:
US6844258
Ru barrier layer 650b and a seed layer 666 are deposited in a trench, the seed layer is partially oxidized by exposing it to an oxidizing ambient. The oxide layer 667 serves as a protective layer and is dissolved when contacted with a plating bath:
US2006223310
This place covers:
Introducing alloying elements, i.e. metallic elements, by diffusion into or reaction with pre-fabricated conductive thin film into.
Examples:
A barrier layer, an adhesion layer (Ti), a seed layer and a Cu fill are formed in a dual damascene opening; after planarisation, a thermal treatment is carried out to react the adhesion layer with the Cu thereby forming an interface layer having a graded Cu content:
US2006154465
Conductive thin film 608 (Ca film) is formed over an inlaid Cu line (601) and heat treatment is performed to diffuse Cu from the line into the Ca layer thereby forming a CuCa capping layer (606). The unreacted material of layer 608 is subsequently removed:
US6566262
This place does not cover:
Layers itself being fabricated by the diffusion of alloying elements |
Diffusion is a bi-directional process, i.e. there can be cases where it cannot be unambiguously determined whether the final layer is the result of diffusing elements into the layer (which would constitute an example for the present class) or if the final film is the result of diffusing elements out of an original thin film, e.g. into the bulk conductor (this would pertain to H01L 21/76867, see the examples given there). In such cases both classes H01L 21/76858 and H01L 21/76867 should be assigned.
This place covers:
Implantation methods, i.e. methods allowing for precise control of the energy of the implanted ions as well as of the implantation depth.
Examples:
Sn ions are implanted into barrier layer (440) in order to render the barrier amorphous and to introduce dopants having favourable electromigration properties:
US6835655
the surface of a CoWP capping layer (34) is nitrided by N2 ion implantation:
US2006175708
Attention is drawn to the following places, which may be of interest for search:
Implantation in semiconductors | |
implantation in insulating layers |
This place covers:
Methods for removing contaminants, e.g. oxides, from thin functional conductive films.
Methods for transforming their grain structure.
Example:
Oxides and other contaminants of a Cu seed layer (144) are removed by a wet-chemical treatment:
US2005245072
This place covers:
Contacting the film with plasmas or particles, e.g. high energy photons, while not introducing a new element into the film, e.g. treatment by UV irradiation for the removal of oxides.
Examples:
Barrier layer (Ti/TiN layer 118) is plasma treated to roughen the surface of the layer in the region 120. As a result, the number of nucleation sites is increased which slows down the growth of W layer 124:
US2005014358
Barrier layer (52) is subjected to a two-step redistribution process, i.e. overhanging portions (60) are removed and redistributed to reinforce sidewall regions (32, 34) where the PVD barrier is not thick enough. In a first step, this redistribution is achieved by bombardment with Ar and Ta ions with simultaneous deposition of Ta, in the second step, only Ar is used for material redistribution:
US2005260851
This place covers:
Thermal treatment of thin functional films not introducing additional elements into the film, e.g. plasma annealing
Examples:
a Cu seed layer (228) is locally heat treated in order to induce grain growth in the seed layer:
US2006223311
a Ru barrier/seed layer (108) is annealed after deposition to remove oxides or other contaminants prior to plating:
US2005274622
This place does not cover:
Film stacks, e.g. Ti/TiN and W, TaN/Ta and Cu, subjected to annealing after filling the contact hole |
Attention is drawn to the following places, which may be of interest for search:
Seed layers treated by an annealing step |
"Plasma annealing" should be classified here and in H01L 21/76862.
Note that for assigning this group symbol it is important that it is the thin film per se which is subjected to the thermal treatment. Thermal treatment of the main conductor is classified in H01L 21/76838 or, if the main conductor is formed in an opening in a dielectric, in H01L 21/76883.
Thermal treatments for driving an alloying element into the thin metal film are not classified here but in H01L 21/76858.
This place covers:
Removal of overhanging or "necking" portions of conductive thin films at the upper regions of via holes, or all cases where sputter etching and sputter deposition are carried out simultaneously.
Examples:
Seed layer (10) is removed so as to provide a base layer for selective filling of the dual damascene trench;
US2006094220
Overhanging portions of a barrier layer 308 and/or a Cu seed layer (310) are removed and redistributed by gas cluster ion beam (GCIB) processing:
WO2004044954
Capping layer (106) on an underlying conductor (105) is partially etched off by sputtering; the sputtered material of barrier (106) is redistributed on the via sidewalls to form a bottomless first barrier:
US2006264030
This place does not cover:
Forming a bottomless barrier |
Attention is drawn to the following places, which may be of interest for search:
Selective removal of a seed layer for electroplating |
This place covers:
Formation of a functional conductive thin film, e.g. barrier, liner, adhesion or seed layers, by diffusing alloying elements such that they segregate at the surfaces of a conductor.
Diffusion of material from an initial thin film into a surface portion of the conductor, optionally followed by the removal of said initial thin film.
Examples:
A layer stack comprising a first barrier layer (6) and a metal layer (Hf, Zr, or Ti) suitable for forming an intermetallic compound with Cu is deposited in a dual damascene trench. A heat treatment forms layer (10b) comprising a compound of Cu and Hf, Zr, or Ti, while at the same time another compound layer (10a) is formed within the main conductor by diffusion of Hf, Zr, or Ti:
EP0881673
Barrier layer sections 6a, 6b are formed by diffusing material of the barrier layer 510 into the porous dielectric 2:
US2006154464
Al from Al layer 22 is diffused into inlaid Cu in order to form a CuAl electromigration barrier 12; the remaining unreacted Al layer is removed:
US2004207093
Attention is drawn to the following places, which may be of interest for search:
PVD | |
CVD | |
Deposition from liquids |
This place covers:
Methods specially adapted for either forming a discontinuous thin functional conductive film or for treating a discontinuous film so as to make it continuous, e.g. repair of seed layers.
Example:
Ti layer 126 is formed only incompletely on the sidewalls of contact hole 124; the TiSix layer 132 repairs the discontinuities in layer 126:
US2005233577
This place covers:
Thin conductive films formed in conjunction with the manufacture of contacts for capacitors
Example:
Formation of the barrier layer (13e):
US5699291
Attention is drawn to the following places, which may be of interest for search:
Capacitor electrodes themselves |
This group is intended to sort of "filter out" all documents related to capacitor contacts providing a solution to the very specific problems encountered during the manufacture of capacitors. The groups H01L 21/76843, H01L 21/7685, H01L 21/76853, H01L 21/76867 should also be given, provided "interesting" aspects which might also be of importance in the context of more conventional barriers are disclosed.
This place covers:
Formation of seed, wetting, nucleation or catalyst layers.
Whenever any one of the structural aspects covered by H01L 21/76843 or H01L 21/7685 applies the corresponding group symbol should be given in addition to the seed layer groups with the only exception that "layer combinations", i.e. structures containing stacks of seed layers, are not classified in H01L 21/76846.
Whenever any one of the after-treatment or manufacturing aspects covered by H01L 21/76853, H01L 21/76867 or H01L 21/76868 applies the corresponding group should also be given.
Documents related to seed layers are classified in the head group H01L 21/76871 only if it is not clear which deposition method is envisaged or if the corresponding seed layer is suitable for all three of the deposition methods listed below.
This place covers:
Seed layers specifically adapted for facilitating the deposition of conductive films by electroless plating
Examples:
Formation of a Pd catalyst layer for electroless CoWP deposition on top of an inlaid Cu interconnect:
EP1496542
Formation of a Pd catalyst layer for electroless Cu plating (The Pd seed is formed by plasma-immersion ion implantation into a TaN barrier layer):
US2006040065
This place covers:
Methods for selectively filling of vias or trenches in a dielectric layer with a conductive material, e.g. bottom up fill of a damascene opening not leading to a metal overburden on the field regions surrounding the opening.
Attention is drawn to the following places, which may be of interest for search:
Plating on semiconductors in general |
If the deposition method is disclosed in some detail and includes one or more of PVD, CVD, ALD or liquid deposition, the corresponding group symbol H01L 21/2855, H01L 21/28556, H01L 21/28562, H01L 21/288 or H01L 21/2885 should also be assigned.
Attention is drawn to the following places, which may be of interest for search:
Lift-off of resists | |
Lift-off of other layers |
This place covers:
After-treatment for improving or modifying the result of the process of filling an opening in a dielectric layer, e.g. a via hole or a damascene trench, with conductive material.Thermal treatments before or after polishing, e.g. to induce grain growth, removal of metal residues, plasma cleaning
This place does not cover:
Plasma treatment specifically adapted for forming a thin layer on the surface of the conductor | |
Reflowing the conductor or applying pressure so as to better fill the opening | |
Oxidation or otherwise rendering (parts of) the conductor non-conductive |
The after-treatment is part of a multi-step process for forming a conductor in an opening in a dielectric. Cleaning of conductors per se is classified in H01L 21/02068 - H01L 21/02074.
This place covers:
Conductors formed by through-mask plating
This place does not cover:
Formation of pillars, studs, bumps etc. for connecting the semiconductor substrate to other substrates |
Attention is drawn to the following places, which may be of interest for search:
Doping |
This place covers:
Methods in which the properties of an otherwise completed conductive member of an interconnect, i.e. the main conductor, are modified, e.g. by introducing dopants into the conductor, alloying the main conductor with another metal
This place does not cover:
Smoothing; Planarisation | |
Modification of thin functional conductive films such as barrier, adhesion, liner or seed layers | |
Processes for fabricating fuses and anti-fuses are classified with the fuses and anti-fuses in |
Attention is drawn to the following places, which may be of interest for search:
Self aligned silicidation on field effect transistors |
This place covers:
Establishing a conductive path extending through the substrate from the top surface to the bottom surface, e.g. through-silicon vias
Example
EP2426710A2
This place covers:
In the group range H01L 21/77 - H01L 21/86 are classified processes for integration a plurality of solid state components formed in or on a common substrate, with
- H01L 21/77 and H01L 2021/775 covering the manufacturing of devices consisting of a plurality of solid state components formed or assembles ON a common substrate, e.g. integrated circuits formed of a plurality of chips on a host substrate, and
- H01L 21/82 - H01L 21/86 covering the manufacturing of devices consisting of a plurality of solid state components formed IN a common substrate, e.g. integrated circuits formed of a single chip, and
- H01L 21/78 - H01L 21/786 being reserved to processes for the division of a substrate into a plurality of individual devices.
This place does not cover:
Integration processes for the manufacture of devices of the type classified in H01L 27/14, H01L 27/15, H10N 19/00, H10N 39/00, H10N 59/00, H10N 79/00, H10N 89/00, H10K 19/00, H10K 39/00, H10K 59/00 and H10K 65/00 | H01L 27/14, H01L 27/15, H10N 19/00, H10N 39/00, H10N 59/00, H10N 79/00, H10N 89/00, H10K 19/00, H10K 39/00, H10K 59/00 and H10K 65/00 |
Multistep methods for manufacturing random access memories [RAM] structures |
Attention is drawn to the following places, which may be of interest for search:
Devices comprising components using organic materials as active part | |
Devices sensitive to light | |
Devices adapted to emit light | |
Devices comprising components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier | |
Components specially adapted for sensing light, electromagnetic or corpuscular radiation, or specially adapted for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation | |
Devices with components specially adapted for light emission | |
Devices comprising thermo-electric components | |
Devices comprising piezoelectric, electro-strictive or magneto-strictive components | |
Devices comprising magneto-galvanic devices, e.g. Hall effect devices, MRAM | |
Devices comprising superconductive components | |
Devices including bulk negative resistance effects, like Gunn devices |
Integration processes for the manufacture of devices of the type classified in H01L 27/14 , H01L 27/15, H10N 19/00, H10N 39/00, H10N 59/00, H10N 79/00, H10N 89/00, H10K 19/00, H10K 39/00, H10K 59/00 and H10K 65/00 are not classified in this group and its sub-groups. Instead, as they are peculiar to said devices, they are classified together with the devices.
Multistep processes for manufacturing memory structures in general using field effect technology are covered by H10B 99/00 ;
Multistep processes for manufacturing dynamic random access memory structures are covered by H10B 12/01;
Multistep processes for manufacturing static random access memory structures are covered by H10B 10/00;
Multistep processes for manufacturing read-only memory structures are covered by H10B 20/00;
Multistep processes for manufacturing electrically programmable read-only memory structures are covered by H10B 69/00
This place covers:
Multistep processes for the fabrication of devices comprising a plurality of TFT on an insulating substrate, e.g. for driving LCD displays.
Attention is drawn to the following places, which may be of interest for search:
Recrystallization of amorphous or polycrystalline semiconductor layers | |
LCD displays per se |
If a single step among the multistep sequence appears to be particular it should be given a group symbol in the corresponding single step group.
This place covers:
Multistep processes for singulating devices.
This place does not cover:
Devices sensitive to light | |
Light emitting devices |
Attention is drawn to the following places, which may be of interest for search:
Single mechanical steps like cutting semiconductors | |
Laser dicing | |
Single mechanical steps of grinding, lapping and polishing in general | |
Fine working of crystals, e.g. semiconductors |
This place covers:
Separation of layers comprising active devices from the substrate, e.g. splitting after Epitaxial Lift-Off
In this place, the following terms or expressions are used with the meaning indicated:
ELO | Epitaxial Lift-Off |
This place covers:
Division of the substrate into individual components where the process is peculiar to the insulating body or substrate.
This place covers:
Multistep processes of integration of devices consisting of a plurality of solid state components formed IN a common substrate, i.e. integrated circuits formed of a single chip.
Attention is drawn to the following places, which may be of interest for search:
Integrated circuits |
Within the group range H01L 21/82 - H01L 21/86, a particular aspect linked to the fabrication of several components must appear. When the multistep processes do not show specific aspects linked to the fabrication of several components, e.g. when the integrated circuit is only constituted of a multiplicity of an identical device without further specification, then the process may only be classified with the multistep process for fabrication of this device, e.g. in H01L 29/00. Thus, the mere mention of the fabrication of an integrated circuit, when the fabrication of a device is disclosed, does not require a group symbol in H01L 21/82.
When the fabrication process is specified or peculiar to an electric circuit, only a group symbol in H01L 27/00 is given.
Combination of field effect devices and passive devices is classified in H01L 27/00.
This place covers:
Three dimensional integrated circuits in a common substrate
This place does not cover:
The fabrication of three-dimensional integrated devices by assembling different devices or substrates |
Attention is drawn to the following places, which may be of interest for search:
With a current flow parallel to the substrate surface |
Attention is drawn to the following places, which may be of interest for search:
With a current flow parallel to the substrate surface |
This place covers:
Application of testing and/or measuring procedures during the manufacturing processes of devices as defined under H01L 21/00, with the aim to
- detect defects, repair defects, sort defective devices / wafers
- control the semiconductor device fabrication process,
- with or without corrective action on the process,
which are specific to semiconductor device fabrication, e.g. end point determination.
Covers the measuring of a single parameter or variable
Processes which are not specific to semiconductor device fabrication or processes, where the semiconductor devices are included in a larger system, are typically not classified in H01L 22/00, but are classified in the relevant place for the processes or testing in general, e.g. G01N or G01R.
Attention is drawn to the following places, which may be of interest for search:
Detecting parts, counting parts, handling parts | |
Marks on wafers, test patterns on wafers | |
Means for detecting end-point in lapping or polishing machines | |
Analysing materials by determining their chemical or physical properties | |
Optical characterization of semiconductors | |
Measuring electrical or magnetic variables | |
Multiple probes for testing, e.g. probe cards | |
Testing of individual devices, including on wafers, after manufacture | |
Testing of integrated circuits, including on wafers, after manufacture | |
Contactless testing of integrated circuits | |
Testing and controlling photoresist and lithographic patterns | |
Multiple probes for testing, e.g. probe cards | |
Inspection of images, flaw detection | |
Testing storing means, like memories, including repair | |
Measuring and control of plasma parameters | |
Controlling gas-filled discharge tubes, e.g. plasma machines, by information coming from substrate; end-point detection | |
Testing of photovoltaic systems |
This place covers:
Methods for measurement of structural or electrical parameters as part of the device manufacturing process.
Measuring as part of the manufacturing process; the parameter may be for example the thickness of layers, refractive index of layers, line width, warp of wafers, bond strength, defect concentration, metallurgic parameters, diffusion depth, dopant concentration.
Measurement of parameters wherein the fabrication of semiconductor devices is not particularly relevant to the invention, or wherein the measurement of the parameter could equally be applied to the fabrication of other products than semiconductor products are typically not classified.
This place does not cover:
Procedures, i.e. sequence of activities consisting of a plurality of measurement and correction, marking or sorting steps |
Attention is drawn to the following places, which may be of interest for search:
Measurement of parameters which is not part of the device fabrication processMeasurement of parameters wherein the fabrication of semiconductor devices is not particularly relevant to the invention, and wherein the measurement of the parameter could equally be applied to the fabrication of other products than semiconductor devices | |
Burn-in |
In H01L 22/00, the method for measuring a parameter is classified in H01L 22/20 as soon as it is part of a testing or controlling procedure.
Attention is drawn to the following places, which may be of interest for search:
Electrical measurement of diffusion regions |
This place covers:
Multi-step processes comprising at least a measuring step followed by a correcting, marking or sorting step.
This place does not cover:
Semiconductor factory control |
Attention is drawn to the following places, which may be of interest for search:
Procedures applied to semiconductor fabrication but wherein the fabrication of semiconductor devices is not particularly relevant to the invention and wherein the procedure could equally be applied to the fabrication of products other than semiconductor devices are typically classified in |
Attention is drawn to the following places, which may be of interest for search:
Voltage contrast |
Attention is drawn to the following places, which may be of interest for search:
methods for plasma etching end point control |
End point process detection, when it is exclusively based on the use of a machine which has been designed for that purpose, need not to be classified in H01L 22/00.
Attention is drawn to the following places, which may be of interest for search:
Process control influencing process steps in general, e.g. CD correction by etch or diffusion | |
Switching, multiplexing, gating devices | |
Process control with lithography, e.g. dose control | |
Structures for alignment control by optical means |
This place covers:
- Details of semiconductor or other solid state devices including
- Structural arrangements for protection of semiconductor or other solid state devices against mechanical damage or moisture
- Containers or seals
- Mountings
- Fillings or auxiliary members in containers of encapsulations
- Encapsulations
- Holders for supporting the complete device in operation
- Arrangements for cooling, heating, ventilating or temperature compensation
- Arrangements for conducting electric current to or from the solid state body in operation
- Arrangements for conducting electric current within the solid state body in operation
- Marks applied to semiconductor or other solid state devices
- Protection against radiation of semiconductor or other solid state devices
- Structural electrical arrangements for semiconductor or other solid state devices not otherwise provided for
This place does not cover:
Arrangements for connecting or disconnecting semiconductor or solid-state bodies, and methods related thereto | |
Assemblies consisting of a plurality of individual semiconductor or other solid state devices | |
Details of semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier | |
Details peculiar to semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation | |
Details peculiar to semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission | |
Microstructural devices or systems, e.g. micromechanical devices | |
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part | |
Details peculiar to thermo-electric devices comprising a junction of dissimilar materials | |
Details peculiar to thermoelectric devices without a junction of dissimilar materials | |
Details peculiar to piezoelectric devices; electrostrictive devices; magnetostrictive devices | |
Details peculiar to devices using galvano-magnetic or similar magnetic effects | |
Details peculiar to devices using superconductivity | |
Details peculiar to solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier | |
Details peculiar to bulk negative resistance effect devices | |
Details peculiar to solid state devices not provided for in groups H01L 27/00 – H01L 33/00, H10B 10/00 – H10B 53/00, H10B 69/00, H10K 10/00, H10K 30/00, H10K 50/00, H10K 71/00, H10K 77/00, H10K 85/00 and H10K 99/00 and not provided for in any other subclass |
Attention is drawn to the following places, which may be of interest for search:
Shape of semiconductor body | |
Device electrodes | |
Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating | |
Laser working of semiconductors | |
Rods, electrodes, materials, or media, for use in soldering, welding, or cutting | |
Injection moulding of electrical components | |
Optical interconnections, e.g. light guides | |
Photolithography | |
Record carriers for use with machines and containing semiconductor elements (credit cards, id cards) | |
Structure or manufacture of flux-sensitive heads using magneto-resistive devices or effects | |
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor | |
Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current connectors or for joining electric conductors (soldering / welding) |
The use of Indexing Codes of the indexing scheme H01L 23/00 - H01L 23/66 is mandatory for additional information.
In this place, the following terms or expressions are used with the meaning indicated:
Parts | All structural units which are included in a complete device |
Container | Enclosure forming part of the complete device and is essentially a solid construction in which the body of the device is placed, or which is formed around the body without forming an intimate layer thereon. Generally comprises a base, a lid and leads for electrical connection |
Encapsulation | Enclosure which consists of one or more layers formed on the body and in intimate contact therewith |
This place does not cover:
Mountings | |
Arrangements for cooling, heating, ventilating or temperature compensation | |
Arrangements for conducting electric current to or from the solid state body in operation | |
Protection against radiation | |
High-frequency adaptations | |
Containers for imagers, i.e. semiconductor components sensitive to radiation |
Attention is drawn to the following places, which may be of interest for search:
Housings for MEMs | |
Housings for sensors in general | |
Housings for acceleration sensors | |
Housings for computers | |
Housings for record carriers, e.g. memory cards | |
Housings for memories |
This place does not cover:
The leads being parallel to the base |
Attention is drawn to the following places, which may be of interest for search:
Chip carriers per se | |
Multi-chip modules in general | |
Printed circuit boards |
Attention is drawn to the following places, which may be of interest for search:
Semiconductor conductive substrates |
This place covers:
Additional parts and fillings within container or encapsulation, e.g. stiffeners, spacing layers.
This place does not cover:
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling | |
Protection against radiation |
This place does not cover:
Materials for absorbing or reacting with moisture or other undesired substances |
This place does not cover:
Materials for absorbing or reacting with moisture or other undesired substances |
This place does not cover:
Materials for absorbing or reacting with moisture or other undesired substances | |
Double encapsulation or coating and encapsulation |
This place does not cover:
Protection against radiation |
Attention is drawn to the following places, which may be of interest for search:
Insulating layers for contacts or interconnections |
This place does not cover:
Organo-silicon compounds |
Attention is drawn to the following places, which may be of interest for search:
Mask layer used as insulation layer |
This place does not cover:
Fillings of grooves in memory cells (e.g. capacitors of RAMs) |
This place does not cover:
Mountings or securing means for detachable cooling or heating arrangements |
Attention is drawn to the following places, which may be of interest for search:
Thermal treatment apparatus | |
Temperature control of computers | |
Thermal control of PCBs |
This place does not cover:
Encapsulations | |
Mountings or securing means for detachable cooling or heating arrangements | |
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling | |
The complete device being wholly immersed in a fluid other than air | |
Involving the transfer of heat by flowing fluids |
Attention is drawn to the following places, which may be of interest for search:
Arrangements for heating |
This place does not cover:
Cooling arrangements using the Peltier effect | |
Mountings or securing means for detachable cooling or heating arrangements | |
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling | |
Cooling arrangements with the complete device being wholly immersed in a fluid other than air | |
Cooling arrangements involving the transfer of heat by flowing fluids |
This place does not cover:
Heat sinks being part of lead-frames |
This place does not cover:
Cooling facilitated by selection of materials: diamonds | |
Cooling facilitated by selection of materials: having a heterogeneous or anisotropic structure | |
Cooling facilitated by selection of materials: laminates or multilayers | |
Cooling facilitated by selection of materials: organic materials with or without a thermoconductive filler | |
Cooling facilitated by selection of materials: semiconductor materials |
Attention is drawn to the following places, which may be of interest for search:
Diamond per se |
This place does not cover:
Cooling facilitated by selection of materials: diamonds | |
Cooling facilitated by selection of materials: organic materials with or without a thermoconductive filler |
This place does not cover:
Cooling facilitated by selection of materials: diamonds | |
Cooling facilitated by selection of materials: having a heterogeneous or anisotropic structure | |
Cooling facilitated by selection of materials: laminates or multilayers | |
Cooling facilitated by selection of materials: organic materials with or without a thermoconductive filler | |
Cooling facilitated by selection of materials: semiconductor materials |
Attention is drawn to the following places, which may be of interest for search:
Assemblies consisting of a plurality of individual semiconductor or other solid-state bodies |
Attention is drawn to the following places, which may be of interest for search:
Heating | |
Selection of materials for the device |
Attention is drawn to the following places, which may be of interest for search:
Cooling by liquefied gas |
This place does not cover:
Leadframes specifically adapted to facilitate heat dissipation |
This place does not cover:
Cooling by change of state |
This place does not cover:
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling | |
Cooling arrangements with the complete device being wholly immersed in a fluid other than air |
This place does not cover:
Cooling involving the transfer of heat by flowing liquids |
This place does not cover:
Auxiliary members in containers: bellows | |
Auxiliary members in containers: pistons |
This place does not cover:
Auxiliary members in containers: in combination with jet impingement |
Attention is drawn to the following places, which may be of interest for search:
Arrangements for connecting or disconnecting semiconductor or other solid-state bodies, and methods related thereto | |
Terminals, leads in general |
This place does not cover:
Electrodes of semiconductor devices |
This place does not cover:
Lead-in layers inseparably applied to the semiconductor body: bridge structures with air gap | |
Lead-in layers inseparably applied to the semiconductor body: beam leads | |
Lead-in layers inseparably applied to the semiconductor body: pads with extended contours | |
Lead-in layers inseparably applied to the semiconductor body: for devices consisting of semiconductor layers on insulating or semi-insulating substrates | |
Materials | |
Bond pads | |
Bump connectors |
This place does not cover:
Bump connectors |
This place does not cover:
Leads on insulating substrates |
Attention is drawn to the following places, which may be of interest for search:
Interconnections between components using lead-frames |
This place does not cover:
Lead-frames with additional leads being a wiring board |
This place does not cover:
Lead-frames: geometry for devices being provided for in H01L 29/00 |
This place does not cover:
Lead-frames: geometry for devices being provided for in H01L 29/00 |
This place does not cover:
Thin flexible metallic tape with or without a film carrier provided in the context of subject-matter covered by groups H01L 23/49503 - H01L 23/49568 and H01L 23/49575 - H01L 23/49579 | H01L 23/49503 - H01L 23/49568 and; H01L 23/49575 - H01L 23/49579 |
Attention is drawn to the following places, which may be of interest for search:
Shape of the substrate |
This place does not cover:
Leads on insulating substrates: via connections through the substrates |
Attention is drawn to the following places, which may be of interest for search:
Multilayer metallisation on monolayer substrate |
This place does not cover:
Leads on insulating substrates: multilayer substrates | |
Leads on insulating substrates: consisting of a plurality of insulating substrates | |
Leads on insulating substrates: flexible insulating substrates | |
Leads on insulating substrates: lead-frames fixed on or encapsulated in insulating substrates |
This place does not cover:
Lead-frames consisting of thin flexible metallic tape with or without a film carrier | |
Leads on insulating substrates: for flat-cards, e.g. credit cards |
Attention is drawn to the following places, which may be of interest for search:
Cards per se |
This place does not cover:
Leads on insulating substrates: the leads being also applied on the sidewalls or the bottom of the substrate | |
Leads on insulating substrates: flexible insulating substrates |
Attention is drawn to the following places, which may be of interest for search:
Materials of the substrates | |
Materials of the lead-frames | |
Conductive materials for PCBs | H05K/09D |
Attention is drawn to the following places, which may be of interest for search:
Superconducting fullerenes |
Attention is drawn to the following places, which may be of interest for search:
For printed circuits |
This place does not cover:
Arrangements for conducting electric current to or from the solid state body in operation: lead-in layers inseparably applied to the semiconductor body | |
Leads on insulating substrates |
Attention is drawn to the following places, which may be of interest for search:
Other capacitive arrangements |
Attention is drawn to the following places, which may be of interest for search:
Other inductive arrangements |
Attention is drawn to the following places, which may be of interest for search:
Other resistive arrangements |
This place does not cover:
Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate: geometrical layout of the components |
Attention is drawn to the following places, which may be of interest for search:
Algorithms, e.g. computer aided design of layouts of integrated circuits |
This place does not cover:
Arrangements for conducting electric current within the device in operation from one component to another: containing superconducting materials |
Attention is drawn to the following places, which may be of interest for search:
Nanosized carbon materials per se | |
Superconducting fullerenes |
Attention is drawn to the following places, which may be of interest for search:
Internal lead connections |
This place does not cover:
Printed circuits; casings or constructional details of electric apparatus; manufacture of assemblages of electrical components |
Attention is drawn to the following places, which may be of interest for search:
Manufacture or treatment | |
Mountings per se | |
Materials |
This place does not cover:
Interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates: assembly of a plurality of insulating substrates |
Attention is drawn to the following places, which may be of interest for search:
Multilayer metallisation on monolayer substrates |
This place does not cover:
Interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates: multilayer substrates | |
Interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates: assembly of a plurality of insulating substrates |
Attention is drawn to the following places, which may be of interest for search:
Pins attached to insulating substrates |
This place does not cover:
Interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates: for flat cards, e.g. credit cards |
Attention is drawn to the following places, which may be of interest for search:
Cards per se |
This place covers:
Marks for identification purposes, including electrical structures used to generate identification information for electrical read out.
Typical views of marks of this type:
Attention is drawn to the following places, which may be of interest for search:
Marking devices, scribers | |
Marking methods | |
Marks used for overlay monitoring in photolithography | |
Alignment marks used in photolithographic machines |
This place covers:
Electromagnetic shielding arrangements; RF interference suppression.
This place does not cover:
Lead-frames: battery in combination with a lead-frame | |
Lead-frames: oscillators in combination with a lead-frame |
This place covers:
Active and passive measures to prevent or detect tampering; reverse engineering protection structures; seal rings, protection against delamination of layers during dicing
This place does not cover:
Protection against electrostatic charges or discharges | |
Protection against overvoltage | |
Impedance arrangements | |
High-frequency adaptations |
Attention is drawn to the following places, which may be of interest for search:
Secure housings for data carriers (memories) | |
Protective means for data carriers (memories) |
Attention is drawn to the following places, which may be of interest for search:
Protection against electrostatic discharge (ESD) provided in a semiconductor body | |
Faraday shields in general |
This place does not cover:
Lead-frames: capacitor integral with or on the lead-frame | |
Impedance arrangements: inductive arrangements | |
Impedance arrangements: resistive arrangements | |
High-frequency adaptations |
Attention is drawn to the following places, which may be of interest for search:
Capacitive effects between wiring layers on the semiconductor body |
This place does not cover:
Impedance arrangements: resistive arrangements | |
High-frequency adaptations |
Attention is drawn to the following places, which may be of interest for search:
Inductors formed within interconnection layers |
This place does not cover:
Protection against overvoltage | |
High-frequency adaptations |
This place covers:
Examples of first level interconnects
1 = H01L 24/10 and subgroups,
2 = H01L 24/26 and subgroups,
3 = H01L 24/26 and subgroups,
4 = H01L 24/42 and subgroups
This place does not cover:
Manufacture or treatment of parts | |
Assemblies of semiconductor devices | |
Applying interconnections to be used for carrying current between separate components within a device | |
Containers or seals | |
Mountings | |
Arrangements for cooling, heating, ventilating or temperature compensation | |
Arrangements for conducting electric current | H01L 23/48 - H01L 23/50 and H01L 23/52 - H01L 23/5389 |
Structural electrical arrangements | |
Assemblies consisting of a plurality of individual semiconductor or other solid state devices | |
Details of semiconductor bodies or electrodes of semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier | |
Details peculiar to semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation | |
Details peculiar to semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission | |
Printed circuits | |
Apparatus or manufacturing processes for printed circuits | |
Details peculiar to solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part | |
Details peculiar to thermoelectric devices comprising a junction of dissimilar materials | |
Details peculiar to thermoelectric devices without a junction of dissimilar materials or of thermomagnetic devices | |
Details peculiar to piezoelectric, electrostrictive, magnetostrictive devices in general | |
Details peculiar to devices using galvano-magnetic or similar magnetic effects | |
Details peculiar to devices using superconductivity | |
Details peculiar to solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier or of Ovshinsky-effect devices | |
Details peculiar to bulk negative resistance effect devices | |
Details peculiar to solid state devices not provided for in groups H01L 27/00 – H01L 33/00, H10B 10/00 – H10B 53/00, H10B 69/00, H10K 10/00, H10K 30/00, H10K 50/00, H10K 71/00, H10K 77/00, H10K 85/00 and H10K 99/00 and not provided for in any other subclass |
The use of Indexing Codes of the indexing schemes H01L 24/00 and subgroups, H01L 2224/00 and subgroups and H01L 2924/00 and subgroups is mandatory.
This place covers:
Attention is drawn to the following places, which may be of interest for search:
Bonding areas on insulating substrates, e.g. chip carriers |
Attention is drawn to the following places, which may be of interest for search:
Physical circuit design |
In this place, the following terms or expressions are used with the meaning indicated:
Attention is drawn to the following places, which may be of interest for search:
Bumps on insulating substrates, e.g. chip carriers |
This place covers:
Attention is drawn to the following places, which may be of interest for search:
Manufacturing methods for bumps on insulating substrates | |
Inks, e.g. metallic inks |
This place covers:
Attention is drawn to the following places, which may be of interest for search:
Interconnection structure between a plurality of semiconductor chips |
This place covers:
Attention is drawn to the following places, which may be of interest for search:
metal powder in organic matrix |
Attention is drawn to the following places, which may be of interest for search:
Applying fluids in general | |
Applying adhesive films using preforms |
This place covers:
Attention is drawn to the following places, which may be of interest for search:
Thin flexible metallic tape with or without a film carrier | |
Flexible insulating substrates |
Attention is drawn to the following places, which may be of interest for search:
Holders for supporting the complete device in operation H01L 23/32 |
This place covers:
This place covers:
Attention is drawn to the following places, which may be of interest for search:
Interconnection structure between a plurality of semiconductor chips |
Attention is drawn to the following places, which may be of interest for search:
Wire bonding in general |
This place covers:
This place does not cover:
Devices consisting of a plurality of solid state components formed in or on a common substrate | |
Photovoltaic modules or arrays of photovoltaic cells | |
Panels or arrays of photo electrochemical cells |
Attention is drawn to the following places, which may be of interest for search:
Assembling semiconductor devices using processes or apparatus not provided for in a single one of the subgroups | |
Assemblies of semiconductor devices on lead-frames | |
Leads on insulating substrates (chip carriers) | |
Interconnection structures for a plurality of bare semiconductor chips provided on or in an insulating substrate | |
Arrangements for connecting or disconnecting semiconductor or solid-state bodies; methods related thereto | |
Integrated photodetecting devices on a substrate | |
Tandem solar cells, meaning monolithically integrated solar cells with different wavelengths sensibilities deposited on one another by coating processes | |
Light sensitive devices structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, and electrically or optically coupled thereto (e.g. opto-couplers) | |
Couplings of light guides with optoelectronic elements | |
Static Stores | |
Generators using solar cells or photovoltaic modules | |
Details of complete circuit assemblies provided for in another subclass, e.g. details of television receivers, see the relevant subclass, e.g. H04N | |
Details of assemblies of electrical components in general | |
Organic light emitting devices [OLEDs] | |
Integration of organic light emitting devices (OLEDs), e.g. OLED displays |
The classification of additional information is mandatory in this main group.
In this place, the following terms or expressions are used with the meaning indicated:
Assembly of a Device | The "assembly" of a device is the building up of the device from its component constructional units and includes the provision of fillings in containers. |
This place covers:
- "package in package" devices
- assemblies of rectifier diodes
This place covers:
Arrays of photodetectors disposed next to one another on a common substrate.
This place does not cover:
Multicolour imagers having a stacked pixel-element structure | |
Multispectral infrared imagers, having a stacked pixel-element structure | |
Assemblies of thin film solar cells |
Attention is drawn to the following places, which may be of interest for search:
Mechanically stacked solar cells |
In this place, the following terms or expressions are used with the meaning indicated:
Disposed | means that photodetectors already manufactured are individually placed on the common substrate, as opposed to "integrated" which means the devices are all formed on or in said substrate during the same process |
This place covers:
Photodetectors mechanically stacked on one another:
Attention is drawn to the following places, which may be of interest for search:
Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers |
This place covers:
Hybrid modules of active and passive components
This place does not cover:
Interconnections for hybrid circuits |
This place covers:
Arrangement of memory and logic chips
Arrangement of diode and IGBT
This place does not cover:
Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate and controlled by radiation |
This place covers:
Processes to fabricate devices formed of an assembly of a multiplicity of components on a host substrate.
This place does not cover:
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L 21/06 - H01L 21/326 | |
Assemblies consisting of a plurality of individual semiconductor or other solid state devices |
This place covers:
Semiconductor devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate, i. e. integrated circuits.
Examples of integrated circuits are: memory arrays (SRAM, DRAM, MRAM, ROM, PROM, EPROM, EEPROM), image sensors (CMOS-type image sensors, CCD-type image sensors), organic and inorganic light emitting diode (LED, OLED) displays, logic integrated circuits, switching integrated circuits, arrangements of active or passive semiconducting components in or on a common substrate, electrostatic discharge (ESD) protection integrated circuits.
This main group covers the following areas:
Semiconductor devices formed in or on a common substrate including only passive thin-film or thick-film components.
Semiconductor devices formed in or on a common substrate including inorganic semiconductor components adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier, e.g. memory arrays.
Semiconductor devices formed in or on a common substrate including inorganic semiconductor components sensitive to electromagnetic radiation, e.g. imagers.
Semiconductor devices formed in or on a common substrate including inorganic semiconductor components having at least one potential-jump barrier or surface barrier and adapted for light emission, e.g. LED arrays.
Semiconductor devices formed in or on a common substrate including thermoelectric or thermomagnetic components.
Semiconductor devices formed in or on a common substrate including components exhibiting superconductivity.
Semiconductor devices formed in or on a common substrate including piezoelectric, electrostrictive or magnetostrictive components.
Semiconductor devices formed in or on a common substrate including components using galvano-magnetic effects or similar magnetic field effects.
Semiconductor devices formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier.
Semiconductor devices formed in or on a common substrate including bulk negative resistance effect components.
Semiconductor devices formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part, e.g. OLED displays, OTFT arrays, OPV modules.
Example:
Only the physical structure of integrated circuits is covered by H01L 27/00. Electrical circuit arrangements are classified elsewhere. For instance, electrical circuit arrangements for driving OLED displays are covered by G09G 3/3208. Electrical circuit arrangements for driving semiconductor imagers are covered by H04N 25/00.
Examples:
This place does not cover:
Single step processes or apparatus specially adapted for the manufacture or treatment of integrated circuits or of parts thereof | H01L 21/70, - H01L 31/00, H01L 33/00, H10K 30/00, H10K 50/00, H10K 59/00, H10K 71/00, H10K 85/00, H10K 99/00, H10N 10/00, H10N 30/00, H10N 35/00, H10N 50/00, H10N 52/00, H10N 60/00 |
Details of integrated circuits | H01L 23/00, H01L 24/00, H01L 29/00 - H01L 31/00, H01L 33/00, H10K 30/00, H10K 50/00, H10K 59/00, H10K 71/00, H10K 85/00, H10K 99/00, H10N 10/00, H10N 30/00, H10N 35/00, H10N 50/00, H10N 52/00, H10N 60/00 |
Assemblies consisting of a plurality of individual semiconductor or other solid state devices | |
Printed circuits |
Attention is drawn to the following places, which may be of interest for search:
Components for integrated circuits | H01L 29/00 - H01L 33/00, H10K 99/00, H10N 10/00, H10N 15/00, H10N 30/00, H10N 35/00, H10N 50/00, H10N 52/00, H10N 60/00, H10N 70/00, H10N 80/00, H10N 97/00, H10N 99/00 |
Processes or apparatus specially adapted for the manufacture or treatment of OLED displays | H01L 31/00, H01L 33/00, H10K 30/00, H10K 50/00, H10K 59/00, H10K 71/00, H10K 85/00, H10K 99/00, H10N 10/00, H10N 30/00, H10N 35/00, H10N 50/00, H10N 52/00, H10N 60/00 |
Coatings | |
Light sources | |
Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers | |
Bolometers | |
Measuring electrical variables | |
Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation | |
Lenses | |
Optical filters | |
Polarisers | |
Light guides | |
Photonic crystals | |
Liquid crystal displays | |
Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties | |
Touch screens | |
Computer aided physical circuit design, e.g. layout for integrated circuits | |
Control circuits for electroluminescent panels based on semiconductive elements, e.g. LEDs | |
Circuit arrangements for driving OLED displays | |
Digital stores | |
Alloys | |
Field emission displays | |
Plasma display panels | |
Semiconductor Lasers | |
Electronic switching or gating | |
Logic circuits, inverting circuits | |
Circuit arrangements for driving semiconductor imagers | |
Light sources with substantially two-dimensional radiating surfaces | |
Encapsulations specially adapted for OLED displays | |
Processes or apparatus specially adapted for the manufacture or treatment of organic semiconductor integrated devices |
Only monolithically integrated devices are covered by main group H01L 27/00, in contrast to assemblies consisting of a plurality of individual semiconductor or other solid state devices which are covered by main group H01L 25/00.
In this main group, in the absence of an indication to the contrary, classification is made in the last appropriate place.
In this main group the use of Indexing Code-codes is mandatory to classify additional information. Keywords are assigned to define the invention whenever no appropriate group symbol is available, as well as to define further relevant aspects of the invention.
In this main group the circulation of documents to other related fields is mandatory, whenever appropriate.
In this place, the following terms or expressions are used with the meaning indicated:
Passive semiconductor component: | semiconductor component not introducing energy into the integrated circuit where they are integrated. Examples thereof are resistors, capacitors, inductors. |
Active semiconductor component: | semiconductor component introducing energy into the integrated circuit where they are integrated. Examples thereof are transistors, diodes, and thyristors. |
SOI (Semiconductor on insulator): | Thin monocrystalline semiconductor layer bonded to a support substrate by means of an intermediate insulating layer. Generally a very thin silicon wafer is molecular-bonded to a support substrate by means of a SiO2 layer. |
CMOS structure: | Complementary metal oxide semiconductor structure comprising a PMOSFET and an NMOSFET connected the following way. Example: Their sharp I-V curve results in low power consumption. They are used as inverters. |
Static random access memory (SRAM): | semiconductor memory wherein each bit of data is stored on four transistors that form two cross coupled inverters.It does not need to be refreshed periodically (static). Example: |
Dynamic random access memory (DRAM): | semiconductor memory wherein each bit of data is stored in a separate capacitor.In general it comprises a transistor and a capacitor.The information fades unless the capacitor charge is refreshed periodically (dynamic). Example: US-A-3387286 |
EEPROM: | Electrically erasable programmable read only memory. It generally comprises a select transistor and a memory cell being a MOSFET transistor having a double gate: a floating gate for charge accumulation and state determination, and a control gate, capacitively coupled to the floating gate to determine its state. Example: |
In patent documents, the following abbreviations are often used:
IC | Integrated circuit |
SITL structure | Static induction transistor logic structure |
VLSI | Very Large Scale Integration |
I2L structure | Integrated injection logic structure |
RAM | Random access memory |
SRAM | Static random access memory |
DRAM | Dynamic random access memory |
FerriRAM, FeRAM | ferroelectric RAM |
MRAM | magnetic RAM |
ROM | Read only memory |
PROM | Programmable read only memory |
EPROM | Electrically programmable read only memory |
EEPROM | Electrically erasable programmable read only memory |
APS | Active pixel sensor |
ReRAM, RRAM | resistance random access memory |
PRAM, PCRAM | phase-change memory |
PPS | Passive pixel sensor |
CMOS | Complementary metal oxide semiconductor |
CCD imager | Charge coupled device imager |
OLED display | Organic light emitting diode display |
TOLED display | Transparent OLED display |
AMOLED display | Active matrix OLED display |
PMOLED display | Passive matrix OLED display |
OTFT array | Organic thin film transistor array |
TFT array | Thin film transistor array |
SOI | Semiconductor on insulator |
CCM | Colour changing medium |
This place covers:
Integration of only passive components such as resistors, inductors, capacitors
Attention is drawn to the following places, which may be of interest for search:
Integration of passive components with components specially adapted for rectifying, oscillating, amplifying or switching on a substrate being an insulating body (e.g. SOI): | |
Passive components as such |
This place covers:
Devices formed in a bulk semiconductor substrate
This place covers:
Devices formed on a substrate by thin-film technology.
This place covers:
Integration of active and passive components
Reverse Engineering
This place does not cover:
Master slice integrated circuits | |
Computer aided physical circuit design, e.g. layout for integrated circuits |
Attention is drawn to the following places, which may be of interest for search:
Cooling arrangements per se |
Attention is drawn to the following places, which may be of interest for search:
Circuits therefor |
Attention is drawn to the following places, which may be of interest for search:
Circuits therefor |
Attention is drawn to the following places, which may be of interest for search:
Circuits therefor |
This place covers:
Integration aspects of protecting structures, directed to increase the reliability of integrated circuits, e.g. integrated device arrangements protecting against over-voltage damages, against over-current damages, against thermal runaway, ESD protections, EOS protections.
Attention is drawn to the following places, which may be of interest for search:
Protection arrangements not implemented within the integrated circuit, e.g. protections at packaging level, at printed circuit board level, or at the system level. | H01L 23/34, H01L 23/60, H01L 23/62, H05K/02 , H05K 7/20; H02H 9/04 |
Components per se, including components used as protecting elements | |
Emergency protective circuit arrangements | |
Circuit arrangements for protecting amplifiers | |
Circuit arrangements for protecting electronic switches | |
Circuit arrangements for protecting logic circuits |
In this place, the following terms or expressions are used with the meaning indicated:
IC | Integrated Circuit |
ESD | Electro Static Discharge |
EOS | Electrical Over-Stress |
SOA | Safe Operating Area |
This place covers:
Integration aspects of protecting device arrangements, wherein the device to be protected includes at least a MOS device.
Attention is drawn to the following places, which may be of interest for search:
Latch-up prevention in CMOS |
This place covers:
Integration aspects of protecting diodes
Attention is drawn to the following places, which may be of interest for search:
Multistep processes for the fabrication of diodes | H01L21/329 |
Using diode connected bipolar transistors | |
Using diode connected field effect transistors | |
IC including a plurality of component not having an active region in common | |
IC including a plurality of component not having an active region in common | |
Structural association of diodes and VDMOS | |
Structural association of diodes and LDMOS | |
Diodes per se |
This place covers:
Integration aspects of protecting structures including bipolar transistors, and of the biasing arrangements which render structures adapted to be used as protecting elements
Attention is drawn to the following places, which may be of interest for search:
Multistep processes for the fabrication of bipolar transistors | H01L21/331 |
Bipolar transistors per se |
This place covers:
Integration aspects of protecting silicon controlled rectifiers, and of their triggering structures.
Example: (from EP 2246885 A1)
Attention is drawn to the following places, which may be of interest for search:
Multistep processes for the fabrication of thyristors | H01L21/332 |
Latch-up prevention in CMOS | |
Thyristors per se |
This place covers:
Integration aspects of protecting field effect transistors, and of the triggering structures which render said field effect transistors adapted to be used as protecting elements
Attention is drawn to the following places, which may be of interest for search:
Multistep processes for the fabrication of field effect transistors | H01L21/335 |
Field effect transistors per se | |
Voltage or current sensing structures in VDMOS | |
Voltage or current sensing structures in LDMOS |
This place covers:
Integration aspects of structural adaptations of the field effect transistors which make them electrically behave in a way which substantially differs from the usual one; modifications aimed to enhance parasitic effects, e.g. the bipolar transistor inherently present in MOS transistors.
Example:
This place covers:
Integration details concerning the doping profile, the shape, the structure, the dimensioning of the layer acting as base of the bipolar transistor and of its contact region
Example:
Attention is drawn to the following places, which may be of interest for search:
Prevention of punch-through | |
Prevention of bipolar effect |
This place covers:
Integration of an active clamp by means of a field effect transistor, which is driven in a conducting state by a further field effect transistor coupled to its gate electrode.
Example:
This place does not cover:
Active clamps driven by an inverter |
This place covers:
Integration of an active clamp by means of a field effect transistor, which is driven in a conducting state by a RC discriminating circuit or by other voltage partitioning circuits.
This place does not cover:
Field-effect transistors in a "Darlington-like" configuration as protective elements |
Attention is drawn to the following places, which may be of interest for search:
Structural details of fuses | |
Impedance arrangements | |
Multistep processes for the fabrication of resistors, capacitors, inductors | |
Resistors or capacitors per se |
This place covers:
Details concerning the electrical interconnections between the protecting structures and/or the connections between the protecting structures and the circuit to be protected; specific routing schemes or the provision of dedicated conducting path for the triggering of the protecting structures as well as for the evacuation of the discharge current.
Example:
Attention is drawn to the following places, which may be of interest for search:
Interconnections | |
Routing algorithms |
In this place, the following terms or expressions are used with the meaning indicated:
ESD buses | conductive traces dedicated to the evacuation of current produced by an electrostatic discharge, or to the propagation of triggering signal for the protecting elements |
This place covers:
Integration of the protecting devices in specific areas of the integrated circuit, such as under the bonding pads, or within the scribe-lines, in peripheral regions of memories or TFT displays, in the substrate region below the insulator layer of SOI wafers.
Attention is drawn to the following places, which may be of interest for search:
IC having three dimensional layout | |
Hybrid SOI | |
Arrangements to prevent high voltage or static electricity failures in active matrix liquid crystal display cells |
This place does not cover:
Electrical or thermal protection for MOS devices |
This place covers:
Cross-point memories using a fuse or anti-fuse as the active element.
This place covers:
Cross-point memories
This place covers:
Cross-point memories in which a diode is the selection element.
This place covers:
Integration of memories (e.g. SRAM, ROM, PROM) with peripheral circuits.
This place does not cover:
Integration of DRAM memories with peripheral circuits | |
Integration of floating-gate memories with peripheral circuits | |
Integration of nitride-based memories (e.g. NROM, MONOS, SONOS) with peripheral circuits | |
Integration of FeRAM memories with peripheral circuits |
Attention is drawn to the following places, which may be of interest for search:
Computer aided physical circuit design, e.g. layout design for integrated circuits |
If a layout is shown, the group symbol H01L 27/0207 is also allocated.
This place covers:
Electrical and thermal isolation structures between pixels.
Example of an electrical isolation structure
WO 2010/90149
Example of a thermal isolation structure
WO 2005/098380
This place covers:
Integration of TFTs on an insulating or insulator-covered substrate, such as
Glass, plastic, insulator coated metal or other non-semiconducting substrates.
This place does not cover:
AMOLED displays |
Attention is drawn to the following places, which may be of interest for search:
Manufacture of a plurality of TFTs on a non-semiconducting substrate | |
Multistep processes to manufacture TFTs | |
Thin film unipolar field-effect transistors, i.e. TFTs, per se | |
Active matrix LCD displays | |
Circuit arrangements for AM displays |
In this place, the following terms or expressions are used with the meaning indicated:
AMLCD display | active matrix liquid crystal display |
TFT | Thin film unipolar field-effect transistor |
AMOLED display | active matrix organic light emitting diode display |
This place covers:
SOI integrated circuits.
Attention is drawn to the following places, which may be of interest for search:
Dielectric regions, such as EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology | |
Multistep processes to manufacture devices on a substrate being other than a semiconductor body | |
Multistep processes to manufacture monocrystalline silicon TFTs on insulating substrates | |
Monocrystalline TFTs per se |
This place covers:
Integrated circuits employing partial SOI.
This place covers:
Integrated circuits with FinFETs on an insulating substrate
Attention is drawn to the following places, which may be of interest for search:
Arrangements including only transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET | |
Arrangements including only CMISFET transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET | |
Multistep processes to manufacture transistors with a gate at the side of the channel and a horizontal current flow | |
Transistors with a gate at the side of the channel and a horizontal current flow |
In patent documents, the following abbreviations are often used:
FinFET | MuGFET, BarFET, Triple gate FET, OMEGA FET, Pi-Gate FET |
Attention is drawn to the following places, which may be of interest for search:
Crystallisation per se |
This place covers:
Integrated circuits having TFTs integrated with passive components, e.g. antennas, capacitors
Attention is drawn to the following places, which may be of interest for search:
SOI arrangements | |
Storage capacitors associated with the pixel electrode in AMLCD displays | |
RFID circuits | |
Memories employing capacitors, e.g. DRAM passive two-terminal components without a potential-jump or surface barrier for integrated circuits, details thereof and multistep manufacturing processes therefor |
This place covers:
Arrangements of solar cells or other semiconducting energy conversion devices, arrangements of photo-detecting elements such as 2D-detectors, imagers
This place does not cover:
Radiation-sensitive components structurally associated with one or more electric light sources only | |
Couplings of light guides with optoelectronic elements |
Attention is drawn to the following places, which may be of interest for search:
Radiation detecting components |
This place covers:
- Single discrete photovoltaic cells integrated or directly associated with one or more electric components in or on the same substrate, e.g. single thin film photovoltaic cell with integrated bypass diode.
- Devices consisting of PV cells and other semiconductor components, e.g. transistors, on a common substrate, typically PV cells being used as an energy source to drive the other semiconductors.
- Examples:
This place does not cover:
Photovoltaic modules or arrays of single photovoltaic cells comprising bypass diodes integrated or directly associated with the devices | |
Photovoltaic modules composed of a plurality of thin film solar cells deposited on the same substrate |
Attention is drawn to the following places, which may be of interest for search:
Circuitry connections of bypass diodes in solar panel(s) | |
Solar cell structures | |
Semiconductor organic solar cells |
This place covers:
Integration of devices controlled by radiation. These can be for detection purposes, such as photodiode arrays, or for imaging purposes, such as imagers.
Attention is drawn to the following places, which may be of interest for search:
Radiation detecting components | |
Organic semiconductor devices controlled by radiation |
This place covers:
Example: integration of a visible and an infrared sensor
This group is not exclusive with H01L 27/1446
This place covers:
Spatially repeated sensors of the same type such as photodiode arrays, position-sensitive sensors. The repetition can be linear or in form or a matrix, but not for imaging purposes.
Example:
Attention is drawn to the following places, which may be of interest for search:
Imaging devices |
This group is not exclusive with H01L 27/1443.
The spatial repetition should not be for imaging purposes.
This place covers:
Inorganic semiconductor imaging devices
Attention is drawn to the following places, which may be of interest for search:
Optical filters | |
Waveguides | |
Details of semiconductor imagers (for television systems) | |
Control circuit arrangements for driving solid state imagers |
Imaging devices having components using inorganic materials only are classified in H01L 27/146.
Imaging devices having components using organic materials or a combination of organic materials and other materials are classified in H10K 39/32.
In this place, the following terms or expressions are used with the meaning indicated:
Active pixel sensor (APS) | Sensor comprising pixel amplification means, e.g. a transistor as source follower |
Aperture ratio | Ratio between light sensitive area of a pixel and the total area occupied by that pixel |
Backside illumination | Illumination of the imagers from the of the device where the imager circuitry has not been formed |
Blooming | Spilling over of charges from one pixel to the next one after overexposure |
Charge coupled device | Architecture of an integrated circuit based on the transport of charge packets by capacitive coupling from one capacitor to the next one |
Charge injection device | Architecture of semiconductor device based on measuring currents induced in MOS capacitors at the moment charge packets are injected into the substrate |
Dark current | Signal generated by the image sensor when the device is in the dark |
Delay line | Component used to delay an electrical signal over a defined time |
Dynamic range | Ratio of the largest possible signal (full well capacity of the pixel) divided by the smallest possible signal (background noise) of a sensor- |
Frame-transfer CCD | Two dimensional architecture of a CCD imager that has an analogue memory cell for every pixel below the total array of light sensitive pixels |
Full-frame CCD | Two dimensional architecture of a CCD imager transferring collected charge directly to readout |
Integration time | Time that an imager is collecting charges (photon generated and/or dark current generated) |
Interlaced scanning | Scanning mode in which only part (odd or even lines) of the lines of the image are captured in an exposure period |
Interline-transfer CCD | Two dimensional architecture of a CCD imager wherein each photodiode has a parallel CCD storage region covered by an opaque mask. After image data has been collected and transferred to the adjacent CCD storage region charge is CCD-shifted vertically to the readout IC. |
Overflow drain | Doped region to extract undesired charge resulting from blooming |
Passive pixel sensor | Pixels comprising per pixel only a photodiode or a photodiode and an addressing transistor |
Photoconductor | Material changing its conductivity when light impinges on it. The delta in conductivity is measured and the incoming radiation calculated in imagers. |
TDI-type CCD-imager | Time delay and integration (TDI) is a type of CCD wherein a TDI clock is used to synchronize the movement of charged packets in a CCD with that of another movement. |
Wafer level processing | Processing of several semiconductor devices in a single wafer in the same processing cycle |
In patent documents, the following abbreviations are often used:
APS | Active pixel sensor |
CCD | Charge coupled device |
PPS | Passive pixel sensor |
This place covers:
Details of organic semiconductor imaging structures such as encapsulations, geometry of disposition of passive and active elements, lenses, isolation, etc, whenever they are specific for semiconductor imaging devices, i.e. they solve problems specific to semiconductor imaging devices.
Attention is drawn to the following places, which may be of interest for search:
Encapsulation of integrated circuits |
This place covers:
The disposition of the elements within the pixel, such as the transfer, driving, reset transistors, capacitor, photodetector. Also covered are the disposition of electrodes and wiring lines such as the power, bit and data lines. Disposition of the different doped regions within the pixel also fall within the scope of the definition of this subclass.
Examples:
US 2011/019063
This place covers:
Example:
This place covers:
Only geometrical issues of the photosensitive area.
US 2010/092875
This place does not cover:
Details of an APS photosensitive area such as doping or depth |
This place covers:
Active pixel sensors [APS], i.e. sensors having in each pixel a photodetecting element and amplifications means within the pixel. Very often CMOS technology is used.
Example:
Attention is drawn to the following places, which may be of interest for search:
Scanning details of imagers | |
Circuitry of imagers |
This place covers:
An APS wherein the photosensitive area is characterised by its doping, depth, etc.
Example:
US 2011/241089
This place does not cover:
Only geometrical (i.e.. layout) aspects of a photosensitive area in imagers |
This place covers:
APS-imagers wherein the invention concerns a specific feature of at least one of the transistor within the unit cell (transfer transistor, reset transistor, source follower,...).
This place covers:
Example:
US 2011/241080
This place covers:
Example:
US 2011/241079
This place covers:
Containers and encapsulations specially adapted for imagers
Example:
Attention is drawn to the following places, which may be of interest for search:
Containers of integrated circuits in general | |
Encapsulation of integrated circuits in general |
This place covers:
Any kind of coatings within the imager (e.g. interlayer dielectric (ILD), antireflective coatings (ARC)).
Example:
Attention is drawn to the following places, which may be of interest for search:
Coatings | |
Optical filters |
This place covers:
arrangement of color filters, e.g. Bayer pattern
Examples:
This place covers:
Examples:
This place does not cover:
Shielding in CCD-type imagers |
This place covers:
Optical elements in devices such as lenses, reflectors, light guiding structures within the device. Such devices include, but are not limited to, CCD-imagers.
Example of an optical element:
Attention is drawn to the following places, which may be of interest for search:
Lenses | |
Photonic crystals |
This place covers:
Elements reflecting light towards the light detecting portion
Example:
This place covers:
Electrical or thermal isolation structures between pixels.
This place covers:
Structures processed at a wafer level.
Example:
Attention is drawn to the following places, which may be of interest for search:
Manufacture thereof |
This place covers:
Image sensor in one substrate connected to its driving IC in another substrate.
Example:
This place does not cover:
Hybrid-type infrared imagers | |
Hybrid-type X-ray imagers |
Attention is drawn to the following places, which may be of interest for search:
Interconnect structures | |
Hybrid Infrared CCD or CID imagers |
This place covers:
Structures to connect e.g. one imaging substrate with its driving substrate, or an image sensor with the external driving circuitry, or special connections within the device.
US 2008/308890
This place covers:
Imagers having the circuitry beneath the photosensitive area whenever special arrangements are made to transfer the charges from the sensor to the circuitry.
This place covers:
Imagers wherein light impinges from the surface of the semiconductor wafer opposite to the surface where the imaging structure has been created.
Example:
This place covers:
Components (doped regions, transistors, lines) shared by adjacent pixels.
Example:
This place covers:
Photodiode arrays for imaging purposes and MOS imagers.
This place covers:
Imagers with pixels each for a primary colour, e.g. RGB, e.g. achieved by means of filters.
This place does not cover:
Colour imagers having photoconductive layer |
This place covers:
Colour imager with stacked configuration, such as a multiple pn-junction stack each to detect a colour.
Example:
This place covers:
Imagers for sensing infrared radiation
This place does not cover:
Infrared imagers having photoconductive layer |
This place covers:
Imagers for sensing infrared radiation having an infrared sensor in a substrate and the driving circuitry in a separate substrate both being connected together.
Attention is drawn to the following places, which may be of interest for search:
Hybrid type imagers in general | |
Interconnect structures | |
Hybrid type X-ray imagers | |
Infrared imagers having photoconductive layer |
This place covers:
Infrared imagers having generally a stack: LWIR, MWIR, SWIR. The structure is generally similar to that in H01L 27/14647 but for sensing infrared radiation.
Attention is drawn to the following places, which may be of interest for search:
Stacked colour imagers |
This place covers:
Structural arrangements to suppress blooming (see glossary of terms in H01L 27/146) such as overflow drains.
Attention is drawn to the following places, which may be of interest for search:
Blooming suppression in imagers having photoconductive layer |
This place covers:
Vertical and horizontal overflow drains
Attention is drawn to the following places, which may be of interest for search:
Overflow drains in imagers having photoconductive layer |
This place covers:
Imagers for sensing X-ray, G-rays or corpuscular radiation
Attention is drawn to the following places, which may be of interest for search:
X-ray imagers having photoconductive layer | |
Measuring X-, gamma- or corpuscular radiation |
This place covers:
The semiconductor layers convert directly the incoming radiation into charges, without need of a scintillator
This place covers:
Imagers for sensing X-ray, gamma-ray or corpuscular radiation having an infrared sensor in a substrate and the driving circuitry in a separate substrate both being connected together.
Attention is drawn to the following places, which may be of interest for search:
Hybrid type imagers in general | |
Interconnect structures | |
Hybrid type infrared imagers |
This place covers:
This group comprises X-ray radiation imagers having a scintillator (an ionic solid) which converts incoming X-ray radiation into visible light. The detector detects the visible light converted by the scintillator (also called phosphor).
Attention is drawn to the following places, which may be of interest for search:
Measuring X-ray radiation with a scintillation-diode combination |
This place covers:
These imagers work on the principle that the photoconductive layer changes its conductivity with the incoming radiation. The change in conductivity is measured and the incoming radiation derived.
This place covers:
Photoconductive imagers having a substrate with the imagers formed therein and another connected thereto with the electronic circuit.
Attention is drawn to the following places, which may be of interest for search:
Hybrid type imagers in general | |
Interconnect structures | |
Hybrid type infrared imagers | |
Hybrid type X-ray imagers |
This place does not cover:
Blooming suppression in PD- or MOS-imagers |
This place does not cover:
Overflow structures in PD- or MOS-imagers |
This place does not cover:
X-ray detecting PD- or MOS-imagers |
Attention is drawn to the following places, which may be of interest for search:
Measuring X-, gamma- or corpuscular radiation |
This place covers:
Imagers having integrated light sources, wherein the light emitted from the integrated light source is reflected on the object to be detected and enters the imagers. Examples thereof are scanning heads, photocopier heads or fingerprint detectors
Attention is drawn to the following places, which may be of interest for search:
CID-type CCD-imagers wherein the object to be imaged in contact with the sensor | |
Fingerprint or palmprint sensors for the recognition of biometric, human-related or animal-related patterns in image or video data | |
Vascular sensors for the recognition of biometric, human-related or animal-related patterns in image or video data | |
Scanning heads |
This place covers:
Multistep processes specially adapted for the manufacture of imagers
This place covers:
Formation of coatings (antireflective coatings, filters, shielding) as well as microlenses and other optical elements.
Attention is drawn to the following places, which may be of interest for search:
Coatings | |
Optical elements | |
Coatings in general | |
Lenses | |
Optical filters | |
Photonic crystals |
Attention is drawn to the following places, which may be of interest for search:
Wafer level imagers |
This place covers:
Manufacturing process of imagers using technology of the MOS-type
This place covers:
Manufacture of hybrid-type imagers.
The manufacture is in general for any kind of hybrid-type imagers (see types below under informative references).
Attention is drawn to the following places, which may be of interest for search:
Hybrid-type imagers in general | |
Hybrid-type infrared imagers | |
Hybrid-type X-ray imagers | |
Hybrid-type infrared photoconductive |
This place covers:
CCD-type imagers
Attention is drawn to the following places, which may be of interest for search:
Charge coupled devices per se |
This place covers:
Lines and electrodes layouts, disposition of pixel elements such as the transfer gates, photodetectors of CCD-type imagers.
Attention is drawn to the following places, which may be of interest for search:
Circuit arrangements for driving solid state imagers |
This place covers:
Shielding specific to CCDs.
Attention is drawn to the following places, which may be of interest for search:
Shielding in general for imagers |
This place covers:
CCD-imagers having a linear arrangement of the pixels, e.g. as fax heads or photocopiers
This place covers:
Combination of interline transfer with a frame transfer (see hereafter).
Each photodiode has a parallel CCD region which shifts charge vertically to a storage 2D matrix (one storage pixel per one photosensitive pixel). The charges stored in the storage matrix are then read out.
Example:
This place covers:
Each photodiode has a parallel CCD storage region covered by an opaque mask. After image data has been collected and transferred to the adjacent CCD storage region charge is CCD-shifted vertically to the readout IC.
This place covers:
The photosensitive 2D array has adjacent a 2D storage area, having a storage pixel per photosensitive pixel. The charges collected are transferred in parallel to the storage area for readout.
Example:
This place covers:
Time delay and integration type CCD imager. Time delay and integration (TDI) relates to details of CCD imaging arrays operating in a TDI mode (the pixel clock rate must be matched to the image velocity).
This place covers:
CID place the object to be imaged in contact with the sensor and use, typically, LEDs for the illumination of the object to be imaged.
Attention is drawn to the following places, which may be of interest for search:
Contact-type imagers |
This place covers:
Devices consisting of a plurality of monolithically integrated inorganic semiconductor light emitting diode (LED) components or consisting of inorganic semiconductor LED components monolithically integrated with other semiconductor components.
Attention is drawn to the following places, which may be of interest for search:
Hybrid assemblies of a plurality of individual LED devices | |
Hybrid assemblies of LED devices with other semiconductor devices | |
LED devices | |
LED devices with a plurality of light emitting regions | |
Printing devices using LED arrays as print heads | |
LCD displays | |
Devices consisting of semiconductor laser diode components monolithically integrated with other components | |
Displays having an organic semiconductor light emitting material or comprising a mixture of an inorganic and an organic semiconductor light emitting material (OLED displays) |
This place covers:
- Passive two-terminal devices, i.e. resistors, capacitors and inductors, specially adapted for being integrated with other semiconductor devices
- Multistep processes for the fabrication of these two terminal devices
This place does not cover:
Integration methods | |
Testing or measuring during manufacture | |
Integrated circuits | |
Two-terminal components with a potential-jump or surface barrier |
Attention is drawn to the following places, which may be of interest for search:
In case a single step of the multistep sequence would appear peculiar, it should also be classified in the corresponding single step, for example:
- H01L 21/02107 for the formation of insulating layers,
- H01L 21/283 - H01L 21/288 for the formation of conductive layers,
- H01L 21/027 - H01L 21/033 for lithographic aspects
- H01L 21/311 for etching insulating layers
- H01L 21/3213 for etching conductive layers
This place covers:
- Types of inorganic semiconductor components having potential barriers, adapted for rectifying, amplifying, oscillating or switching; Multistep manufacturing processes therefor.
- Types of components for integrated circuits being capacitors or resistors having potential barriers; Multistep manufacturing processes therefor.
- Details of semiconductor bodies of said components; Details of semiconductor bodies not otherwise provided for; Multistep manufacturing processes therefor.
- Details of electrodes of said components; Details of electrodes of semiconductor components not otherwise provided for; Multistep manufacturing processes therefor.
Further information:
In this main group:
Said potential barriers may be of the PN junction type, the metal-semiconductor junction type, the metal-insulator-semiconductor type, the high-low junction type, the heterojunction type.
Said details of semiconductor bodies and said multistep manufacturing processes therefor are covered by groups H01L 29/02 - H01L 29/365.
Said details of electrodes are covered by groups H01L 29/40 - H01L 29/518 except group H01L 29/401, and said multistep manufacturing processes therefor are covered by group H01L 29/401 (pending reorganisation see group H01L 21/28 and subgroups).
Said types of inorganic semiconductor components are covered by groups H01L 29/66 - H01L 29/945 except groups H01L 29/66007 and subgroups, H01L 29/8605, H01L 29/92 - H01L 29/945, and said multistep manufacturing processes therefor are covered by group H01L 29/66007 and subgroups except H01L 29/66022 and H01L 29/66166 - H01L 29/66189.
Said resistors are covered by group H01L 29/8605, and said multistep manufacturing processes therefor are covered by groups H01L 29/66022, H01L 29/6606 and H01L 29/66166.
Said capacitors are covered by groups H01L 29/92 - H01L 29/945, and said multistep manufacturing processes therefor are covered by groups H01L 29/66022, H01L 29/6606 and H01L 29/66174 - H01L 29/66189.
This place does not cover:
Details of semiconductor or other solid state devices other than details of semiconductor bodies or of electrodes thereof | |
Devices consisting of a plurality of solid state components formed in or on a common substrate | |
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof | |
Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof | |
Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers | |
Electric solid-state devices not otherwise provided for | |
Thermo-electric devices comprising a junction of dissimilar materials, i.e. exhibiting Seebeck or Peltier effect with or without other thermo-electric effects or thermomagnetic effects; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof | |
Thermoelectric devices without a junction of dissimilar materials; Thermomagnetic devices, e.g. using Nernst-Ettinghausen effect; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof | |
Piezoelectric devices; Electrostrictive devices; Magnetostrictive devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof | |
Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof | |
Devices using superconductivity; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof | |
Solid state devices adapted for rectifying, amplifying, oscillating or switching having no potential barriers; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof | |
Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof | |
Details peculiar to solid state devices not provided for in groups H01L 27/00 – H01L 33/00, H10B 10/00 – H10B 53/00, H10B 69/00, H10K 10/00, H10K 30/00, H10K 50/00, H10K 71/00, H10K 77/00, H10K 85/00 and H10K 99/00 and not provided for in any other subclass |
Attention is drawn to the following places, which may be of interest for search:
Processes or apparatuses adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof | |
Assemblies consisting of a plurality of individual semiconductor or other solid state devices | |
Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor | |
Single-crystal-growth, e.g. of semiconductor material, in general | |
Ion-sensitive or chemical field-effect transistors | |
Digital stores characterised by the use of particular electric elements; Storage elements therefore | |
Resistors in general | |
Capacitors in general | |
Ceramic barrier-layer capacitors | |
Semiconductor lasers | |
Conversion of electric power | |
Generation of oscillations | |
Amplifiers with semiconductor devices as amplifying elements | |
Electronic switching or gating | |
Logic circuits; Inverting circuits | |
Printed circuits | |
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof |
Classification of invention information is made in any one of the following 3 sets of groups if these sets of groups are relevant:
- H01L 29/02 - H01L 29/36 for details of semiconductor bodies and multistep manufacturing processes therefor;
- H01L 29/40 - H01L 29/51 for details of electrodes and multistep manufacturing processes therefor; and
- H01L 29/66 - H01L 29/94 for types of components and multistep manufacturing processes therefor.
Classification of additional information through allocation of the Indexing Codes H01L 29/00 - H01L 29/94 is mandatory.
In this place, the following terms or expressions are used with the meaning indicated:
alloy | homogeneous material having chemically combined atoms or ions in variable proportions, e.g. AlxGa(1-x)As |
bidirectional | conducting main current in opposite directions |
bandgap, band gap | difference between energy levels of electrons bound to their nuclei (valence electrons) and energy levels allowing electrons to migrate freely (conduction electrons) |
bipolar device | device using both charge carrier types in operation, i.e. both electrons and holes |
breakdown | sudden change to a very low dynamic electrical resistance, e.g. in a reverse biased pn-junction |
channel stopper | means for limiting parasitic surface channel formation, usually a highly doped surface region in a lightly doped substrate of same conductivity type |
charge carrier | electron (having a negative charge) or hole (having a positive charge) |
circuit | plurality of electric elements interconnected to perform an electrical or electronic function |
conductivity | ability of a material to conduct electric current |
component | a single active or passive electric circuit element that may be formed in or on a common substrate |
compound | homogeneous material having chemically combined atoms or ions in definite proportions, e.g. gallium arsenide (GaAs), silicon carbide (SiC) |
device | electric circuit element |
diode | two-terminal semiconductor component with non linear current-voltage characteristic |
electrode | region other than the semiconductor body itself, which exerts an influence on the solid state body electrically, whether or not an external electrical connection is made thereto. The term covers capacitive or inductive coupling arrangements and an electrode may include several portions, e.g. metallic and dielectric regions of a capacitive coupling arrangement. Only those portions which exert an influence on the solid state body by virtue of their shape, size or disposition or the material of which they are formed are considered to be part of the electrode. |
electron | negative charge carrier |
field plate | electric field shaping field-effect electrode |
guard region | electric field shaping semiconductor region, e.g. to increase the breakdown voltage of an adjacent pn-junction |
guard ring | electric field shaping ring-shaped semiconductor region |
high-low junction | junction of materials with relatively high and low doping concentration |
heterojunction | junction of different materials |
hole | positive charge carrier, i.e. missing valence electron, valence band vacancy |
homojunction | junction of same material |
multiple quantum well | quantum structure composed of a plurality of uncorrelated quantum wells |
N-type | negative conductivity type, i.e. with electrons as majority charge carriers |
ohmic contact | non-rectifying contact |
part | any structural unit included in a complete device |
Pn-junction | junction of materials of opposite conductivity types, i.e. n-type and p-type materials |
P-type | positive conductivity type, i.e. with holes as majority charge carriers |
quantum well | potential well with one-dimensional confinement whereby quantum effects are achieved |
quantum wire | potential well with two-dimensional confinement whereby quantum effects are achieved |
quantum box | potential well with three-dimensional confinement whereby quantum effects are achieved |
schottky contact | rectifying metal-semiconductor contact |
semiconductor body | body of semiconductor material within which, or at the surface of which, the physical effects characteristic of the component occur |
silicide | silicon-metal compound |
structurally associated with | with a built-in |
superlattice | quantum structure with a plurality of correlated quantum wells leading to the formation of mini-bands and mini-bandgaps across the whole structure |
unipolar device | device using only one of both charge carrier types, i. e. either electrons or holes |
In patent documents, the following words/expressions are often used as synonyms:
- atomic layer doping, atomic plane doping, delta doping, planar doping
- chip, die
- depletion region, space charge region
- electrode, contact
- Group IV, group 14: C, Si, Ge, Sn, Pb
- II-VI, group 12/16, e.g. CdTe
- III-V, AIIIBV, AIII-BV, group 13/15, e.g. GaAs
- intrinsic, undoped, not intentionally doped
- impurity, dopant, doping material
- polysilicon, poly-Si, polycrystalline silicon
- charge compensation, coolMOS, multi-RESURF, superjunction
- channel stopper, channel stop, chanstop
In patent documents, the following words/expressions are often used with the meaning indicated:
Breakover | start of regenerative current flow in a thyristor |
Chip | piece of semiconductor material, e.g. single crystal semiconductor substrate, having one or more active or passive electric circuit elements |
(charge or carrier) confinement | restriction of charge carriers to locations of reduced dimensions, e.g. quantum wells, field-effect induced potential wells |
Crystal defect | non-uniformity in crystal lattice |
De Broglie wavelength | wavelength of a particle |
Depletion region | region from which free charge carriers are expelled |
Direct bandgap material | semiconductor material wherein transition from the conduction to the valence band does not require a change in crystal momentum for an electron, e.g. gallium arsenide (GaAs) |
Doping concentration | number of dopant atoms per a given volume of semiconductor material, e.g. per cubic centimetre |
Doping density | number of dopant atoms per a given surface of semiconductor material, e.g. per square centimetre |
Doping profile | point-to-point doping concentration throughout a semiconductor body or region thereof |
Epitaxial layer | added layer of semiconductor crystal taking on the same crystalline orientation as a semiconductor crystal substrate |
Field oxide | oxide layer overlying a major surface of a device semiconductor body |
Floating gate | electrically floating gate electrode, e.g. having no direct electrical connection, usually used for charge storage |
Forward bias | voltage applied in a current conducting direction |
Indirect bandgap material | semiconductor material wherein transition from the conduction to the valence band requires a change in crystal momentum for an electron, e.g. silicon (Si) |
Inversion layer | surface region in a semiconductor material wherein the minority carrier concentration is larger than the majority carrier concentration, e.g. induced by field-effect |
Latch-up | regenerative feedback loop thyristor-type conducting state, being parasitic in e.g. non thyristor-type components due to loss of gating capability |
Lifetime killer | deep level impurity creating a potential trap for charge carriers in the forbidden band remote from the conduction and valence bands thereby reducing charge carrier lifetime |
Majority carrier | more abundant charge carrier |
Minority carrier | less abundant charge carrier |
Polycide | polysilicon-silicide stack |
Recombination center, deep level center | potential trap for charge carriers in the forbidden band remote from the conduction and valence bands |
Reverse bias | voltage applied in a current blocking direction |
Shockley diode | two-terminal thyristor |
Silicon controlled rectifier (SCR) | three-terminal thyristor |
Salicide process | self-aligned silicide process |
Wide band gap semiconductor material | semiconductor material with a band gap larger than 1.7 eV, e.g. SiC, GaN, diamond |
In this place, the following terms or expressions are used with the meaning indicated:
BBT | Bulk Barrier Transistor |
CHINT | CHarge INjection Transistor |
FCTh | Field Controlled Thyristor |
IGBT | Insulated Gate Bipolar Transistor |
IPG | In-plane Gate Transistor |
HET | Hot Electron Transistor |
HFET | Heterojunction Field Effect Transistor |
JFET | Junction Field Effect Transistor |
MBT | Metal Base Transistor |
MISFET | Metal-Insulator-Field Effect Transistor |
PBT | Permeable Base Transistor |
PDBT | Planar Doped Barrier Transistor |
RHET | Resonant Tunnelling Hot Electron Transistor |
RTT | Resonant Tunnelling Transistor |
SET | Single Electron Transistor |
SIT | Static field Induction Transistor |
SiTh | Thyristor |
VMT | Velocity Modulation Transistor |
This place covers:
For multistep processes, a junction between two regions of the same material but in a different crystalline state, e.g. amorphous silicon or polysilicon emitters on single crystalline silicon, is not considered as an heterojunction
This place covers:
So-called FCTh, SITh and FCD are classified in H01L 29/6609.
Documents are classified in this group when they are concerned with avoiding a short circuit between source or drain and gate.
Improving the source or drain contact is classified elsewhere, e.g. H01L 21/28518.
Improving the gate is also classified elsewhere, e.g. H01L 21/28052.
To note the mere presence of salicide, the corresponding Indexing Code is systematically allocated
This place covers:
It follows from the definition that source / drain with different silicide thicknesses are also classified here, as at least one of the thickness of the source / drain silicide is different from the thickness of the gate silicide
Processes where only a part of the gate is a dummy layer, e.g. part of a silicide stemming from the silicidation of polysilicon, are also classified in this group.
This place does not cover:
Manufacturing of the gate itself |
Processes wherein there are no source and drain semiconductor regions formed in the active layer, i.e. no high-temperature, e.g. a 800°C, step is required for these regions, are classified in this group.
Examples: S&D deposited on the active layer;
No S&D regions at all, e.g. alloyed contacts;
Gate recess etched through S&D layer(s).
This place covers:
Processes wherein the drain is formed before the final gate but wherein a LDD or the like is formed after
The single step processes forming the multistep should also be classified independently of the multistep, provided the single step gives significant information.
This place does not cover:
Devices consisting of a plurality of solid state components formed in, or on, a common substrate, other than combinations of radiation-sensitive components with one or more electric light sources | |
Organic photosensitive devices |
Attention is drawn to the following places, which may be of interest for search:
Imager structures consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate | |
Production of heat using solar heat | |
Measurement of X-radiation, gamma radiation, corpuscular radiation or cosmic radiation with semiconductor detectors | |
Measurement of X-radiation, gamma radiation, corpuscular radiation or cosmic radiation with resistance detectors | |
Measurement of neutron radiation with semiconductor detectors | |
Couplings of light guides with optoelectronic elements | |
Arrangement for obtaining electrical energy from radioactive sources | |
Electrolytic light sensitive devices, e.g. dye sensitized solar cells |
In this place, the following terms or expressions are used with the meaning indicated:
Homojunction | p-n junction involving both p and n regions made out of the same material, with the same composition and the same structure (only the doping species change). |
Heterojunction | p-n junction involving two different materials, the difference being in the structure and/or the composition (examples: p-type amorphous silicon / n-type crystalline silicon; GaAs/GaAlAs) |
Tandem solar cell | A plurality of junctions are monolithically stacked on one another, forming a multiple junction solar cell |
Schottky contact | Rectifying (non-ohmic) metal/semiconductor contact |
Group 14 elements | Formerly known as group IVa elements (C, Si, Ge, Sn, Pb) |
Coating | A "coating" is a thin layer deposited on the surface of the semiconductor device and only on its surface, having passivating or optical (ex: AR) effects. |
Encapsulation | An "encapsulation" is an enclosure which consists of one or more layers formed on the body and in intimate contact therewith. Compared to a "coating", an "encapsulation" is usually a much thicker film (used for protecting the device from the outside) which also usually wraps the edges of the device. |
Container | Enclosure forming part of the complete device and is essentially a solid construction in which the body of the device is placed, or which is formed around the body without forming an intimate layer thereon. |
Apparatus | A category of subject matter which is a machine or device, described in terms of its functional capabilities or structural features, that is used to make a product, or to carry out a non-manufacturing process or activity. |
Electrodes | Regions in or on the body of the device (other than the solid state body itself), which exert an influence on the solid state body electrically, whether or not an external electrical connection is made thereto. In electrode arrangements including several portions only those portions which exert an influence on the solid state body by virtue of their shape, size or disposition or the material of which they are formed are considered to be part of the electrode. The other portions are considered to be "arrangements for conducting electric current to or from the solid state body" or "interconnections between solid state components formed in or on a common substrate", i.e. leads. |
Up- or down conversion | Transformation of incident photons having wavelengths into different wavelengths (longer or shorter) in order to increase absorption of the photoactive part of the device (usually using luminescent materials) |
Photoelectric devices | Light sensitive devices based on the photoelectric effect, including both photovoltaic devices (solar cells) and photodetecting devices (photosensors) |
Photoconductive material | Material in which the electrical conductivity changes when light is absorbed by said material |
Superlattice | Periodic structure involving alternating semiconductor layers, the thickness of each layer being typically of a few nanometres and in which quantum effects take place. The difference between adjacent layers lies in the composition and/or the doping. |
Intrinsic layer | Semiconductor layer which is not intentionally doped |
In patent documents, the following abbreviations are often used:
A-Si, α-Si | amorphous silicon |
C-Si | crystalline silicon |
Mc-Si, muc-Si, μc-Si, μ-Si | microcrystalline silicon |
Poly-Si | polycrystalline silicon |
PIN | P-N junction with thick intrinsic layer in between |
AIBIIICVI compound | I-III-VI compound, chalcogenides, chalcopyrites |
CIS | CuInSe2 |
CIGS | CuInGaSe2 |
CIGSS | CuInGaSSe |
TCO | Transparent conducting oxide |
ITO | Indium Tin Oxide |
FTO | Fluorine doped tin oxide |
AZO | Aluminium doped Zinc Oxide |
GZO | Gallium doped Zinc Oxide |
QW | Quantum well |
MQW | Multiple Quantum Well |
HIT | Heterojunction with Intrinsic Thin-layer |
PERL solar cell | Passivated Emitter Rear Locally Diffused solar cell |
ARC, AR | Anti-reflective coating |
MPPT | Maximum Power Point Tracking |
MWT | Metal Wrap Through |
FMWT | Front Metal Wrap Through |
EWT | Emitter Wrap Through |
IBC | Interdigitated Back Contact (solar cells) |
BSR | Back Surface Reflector |
BSF | Back Surface Field |
PV | Photovoltaic |
IR | Infrared |
UV | Ultraviolet |
CVD | Chemical Vapour Deposition |
PVD | Physical Vapour Deposition |
LPE | Liquid Phase Epitaxy |
ALD | Atomic Layer Deposition |
MOCVD | Metal Organic Chemical Vapour Deposition |
PECVD | Plasma Enhanced Chemical Vapour Deposition |
MBE | Molecular Beam Epitaxy |
MIS | Metal Insulator Semiconductor |
This place covers:
- Identification marks
- Nozzles for washing solar modules
- Storage details or shipping means for solar cells
- Design details, camouflage
This place does not cover:
Particular substrate for thin film solar cells | |
Particular substrate for bulk photovoltaic cells | |
Processes or apparatus peculiar to the manufacture or treatment of these devices or of parts thereof, e.g. deposition methods |
This place covers:
Details of electrical interconnection of packaging;
Arrangements being portions of the electrical connections to the devices but not being an electrode, i.e. having direct electrical contact with the body of the device.
This place does not cover:
Electrodes | |
Electrical interconnection between solar cells for thin film solar cells: | |
Electrical interconnection between solar cells for bulk solar cells |
This specific subgroup (H01L 31/02002) is only relevant if the potential barrier of the device is not mentioned, i.e. when it is not clear if the device concerned is a photoconductive or a junction device); If there is a potential junction, then H01L 31/02005, if the device is a solar cell or a solar module, then H01L 31/02008.
This place covers:
Details of electrical interconnection of packaging for devices involving a potential barrier.
This place covers:
Special electrical connections of a solar cell or a solar module, i.e. to conduct electrical current to an external load.
contact terminal 40
Attention is drawn to the following places, which may be of interest for search:
Connection between cells within a module for thin film solar cells | |
Connection between cells within a module for bulk solar cells | |
Wiring substrates, e.g. for back contacted solar cells | |
Electrical connection means, e.g. junction boxes, specially adapted for structural association with photovoltaic modules |
This place does not cover:
Electrical connection means, e.g. junction boxes, specially adapted for structural association with photovoltaic modules |
Attention is drawn to the following places, which may be of interest for search:
Circuitry associated to or formed in the module, e.g. bypass diodes associated with the serial interconnection between cells of the module | |
MPPT systems |
This place covers:
Photodetectors sensitive to the position of the light beam, for alignment
Quadrant photodiodes, i.e. 4 pixels-photodetectors - and only 4 -, for position adjustment.
This place does not cover:
Photodetectors having more than 4 pixels |
This place covers:
Specific circuitry used with avalanche photodiodes
This place covers:
Packaging aspects for single photosensitive components: Housing, transparent windows or resins.
This place does not cover:
Housing/encapsulation for photovoltaic devices | |
Containers/encapsulation for organic photosensitive devices |
Attention is drawn to the following places, which may be of interest for search:
Containers not specific to light sensitive devices (microelectronic) | |
Assemblies consisting of a plurality of individual semiconductor or other solid-state devices, e.g. the devices having separate containers | |
Optical elements or arrangements associated with semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength specially adapted for the control of electrical energy by such radiation | |
Optical elements directly associated or integrated with the PV cell | |
Light absorption and re-emission at a different wavelength by the optical element directly associated or integrated with the PV cell, e.g. luminescent sheets for up or down-conversion | |
Packaging for devices classified in groups | |
Semiconductor devices specially adapted for light emission, characterised by the semiconductor body package | |
Sealing arrangements of electroluminescent light sources | |
Encapsulation of light emitting devices |
This place covers:
Photosensitive semiconductor devices on which one or more layer(s) are directly deposited - as opposed to "optical elements" which are placed above or upon the device) - e.g. involving electrically passivating properties or optical enhancing properties.
This place does not cover:
Provisions for preventing damage caused by corpuscular radiation, e.g. for space applications |
Attention is drawn to the following places, which may be of interest for search:
Luminescent layers for photodetectors | |
Encapsulation of solar cells | |
PV devices comprising luminescent layers | |
Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof, e.g. passivation methods | |
Passivation and encapsulation of organic photosensitive devices |
If the layer is texturized, then classify in both (subgroup of) H01L 31/0216 and H01L 31/0236.
Attention is drawn to the following places, which may be of interest for search:
Coatings of integrated photosensitive devices (imagers) |
Attention is drawn to the following places, which may be of interest for search:
Colour filter arrangements of integrated photosensitive devices (imagers) |
This place covers:
Light shielding layers to protect circuitry, for instance the transistor of the pixel.
Also used to detect and subtract dark current in photodetectors.
This place does not cover:
Optical shielding of integrated devices |
Attention is drawn to the following places, which may be of interest for search:
Interference filters |
This place covers:
Passivation layer or any kind of coating protection specially adapted for photovoltaic cells.
This place does not cover:
Special textures or texturization of surfaces | |
Solar cell encapsulations |
Attention is drawn to the following places, which may be of interest for search:
Interference filters |
This place covers:
Multilayer coatings, e.g. double layer AR coatings for solar cells.
This place does not cover:
Special surface textures or texturization methods | |
Luminescent layers for solar cells |
This place covers:
Electrodes and manufacturing methods thereof.
This place does not cover:
Electrodes for organic photosensitive devices |
Attention is drawn to the following places, which may be of interest for search:
Methods for making electrodes are in | |
Methods for making a transparent electrode |
This place covers:
Electrodes or electrode structures for photodiodes, phototransistors and photoconductor devices, and the fabrication thereof.
This place covers:
Electrode structures for solar cells and fabrication methods.
This place does not cover:
Transparent electrodes (including for solar cells) | |
Interconnections between cells within a module when the cells are not integrated on the same substrate | |
Method for forming transparent electrode | |
Electrodes for photo electrochemical cells (DSSC, Grätzel type) for counter electrode |
Attention is drawn to the following places, which may be of interest for search:
Series interconnection structures of thin film solar cells in a module |
Methods for forming solar cell electrodes are classified here and not in H01L 31/18, except the method for forming transparent electrode, which is classified in H01L 31/1884.
For electrodes of thin film solar cells, double classification is made in H01L 31/022425 and H01L 31/046, but not for the series interconnection structures of thin film solar cells in a module, which is covered by H01L 31/046.
This place covers:
Specific patterns of front electrodes.
Specific transversal sections of electrodes or back electrodes are covered by H01L 31/022425.
This place covers:
Transparent electrodes for photodetectors and/or solar cells.
This place does not cover:
Method for manufacturing a transparent electrode |
Attention is drawn to the following places, which may be of interest for search:
Transparent electrodes for light emitting devices | |
Material composition, e.g. conductive oxides | |
Transparent electrodes for organic light sensitive devices |
If both method and material are relevant, then both H01L 31/022466 and H01L 31/1884.
Give this group symbol if some absorption curves or other optical properties of the TCO layers are disclosed.
This place covers:
Optical elements used for focusing, reflecting or diffracting light and associated with the photosensitive device.
This place does not cover:
Surface textures for light trapping effects | |
Optical elements for photovoltaic cells | |
Light-reflecting or light-concentrating means specially adapted for PV modules |
Attention is drawn to the following places, which may be of interest for search:
Imager structures, e.g. microlenses for CCDs |
Plasmonic structures: if part of Schottky junctions, then see H01L 31/1085 (MSM). If purely optical, then here (or H01L 31/02322)
This place covers:
Luminescent element meant for converting incident wavelengths into different wavelengths, better suited to the spectral absorption of the device (so called "up-conversion" or "down-conversion").
This place does not cover:
Luminescent element for solar cells |
This place covers:
- Surface textures specially adapted for light trapping effects, for both photodetectors and solar cell devices
- Texturization methods
Attention is drawn to the following places, which may be of interest for search:
Chemical or electrical treatment, e.g. etching, of semiconductors | |
Light emitting devices with a roughened surface |
Texturization methods are covered by this group, and not in H01L 31/18.
Corrugated surface; protrusions; projections; roughened surface; pyramidal structures (for silicon); light trapping.
This place covers:
Cooling arrangements for photodetectors
This place does not cover:
Cooling arrangements for photovoltaic devices |
Attention is drawn to the following places, which may be of interest for search:
Cooling apparatuses in general, e.g. arrangement or mounting of refrigeration units |
This place covers:
Photodetectors and solar cells having a particular semiconductor body
The "particularity" can be:
- the nature of the material (specific composition, special doping species)
- material shapes or dimensions
- the crystalline structure
This group and subgroups thereof are only used for classifying invention information, e.g. not every document dealing with group IV materials is classified H01L 31/028
This place covers:
Device characterized by the material used as active layer having a specific composition, i.e. the light absorbing semiconductor material
This place does not cover:
Materials which are not active materials | |
Manufacturing methods | |
Organic semiconductor materials |
This place covers:
Inorganic semiconductor materials forming the active part of photosensitive devices, photodetectors and photovoltaic devices
Attention is drawn to the following places, which may be of interest for search:
Organic semiconductor materials |
Attention is drawn to the following places, which may be of interest for search:
Documents relating to the Staebler-Wronski effect | |
Deposition methods of group IV materials |
This group covers only devices with specificity in the group IV material. This group symbol is not given as an index code to all documents referring to a photoelectric structure comprising group IV elements.
This place does not cover:
Porous silicon as antireflective layer for photodiodes | |
Porous silicon as antireflective layer for solar cells |
This place covers:
HgCdTe compounds having a low bandgap, e.g. for IR photodetector
This place covers:
Ternary or quaternary compounds having a specific stoichiometry, absorption spectrum or band gap
This place does not cover:
Chalcopyrite compounds characterised by the doping material | |
Chalcogenide compounds characterised by the doping material |
This place covers:
CIS and CIGS materials and deposition methods.
Attention is drawn to the following places, which may be of interest for search:
Forming chalcogenide semiconducting materials not being oxides on a substrate | |
Heterojunction solar cells including a I-III-VI active layer | |
Coating by vacuum evaporation, by sputtering or by ion implantation of sulphides, selenides or tellurides | |
Reactive treatment with sulphur or selenium after deposition |
Methods for forming CIS or CIGS are classified here, not in H01L 31/18.
This place covers:
Cu2O/CdS and Cu2S/CdS heterojunction devices
This place covers:
Photoelectric devices in which the active layer is characterized by some geometrical aspects.
The substrate or body of the device on which the active layer is formed
Devices comprising nanodots, quantum dots, quantum wires, as active material
Active layers involving quantum effects, e.g. quantum dots and intermediate band solar cells
Photoactive nanotubes or nanowires
Geometrical aspects of other parts of the device than active layer and body are classified with said other parts, e.g. electrodes | |
Semiconductor particles embedded in insulating material | |
Nanotubes or nanowires forming an heterojunction with an organic semiconductor material |
This place covers:
Photodetectors and photovoltaic cells involving superlattices or multiple quantum wells.
Attention is drawn to the following places, which may be of interest for search:
Semiconductor nanoparticles within a matrix |
Superlattices, quantum wells, MQW (multiple quantum wells), quantum dots, quantum wires, quantum boxes, nanodots, nanorods.
This place covers:
Photodetectors and also solar cells having at least one potential jump barrier.
This place covers:
Devices having special shapes of the device body, e.g. cylindrical or spherical bodies:
Fig 6 of EP1253649
This place covers:
Sawteeth, interdigitated junctions
P1005095
This place covers:
Polycrystalline semiconductors
Amorphous materials
Crystalline particles in an amorphous matrix
Metallic or insulating substrates used for thin film deposition
Particular orientation of the crystalline planes of e.g. substrates or body in the device:
Figure 1 of EP1302976
Semiconducting whiskers
This place does not cover:
Porous silicon as active material |
This place does not cover:
Thin films deposited on metallic or insulating substrates |
This place covers:
Polysilicon devices
This place does not cover:
Thin films deposited on metallic or insulating substrates |
This place covers:
Amorphous silicon devices
Attention is drawn to the following places, which may be of interest for search:
Deposition methods of amorphous silicon |
This group symbol is given, if specific aspects of amorphous material are disclosed.
This place covers:
Subject-matter which describes the Staebler-Wronski effect or aims at solving problems and drawbacks related to this effect.
This place covers:
Semiconductor particles, e.g. nanoparticles, in a dielectric matrix
Semiconductor particles, e.g. nanoparticles, in an inorganic semiconductor matrix
This place does not cover:
Semiconductor devices including thin films |
In this place, the following terms or expressions are used with the meaning indicated:
MGL | Monograin layer also called monograin membrane, i.e. powder particles embedded within a polymer membrane |
This place covers:
Thin films deposited on "cheap" substrates, e.g. glass, metal, ceramic substrates
Barrier layers used to avoid out-diffusion of impurities from said "cheap" substrates
Attention is drawn to the following places, which may be of interest for search:
I-III-VI (chalcopyrite) compounds deposited on a flexible substrate | |
II-VI materials deposition on non-semiconductor substrates | |
III-V materials deposition on non-semiconductor substrates | |
Flexible substrates for photoelectrochemical solar cells |
Classification is given with this symbol whenever a detailed substrate is described.
This place covers:
Non semiconductor substrates on which only group IV thin film devices are deposited, e.g. amorphous silicon devices on metallic or insulating substrates.
This place covers:
Semiconductor devices sensitive to light and adapted for the direct conversion of the light into electrical energy for the purpose of providing electrical energy (not for light detection purposes).
This group and subgroups do not cover organic light sensitive devices, which are covered by H10K 30/00 as expressed by the limiting reference after H01L 31/00.
This place does not cover:
Testing of PV devices during manufacture | |
Electrolytic light sensitive devices, e.g. dye sensitized solar cells | |
Testing of PV devices after manufacture | |
Organic solar cells |
Attention is drawn to the following places, which may be of interest for search:
Imager structures consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate | |
Electrodes at the cell level | |
Devices in which radiation controls flow of current through the device, e.g. photodetectors | |
Production of heat using solar radiation | |
Measurement of X-radiation, gamma radiation, corpuscular radiation or cosmic radiation with semiconductor detectors | |
Measurement of X-radiation, gamma radiation, corpuscular radiation or cosmic radiation with resistance detectors | |
Measurement of neutron radiation with semiconductor detectors | |
Couplings of light guides with optoelectronic elements | |
Arrangement for obtaining electrical energy from radioactive sources | |
Electrochemical current or voltage generators |
- The group H01L 31/04 itself only includes subject-matter where the nature of the light converting material is not clear.
- Devices including photovoltaic cells as power source, wherein the document does not disclose any structural details regarding said photovoltaic devices, should be classified in the relevant groups for said device as such.
In this place, the following terms or expressions are used with the meaning indicated:
Homojunction | pn junction involving both p and n regions made out of the same material, with the same composition and the same structure (only the doping species change). |
Heterojunction | pn junction involving two different materials, the difference lying in the crystal structure and/or the composition (example : p-type amorphous silicon / n-type crystalline silicon) |
P-i-n structure | P-N junction with thick intrinsic layer in between, whereby the intrinsic interlayer is the major part of the absorbing layer, i.e. not Heterojunction with Intrinsic Thin-layer solar cells |
Heterojunction with Intrinsic Thin-layer solar cells | P-N structures including a very thin intrinsic inter-layer, which is not the absorbing layer of the structure |
Tandem solar cell | a plurality of junctions are monolithically stacked on one another (for lateral integration, see H01L 27/142) |
Schottky contact | rectifying (non-ohmic) metal/semiconductor contact |
Group 14 elements | formerly known as Group IVA elements (C, Si, Ge, Sn, Pb) |
Conversion devices | light sensitive devices specially adapted for conversion of light into electrical energy, not for the purpose of light detection |
MIS | Metal Insulator Semiconductor |
In patent documents, the following abbreviations are often used:
a-Si, α-Si | amorphous silicon |
c-Si | crystalline silicon |
mc-Si, muc-Si | microcrystalline silicon |
poly-Si | polycrystalline silicon |
PIN, p-i-n | P-N junction with thick intrinsic layer in between |
AIBIIICVI compound | I-III-VI compound, chalcogenides, chalcopyrites |
CIS | CuInSe2 |
CIGS | CuInGaSe2 |
CIGSS | CuInGaSSe |
TCO | Transparent conducting oxide |
ITO | Indium Tin Oxide |
AZO | Aluminium doped Zinc Oxide |
GZO | Gallium doped Zinc Oxide |
QW | Quantum well |
MQW | Multiple Quantum Well |
HIT | Heterojunction with Intrinsic Thin-layer |
PERL solar cell | Passivated Emitter Rear Locally Diffused solar cell |
ARC | Anti-reflective coating |
MPPT | Maximum Power Point Tracking |
MWT | Metal Wrap Through |
FMWT | Front Metal Wrap Through |
EWT | Emitter Wrap Through |
IBC | Interdigitated Back Contact (solar cells) |
In patent documents, the following words/expressions are often used with the meaning indicated:
"solar cells" | "photovoltaic cells" |
This place covers:
- Photovoltaic devices specially adapted for space applications.
- Special features to improve the radiation resistance of the PV cell to avoid radiation damage
Attention is drawn to the following places, which may be of interest for search:
Semiconductor devices sensitive to very short wavelengths, e.g. X-rays, gamma-rays or corpuscular radiation | |
Space applications, e.g. power supply for satellites made of solar cell modules |
This place covers:
- PV cell arrays, modules or panels. The PV cells used here are normally of the crystalline-polycrystalline type (bulk cells), e.g. silicon solar cells
- Special configuration of the PV cells array,
- Special electrical connections of the PV cells in a module
- Circuitry integrated with the PV cells
- Specific dispositions or shapes of adjacent cells within the module
- Special configuration or structure of PV modules, adapted for special applications, e.g. solar hats
- Bypass diodes associated to the interconnections between cells of the module.
This place does not cover:
Supporting structures for PV modules |
Attention is drawn to the following places, which may be of interest for search:
Circuit arrangements for solar cells |
In patent documents, the following words/expressions are often used as synonyms:
- "modules" and "panels"
This place covers:
Bypass diodes in PV modules, e.g. bypass diodes for a string of PV cells in a PV module
Example:
This place does not cover:
bypass diodes in the junction box |
This place covers:
Bypass diodes in PV modules, e.g. integrated with thin film solar cells.
Example:
This place covers:
PV modules or arrays of single PV cells including inorganic thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells.
Example:
This place covers:
PV modules composed of a plurality of inorganic thin film solar cells deposited on the same substrate and electrically connected together, e.g. thin film a-Si, CIS or CdTe solar cells.
Example:
Attention is drawn to the following places, which may be of interest for search:
Method of deposition of CIS compounds | |
Thin films deposited on metallic or insulating substrates | |
Method of deposition of amorphous silicon cells | |
Roll to roll deposition of amorphous silicon device |
This place covers:
specific patterning methods (like laser trimming, chemical etching) which aims at forming a module from a plurality of (interconnected) adjacent thin film solar cells from initially continuous thin films.
Attention is drawn to the following places, which may be of interest for search:
Processes or apparatus specially adapted for the manufacture or treatment of PV cells | |
Processes or apparatus specially adapted for the manufacture or treatment of PV cells comprising amorphous semiconductor materials |
This place covers:
specific interconnection structures interconnecting adjacent thin film solar cells, e.g. insulating spacer to avoid short-circuits between cells.
Examples:
This place does not cover:
specific patterning methods to interconnect adjacent thin film solar cells in a thin film PV module |
This place covers:
Example:
This place covers:
Solar cells formed in a semiconductor substrate (bulk type) and being separated by V-grooves or having a plurality of vertical junctions.
Examples:
This place covers:
Photovoltaic cell arrays made by cells in a planar, e.g. repetitive, configuration on a single semiconductor substrate; PV cell microarrays.
Examples:
This place does not cover:
Photovoltaic modules composed of a plurality of thin film solar cells deposited on the same substrate |
This place covers:
- PV devices comprising encapsulation layers specially adapted for protecting the photovoltaic module, e.g. details of laminations, materials in-between; methods for obtaining them.
Illustrative example of subject matter classified in this place:
1.
- Housings for PV cells.
Illustrative example of subject matter classified in this place:
2.
Attention is drawn to the following places, which may be of interest for search:
Encapsulation of photodetectors or photodiodes | |
Coatings at the cell level, e.g. for passivation or antireflection | |
Back side reflectors for PV cells | |
Processes or apparatus peculiar to the manufacture or treatment of these devices or of parts thereof | |
Layered products essentially comprising sheet glass or glass | |
Synthetic resin laminates | |
Adhesives per se | |
Materials for sealing or packing joints or covers | |
Encapsulation of organic solar cells |
Attention is drawn to the following places, which may be of interest for search:
Layered sheets per se |
This place covers:
- The serial interconnection of PV cells (10) inside a PV module (100), e.g.:
- Specific interconnection materials for electrically interconnecting PV cells
- Wiring substrates for serial connection of back contacted solar cells
- Methods for interconnecting PV cells
This place does not cover:
Electrodes for PV cells | |
Electrical interconnection of thin film solar cells formed on a common substrate | |
Particular structures for electrical interconnecting of adjacent thin film solar cells in the module | |
Electrical interconnection means specially adapted for electrically connecting two or more PV modules |
This place covers:
- PV cells comprising active cooling means, e.g. peltier elements, a liquid or gaseous coolant, directly associated or integrated with the cell
- PV cells comprising passive cooling means, e.g. heat sinks, directly associated or integrated with the cell
This place does not cover:
Cooling means in combination with the PV module |
Attention is drawn to the following places, which may be of interest for search:
Cooling means using Peltier elements for semiconductor devices in general | |
Cooling means for photodetectors or photodiodes | |
Optical elements directly associated or integrated with the PV cell, e.g. light reflecting and light concentrating means | |
Thermoelectric devices operating with Peltier or Seebeck-effect only |
This place covers:
Hybrid solar devices, i.e. PV cells including means for utilising thermal energy, e.g. by using Seebeck elements
Attention is drawn to the following places, which may be of interest for search:
Using solar heat per se | |
Means to utilise heat energy directly associated with the PV module |
This place covers:
Photovoltaic devices including a battery to store electrical energy
This place does not cover:
Energy storage means associated with the PV module |
Attention is drawn to the following places, which may be of interest for search:
Accumulators structurally combined with charging apparatus | |
Circuit arrangements for charging batteries with solar cells |
This place covers:
PV cells comprising solar concentrators, lenses and reflectors, e.g. Fresnel lenses:
Attention is drawn to the following places, which may be of interest for search:
Antireflective coatings for light sensitive devices | |
Concentrating means for semiconductor photodetectors | |
Concentrators for solar heat collectors | |
Optical elements per se |
This place covers:
PV cells comprising coatings or separate members, which change the wavelengths of the incident light, making it more suitable for absorption by the associated PV cell, e.g. fluorescent concentrators:
Attention is drawn to the following places, which may be of interest for search:
Luminescent member for photodetectors, e.g. for X-ray detectors | |
Luminescent, e.g. electroluminescent, chemiluminescent materials |
In this place, the following terms or expressions are used with the meaning indicated:
Up conversion / down conversion | Incident photons are converted into photons of higher/respectively lower energies (shorter, respectively longer wavelengths). |
In patent documents, the following words/expressions are often used as synonyms:
- "photoluminescent materials"," luminescent materials" and "phosphorescent materials"
This place covers:
PV cells comprising light-reflecting means sending back the light that already went through the PV cell, e.g. an Ag electrode in order to reflect the light on the back of the PV cell.
Attention is drawn to the following places, which may be of interest for search:
Electrodes for PV cells |
When an electrode has a specific structure/composition specially adapted for acting as back surface reflector, the document should be classified in H01L 31/056 and additionally in H01L 31/022425.
Attention is drawn to the following places, which may be of interest for search:
Photovoltaic cell arrays including PV cells having multiple vertical junctions or multiple V-groove junctions formed in a semiconductor substrate |
This place covers:
Point contact solar cells:
(Fig 3 US6034321)
See for instance EP2120269.
This place does not cover:
Devices having potential barriers being of the Schottky type |
Attention is drawn to the following places, which may be of interest for search:
Electrodes for light sensitive devices as such and manufacturing methods |
Concerning the meaning of "point contact": the point contact in this group must be ohmic.
This place covers:
Photovoltaic devices where the potential barrier consists in a metal-insulator-semiconductor (MIS) structure:
(US2006102972)
Attention is drawn to the following places, which may be of interest for search:
Photodetectors being of the conductor-insulator- semiconductor type, e.g. having a MIS structure |
MIS: Metal - Insulator - Semiconductor; Tunnel (contact, oxide, structure,...)
Inversion layers; Field effect.
This place covers:
Photovoltaic devices where the absorbing part of the device involves a layer with a graded bandgap:
When classifying in H01L 31/065 (graded bandgap), subject matter related to the junction type is additionally classified in the corresponding other subgroups provided for under H01L 31/06.
Example: Solar cells having a p-i-n structure with a graded band gap intrinsic region, are classified in H01L 31/065 and additionally in H01L 31/075.
This place covers:
Photovoltaic devices where the potential barrier is a p-n junction involving one single material (same composition and same crystal structure) with different dopants (so called "homojunction"). This group covers mostly silicon homojunction p-n solar cells.
Example of bulk silicon solar cell:
Example of thin film solar cell:
Attention is drawn to the following places, which may be of interest for search:
Devices having potential barriers being only of the PN heterojunction type, e.g. a-Si / c-Si solar cell | |
Photodetectors with p-n-homojunction structure | |
Methods for manufacturing homojunction solar cells |
All homojunction solar cells are classified in H01L 31/068 and additionally in H01L 31/0236, H01L 31/0224, H01L 31/02167, and H01L 31/02168, whenever appropriate.
Multiple homojunctions are covered by H01L 31/0687, unless one of the junctions is of special interest as such. In that case, the subject matter is additionally classified in H01L 31/068.
Amorphous silicon is not considered to be the same material as crystalline silicon, because a-Si and c-Si have a different crystal structure, and a different band gap. An a-Si / c-Si structure is, therefore, considered a heterojunction, which are covered by H01L 31/072.
This place covers:
Tandem homojunction solar cells, i.e. a plurality of homojunction cells deposited on one another so as to form a single integrated photovoltaic structure, each cell having a different bandgap and thus a different spectral sensitivity. Tunnel junctions between cells usually ensure the electrical connection and the current flow between the cells.
(Fig 1 of EP1469528)
- stacked solar cells, meaning different solar cells mechanically stacked on one another, not integrated as a single structure: H01L 31/043, see figure below)
This place does not cover:
Stacked solar cells (see figure above), i.e. different solar cells mechanically stacked on one another, not integrated as a single structure. |
Attention is drawn to the following places, which may be of interest for search:
Solar cells laterally integrated on a common substrate | |
Heterojunctions tandem solar cells | |
p-i-n tandem solar cells | |
Tandem solar cells comprising sub-cells each having a different kind of potential barrier |
III-V (homojunction) tandem solar cells are classified both in H01L 31/0687 and additionally in H01L 31/0693, if all the cells of the tandem structure are III-V homojunction cells.
This place covers:
Photovoltaic PN homojunction devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. n-GaAs / p- GaAs.
Space solar cells, concentrator solar cells
Attention is drawn to the following places, which may be of interest for search:
III - V heterojunctions solar cells, i.e. solar cells involving two different III-V materials within one junction |
III-V (homojunction) tandem solar cells are classified both in H01L 31/0687 and additionally in H01L 31/0693, if all the cells of the tandem structure are III-V homojunction cells.
This place covers:
Photovoltaic devices where the junction consists in a Schottky barrier (rectifying metal-semiconductor junction).
Attention is drawn to the following places, which may be of interest for search:
Photodetectors with Schottky structure |
In this place, the following terms or expressions are used with the meaning indicated:
Schottky contact | metal-semiconductor structure involving a potential barrier (that is, not ohmic).The Schottky metal is both a part of the junction and an electrode. |
This place covers:
Photovoltaic devices where the junction consists in a p-n structure involving two different materials (compositionally and/or structurally), thereby forming a so called heterojunction.
The different heterojunctions types are dispatched in the subgroups H01L 31/072 and subgroups and H01L 31/0336 and subgroups.
This place does not cover:
P-i-n solar cell structures |
Attention is drawn to the following places, which may be of interest for search:
Materials of the semiconductor bodies | |
Heterojunction photodetectors |
This place covers:
Tandem heterojunction solar cells, i.e. photovoltaic structures consisting of a plurality of heterojunctions cells (and only heterojunction solar cells) deposited on one another so as to form a single integrated photovoltaic structure, each cell having normally a different bandgap and a different spectral sensitivity.
This place does not cover:
Stacked solar cells, i.e. different solar cells mechanically stacked on one another, not integrated as a single structure |
Attention is drawn to the following places, which may be of interest for search:
Solar cells laterally integrated on a common substrate | |
Tandem homojunction solar cells | |
P-i-n tandem solar cells | |
Tandem solar cells comprising sub-cells each having a different kind of potential barrier |
This place covers:
Heterojunction photovoltaic device wherein the heterojunction barrier consists in two different II-VI compound materials.
Attention is drawn to the following places, which may be of interest for search:
II-VI heterojunction photodetectors |
This place covers:
Heterojunction photovoltaic devices wherein the heterojunction consists in two different III-V compound materials.
Attention is drawn to the following places, which may be of interest for search:
III-V heterojunction photodetectors |
This place covers:
Heterojunction photovoltaic devices wherein the heterojunction consists in two different materials, only one of them being silicon or another Group IV element or alloy.
Attention is drawn to the following places, which may be of interest for search:
Heterojunction comprising only Group IV materials | |
III-V heterojunction photodetectors |
In this place, the following terms or expressions are used with the meaning indicated:
Group IVA is also referred to as Group 14 (new nomenclature).
This place covers:
Heterojunction photovoltaic devices wherein the heterojunction barrier consists in two different group IV materials (elements or alloys).
Attention is drawn to the following places, which may be of interest for search:
AIV/BIV heterojunction photodetectors |
In this place, the following terms or expressions are used with the meaning indicated:
Group IVA is also referred to as group 14 (new nomenclature).
This place covers:
Heterojunction photovoltaic devices wherein the heterojunction barrier consists in two different group IV materials with different crystalline structures (with or without a thin intrinsic interlayer in-between).
Illustrative example of the subject matter classified in H01L 31/0747:
Attention is drawn to the following places, which may be of interest for search:
P-i-n solar cells with the intrinsic part composed of one amorphous sublayer and one microcrystalline sublayer, both being absorption layers (meaning of similar thicknesses) | |
AIV/BIV heterojunction photodetectors |
This place covers:
- Heterojunction photovoltaic devices wherein the heterojunction barrier includes at least one I-III-VI compound
This place covers:
- Photovoltaic devices wherein the potential barrier consists of a p-i-n structure, the intrinsic layer being the light absorbing layer.
Illustrative example of the subject matter classified in H01L 31/075:
Most solar cells having p-i-n structure are made of a-Si with a thicker i layer between thinner p and n layers.
Attention is drawn to the following places, which may be of interest for search:
Photodetectors with p-i-n structure |
p-n structures including a very thin intrinsic inter-layer, which is not the absorbing layer of the structure are considered to be PN heterojunctions, which are covered by group H01L 31/0747.
If all p, i and n layers are crystalline, i.e. poly- or monocrystalline, not microcrystalline, then H01L 31/077.
This place covers:
- Tandem p-i-n solar cells, i.e. a plurality of p-i-n structures deposited on one another so as to form a single integrated photovoltaic structure, each cell having normally a different bandgap and therefore different spectral sensitivity.
This place does not cover:
Stacked solar cells (see figure below), i.e. different solar cells mechanically stacked on one another, not integrated as a single structure. |
Attention is drawn to the following places, which may be of interest for search:
Solar cells laterally integrated on a common substrate | |
Tandem solar cells comprising sub-cells each having a different kind of potential barrier | |
Multiple wavelength photodetectors | |
P-i-n photodetectors |
This place covers:
Photovoltaic p-i-n structures wherein at least one of the active layers is crystalline.
Attention is drawn to the following places, which may be of interest for search:
Mechanically stacked on one another | |
P-n structure with very thin intrinsic interlayer which does not act as the absorbing region of the structures | |
Photodetectors with p-i-n structure |
This place covers:
Tandem solar cells with different junction types, e.g. one p-i-n sub-cell and one heterojunction sub-cell integrated on one another. Normally, all type of tandem solar cells which are not classified in H01L 31/0687, H01L 31/0725 or H01L 31/076).
Normally, all types of tandem solar cells which are not classified in H01L 31/0687, H01L 31/0725 or H01L 31/076 are classified here.
This place covers:
Photosensitive devices specially adapted for detection of photons.
Photoconductors devices not having a potential barrier Photodetection devices involving one or more potential barriers, e.g. photodiodes, phototransistors
All wavelengths, i.e. terahertz (far IR), IR, visible, UV, X rays, gamma, corpuscular radiation is covered.
Attention is drawn to the following places, which may be of interest for search:
Integrated photosensitive devices (imagers) | |
Pyrometry (infrared radiation measurements) | |
Photometry | |
Sensors for corpuscular radiation, X-rays or gamma rays as a whole (including circuitry) |
In this place, the following terms or expressions are used with the meaning indicated:
Photoconductive | the electrical conductivity of the material changes when light is absorbed by said material |
This place covers:
Photoconductive devices, involving no junction, sensitive to very short wavelengths.
Attention is drawn to the following places, which may be of interest for search:
Photodiode arrays sensitive to short wavelength | |
Photoconductor arrays sensitive to short wavelengths | |
Solar cells | |
Devices sensitive to infrared, visible or UV light | |
Measuring radiation intensity of very short wavelengths radiations with semiconductor devices |
This place covers:
Photoconductive devices, involving no junction, sensitive to infrared, visible and UV light.
This place does not cover:
Devices comprising at least one potential jump barrier, e.g. photodiodes | |
Bipolar phototransistors | |
Photothyristors | |
Field effect phototransistors |
Attention is drawn to the following places, which may be of interest for search:
Solar cells | |
Photoconductive devices sensitive to wavelengths not being IR, visible or UV, i.e. being very short wavelength and corpuscular radiations | |
Photodiodes sensitive to wavelengths not being IR, visible or UV, i.e. being very short wavelength and corpuscular radiations | |
Radiation pyrometer using semiconductor devices |
This place covers:
Photodetecting devices for IR, visible and UV and very short wavelength or particles, comprising at least one potential barrier, e.g. p-n homojunction, heterojunction, Schottky junction, p-i-n structure
Photodiodes (one barrier)
Bipolar photo transistors (two barriers)
Photo thyristors (three barriers)
Field effect photo transistors (junction or MIS transistors).
Attention is drawn to the following places, which may be of interest for search:
Integrated devices, e.g. imagers | |
Photoconductors | |
Photometry using radiation detectors | |
Radiation pyrometer using semiconductor devices | |
Photometry (not just the photosensitive semiconducting part, but also circuitry and other aspects of sensors) | |
Radiation sensors (not just the photosensitive semiconducting part, but also circuitry and other aspects of sensors) | |
Semiconductor radiation intensity detectors, e.g. for very short wavelengths | |
Measuring spatial distribution of X-rays or nuclear radiations with semiconductor detectors | |
Semiconductor neutron detector |
This place covers:
Multijunction photodetectors,eg. multispectral photodiodes
Attention is drawn to the following places, which may be of interest for search:
Multicolour (multispectral) imagers with stacked pixels |
Attention is drawn to the following places, which may be of interest for search:
Photodiode integrated with other components (for instance the transistor in a pixel) | |
P-n homojunction solar cells |
In case the photosensing part (pixel) of an integrated device (imager) is described and considered to contain important features, the document is also classified in H01L 31/10 and subgroups.
This place covers:
Devices including light emitting source(s) as well as photodetector(s) on a common substrate. This specific code is used when it is unclear which device controls the other (emitting device controls photosensitive device or the other way round).
Attention is drawn to the following places, which may be of interest for search:
Assemblies of opto-electronic devices (not integrated on the same substrate, only juxtaposed, and not electrically nor optically coupled) | |
Semiconductor devices having potential barriers, specially adapted for light emission | |
Coupling light guides with opto-electronic elements | |
Amplifiers using electroluminescent element or photocell | |
Electronic switching using opto-electronic devices | |
Optical interconnects | |
Electroluminescent light sources per se | |
Combination of organic light sensitive components with organic light emitting components, e.g. optocoupler |
This place covers:
Devices wherein the light source is an electroluminescent element, e.g. a LED device.
This place covers:
Devices wherein the signal from the photodetector is used for controlling the emission of light from the light source.
Details of containers and/or encapsulation for these devices (including light source(s) and photodetector(s) are only classified here, not in H01L 31/0203).
This place covers:
Combinations of LED and photodiode, both devices optically coupled, when the signal from the photodiode controls the light emission from the LED.
This place covers:
Integrated combinations of LED and photodiode in/on the same substrate, both devices optically coupled, when the signal from the photodiode controls the light emission from the LED
This place covers:
Devices, wherein the light from the light source is sent to the photodetector which gives an electrical signal.
Attention is drawn to the following places, which may be of interest for search:
Assemblies of opto-electronic devices, not being integrated on the same substrate, only juxtaposed | |
Proximity sensors | |
Coupling light guides with opto-electronic elements | |
Electronic switching or gating using opto-electronic devices |
Details of containers and/or encapsulation for these devices (including light source(s) and photodetector(s) are only classified here, not in H01L 31/0203).
Attention is drawn to the following places, which may be of interest for search:
Testing of photovoltaic devices, e.g. of PV modules or single PV cells |
This place covers:
Deposition, etching, patterning, doping of group IVA (group 14) elements or alloys as parts of photosensitive devices.
Attention is drawn to the following places, which may be of interest for search:
Etching, cleaning, patterning of semiconductors outside the specific context of photosensitive devices | |
Deposition of semiconductors outside the specific context of photosensitive devices | H01L 21/02104, C23C 16/00, C23C 14/00, C23C 18/00, C30B,... |
Heat treatments, e.g. dopant activation, crystallization |
If the device obtained by the method is of particular interest, then the document is additionally classified in the relevant device groups H01L 31/06, H01L 27/142, or H01L 31/08.
This place covers:
Deposition, etching, patterning, doping of group II-VI compounds as parts of photosensitive devices
Attention is drawn to the following places, which may be of interest for search:
Processes relating to semiconductor devices per se |
This place covers:
Deposition, etching, patterning, doping of group III-V compounds as parts of photosensitive devices.
Attention is drawn to the following places, which may be of interest for search:
Processes relating to semiconductor devices per se |
This place covers:
Post-treatment of (non-amorphous) photosensitive devices or of materials within photosensitive devices (possibly before final completion of the device).
This place does not cover:
Post-treatment specific to amorphous semiconductors, wherein the final film is still amorphous after the treatment |
Attention is drawn to the following places, which may be of interest for search:
Crystallisation or recrystallisation of non-monocrystalline semiconductor materials per se | |
Thermal treatment for modifying the properties of semiconductor bodies per se |
This place covers:
Heat treatments of the deposited layers or of the devices
This place does not cover:
Recrystallization |
Attention is drawn to the following places, which may be of interest for search:
Thermal treatment for modifying the properties of semiconductor bodies per se | |
Selenization in I-III-VI chalcopyrite semiconductor layer formation |
If the treatment is done during the formation of the semiconductor layers, the annealing is not considered to be a "post treatment" and these processes details are classified in groups dealing with the formation of the semiconductor layers.
This place covers:
After-treatments for passivation
Attention is drawn to the following places, which may be of interest for search:
Coating deposition |
This place covers:
Crystallization processes and recrystallisation processes: the starting layer being in polycrystalline or amorphous state, after the treatment being then in mono- or polycrystalline state, e.g. crystallization of amorphous layers.
Attention is drawn to the following places, which may be of interest for search:
Film crystallization as such (not specific to photosensitive devices) | |
Particular post-treatment of the devices, wherein the layers after the treatment are still amorphous |
This place covers:
Apparatus and processes in which a plurality of substrates or devices are simultaneously processed.
Attention is drawn to the following places, which may be of interest for search:
Apparatuses not specific to the fabrication of solar cells or photodetecting devices |
This place covers:
Stringer devices, for automatic soldering of interconnecting tabs to solar cells (of bulk type) for series connections
This place covers:
Methods for manufacturing transparent electrodes.
Attention is drawn to the following places, which may be of interest for search:
Electrode material or optical/electrical properties of transparent electrodes | |
Transparent electrodes for semiconductor light emitting devices LEDs | |
Conductive materials, e.g. oxides | |
Transparent electrodes for organic devices |
This place covers:
Apparatuses and methods specific to amorphous semiconductor materials
This place does not cover:
Apparatuses and methods relating to microcrystalline silicon |
Attention is drawn to the following places, which may be of interest for search:
Crystallization of amorphous layers |
Microcrystalline is not considered amorphous for purposes of classification.
This place covers:
Methods for depositing elements of the fourth group of the Periodic System, e.g. amorphous silicon.
For methods aimed at decreasing the Staebler-Wronski effect, classification is additionally made in H01L 31/03767.
This place covers:
Methods or specific apparatuses for processing a plurality of devices on a substrate, e.g. multi-chamber deposition of p-i-n amorphous silicon solar modules and roll to roll processes.
This place covers:
Methods to recover short-circuit defects in amorphous silicon solar cell modules.
This place covers:
Light emitting diodes [LEDs] or superluminescent diodes [SLDs], including LEDs or SLDs emitting infrared [IR] light or ultraviolet [UV] light.
The subgroup H01L 33/48 covers elements in intimate contact with the semiconductor body or integrated with the package.
This place does not cover:
Devices consisting of a plurality of monolithically integrated LED components or of LED components monolithically integrated with other semiconductor components | |
Semiconductor lasers | |
Organic light emitting diodes [OLEDs] or polymer light emitting diodes [PLEDs] |
Attention is drawn to the following places, which may be of interest for search:
Hybrid assemblies of a plurality of individual LED devices | |
Hybrid assemblies of LED devices with other semiconductor devices | |
Compositions of polymers for encapsulating LEDs | |
Photoluminescent materials per se | |
Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers | |
Couplings of planar or plate-like light guides with LEDs | |
Couplings of light guides with optoelectronic elements | |
Liquid crystal display backlights using LEDs | |
Electroluminescent light sources per se | |
Circuit arrangements for LEDs |
When classifying in the subgroup H01L 33/18 or H01L 33/40, classification is also made in group H01L 33/26 in order to identify the chemical composition of the light emitting region.
Apparatus specially adapted for the manufacture of LEDS or parts thereof is classified together with the corresponding processes in groups H01L 33/005 and H01L 2933/00.
In this place, the following terms or expressions are used with the meaning indicated:
active region | Includes the active junction and immediately adjacent P and N layers, e.g. light emitting layer, confining layer, cladding layer, spacer layer, etc. |
light emitting region | Synonymous with "active region" |
heterojunction | Interface between dissimilar semiconductor crystal having different band gaps. |
graded | The gradual change of the composition or doping level. |
superlattice | A periodic arrangements of layers of different material or doping types. E.g. InGaN/GaN/ InGaN/GaN superlattice, p/n/p/n superlattice, MQW, etc. |
coating | One or more layers, which are formed essentially conformally on at least a portion of a device, and which are directly associated with the semiconductor or solid state body. Coatings typically have passivation or optical characteristics and function more than merely a physical barrier. |
encapsulation | One or more layers, typically comprising epoxy material, which at least partially enclose a device. An encapsulation is often used to hermetically seal the device. |
container | A solid construction in which a device is placed, or which is formed around the device, and which forms a part of a packaged device. A container requires a partial or total enclosure, but does not require a bottom. A container may also contain a filling within the container. |
Intrinsic region or layer | Semiconductor region or layer that is undoped or not intentionally doped such that the electron and hole densities are approximately equal. |
In patent documents, the following abbreviations are often used:
LED | Light Emitting Diode |
SLD | Super Luminescent Diode |
IR | Infrared |
UV | Ultraviolet |
LCD | Liquid Crystal Display |
PCB | Printed Circuit Board |
MQW | Multiple Quantum Well |
SQW | Single Quantum Well |
This place covers:
Light emissive devices characterized by their operation, e.g. field effect, low coherence emission, barrier structure or junction structure.
Attention is drawn to the following places, which may be of interest for search:
Light emitting devices based on quantum effects |
This place covers:
Light emissive devices including at least one p-n junction (e.g. p-n, p-i-n, p-p--n, p-n--n) or hi-lo junction (e.g. n-/n+ or p-/p+), e.g. single p-n junctions or hi-lo homo-junctions.
Illustrative examples:
[n-type layer 10, insulating layer 11, p-type layer 12]
This place covers:
Light emissive devices characterized by an intrinsic region or layer between a p-doped region and an n-doped region.
Attention is drawn to the following places, which may be of interest for search:
Light emissive devices with quantum effect active region |
This place covers:
Light emissive devices having two or more p-n junctions within a single device. Examples include: light emitting bipolar transistors, light emitting thyristors, commonly addressed multi-spectral light emissive devices, and multi-junction light emissive diodes having multiple junctions addressed by a common anode and cathode.
Illustrative examples:
Attention is drawn to the following places, which may be of interest for search:
Light emissive semiconductor bodies having two or more light emitting regions |
This place covers:
Light emissive devices characterized by a heterojunction or a homojunction having a graded energy gap.
Attention is drawn to the following places, which may be of interest for search:
Processes relating to the semiconductor material of light emitting regions | |
Semiconductor body details of light emissive devices |
This place covers:
Heterojunctions or graded gap homojunctions wherein all constituent semiconductor materials are Group III-V compounds.
Attention is drawn to the following places, which may be of interest for search:
Processes relating to light emissive devices with III-V compounds in the active region | |
Group III-V compounds in the light emitting region |
This place covers:
Heterojunctions or graded gap homojunctions wherein all constituent semiconductor materials are Group II-VI compounds.
Attention is drawn to the following places, which may be of interest for search:
Processes relating to light emissive devices with II-V compounds in the active region | |
Group II-VI compounds in the light emitting region |
This place covers:
Light emissive devices including a Schottky barrier junction formed between a Schottky metal and a semiconductor.
Illustrative example:
[Schottky electrode 15]
Attention is drawn to the following places, which may be of interest for search:
Electrode materials of light emissive devices |
This place covers:
Light emissive devices having a metal-insulator-semiconductor barrier at one of the anode or cathode.
Illustrative examples:
[substrate 1, metal oxide 4, conductive layer 5]
This place covers:
Light emissive devices operated by using field-effect, wherein the conductivity of a region is altered by the application of an external electric field. Examples include light emitting MIS gated transistors or light emitting gated diodes.
This place covers:
Broadband light emitting diodes having an optical cavity that generates amplified spontaneous emission, said emission is incoherent or has low coherence. A superluminescent diode is characterized by at least one wave guiding structure that suppresses coherence emission.
Illustrative example:
[AR coatings 21, waveguide bodies 32, 42]
Attention is drawn to the following places, which may be of interest for search:
Shape of light emitting regions | |
Anti-reflective coatings |
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Processes specially adapted for the manufacture or treatment of light emissive devices covered by this main group.
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Processes specially adapted for the manufacture of light emitting devices comprising group IV elements or compounds with or without impurities in the active region.
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Processes specially adapted for the manufacture of light emitting devices comprising amorphous group IV elements or compounds with or without impurities in the active region.
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Processes specially adapted for the manufacture of light emitting devices comprising group III-V compounds with or without impurities in the active region.
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Processes specially adapted for the manufacture of light emitting devices comprising group III-V compounds with or without impurities in the active region and wherein the substrate is not a group III-V compound, e.g. GaN grown on a sapphire growth substrate.
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Processes specially adapted for the manufacture of light emitting devices comprising group III-V nitride compounds with or without impurities in the active region wherein the substrate is not a group III-V compound e.g. sapphire growth substrate.
This place covers:
Processes specially adapted for the manufacture of light emitting devices comprising group III-V nitride compounds with or without impurities in the active region.
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Processes specially adapted for the manufacture of light emitting devices comprising group II-VI compounds with or without impurities in the active region.
This place covers:
Processes specially adapted for the manufacture of light emitting devices comprising group II-VI compounds with or without impurities in the active region wherein the substrate is not a group II-VI compound, e.g. ZnO grown on sapphire growth substrate.
This place covers:
Processes specially adapted for the manufacture of light emitting devices comprising group IV-VI compounds with or without impurities in the active region.
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Wafer bonding or at least partial growth substrate removal from light emissive devices.
This place covers:
- Front end of line treatments or processes, e.g. annealing, encapsulating, wafer level testing or repairing.
- Singulation of a wafer into individual light emissive devices.
This place covers:
Light emissive devices having a particular semiconductor body, and structures or layers that directly influence the light emissive region, e.g. all layers and structures in the current path or directly influencing the semiconductor body, e.g. permanent buffer or stress relaxation layers.
The "particularity" can be:
- the nature of the material (specific composition, special doping species, crystal structure or orientation)
- shape, disposition or dimensions
- inclusions, defects and dislocations
This place covers:
Details regarding the presence or distribution of imperfections, inclusions, dislocations, voids, defects, or particular doping profiles within the semiconductor body.
Illustrative example:
[V-defects 300 and threading dislocations 560 in luminous active layer 550 and semiconductor layers 540, 520]
[p-cladding layer 8, low-doped p-type layer 9, p-contact layer 10 and the associated impurity concentration]
This place covers:
Structures creating a quantum effect within the semiconductor bodies, e.g. tunnelling barriers, quantum wells, super-lattices or similar nanostructures, which create a quantum effect.
The quantum effect structures are within the semiconductor body, but do not need to be in the light emitting region.
Illustrative example:
[superlattice 120 formed between n-type cladding layer 119 and light emitting region 130]
This place covers:
Structures creating a quantum effect within the light emitting regions.
Illustrative example:
[light emitting region 130 being a multiple quantum well including intrinsic region 33 and surrounding n-type region 33n and p-type region 33p]
This place covers:
Light emitting devices with semiconductor bodies having two or more light emitting regions, wherein light emitting regions are not individually addressable.
This place does not cover:
Monolithically integrated arrays of individually addressable light emissive devices |
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Light reflecting structures that directly influence the semiconductor body.
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Resonant cavity structures that directly influence the semiconductor body.
Illustrative example:
[DBR 79 and DBR 78 create a resonant cavity within the semiconductor body]
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Stress relaxation structures, layers or films directly influencing the semiconductor body, e.g. lattice matching or stress relaxation between growth substrates and layers deposited thereon.
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Regions, structures or layers directly influencing the semiconductor body that modify the carrier path, impede or enhance carrier mobility, e.g. carrier transport, blocking or injection layers.
H01L 33/14 is used for carrier transport layers and carrier injection layers.
This place covers:
Regions, structures or layers directly influencing the semiconductor body, which reduce carrier mobility or redirect current path.
This place covers:
Crystal structures, porosity, polarity or crystal orientation of semiconductor bodies.
H01L 33/16 is used for particular crystal structure, orientation, porosity or polarity of semiconductor body regions outside the light emitting region.
This place covers:
Crystal structures, porosity, polarity or crystal orientation of light emitting regions.
This place covers:
Shape of semiconductor bodies, e.g. surface roughness, periodic interfaces or nanostructures.
H01L 33/20 is used for particular shape of semiconductor body regions outside of the light emitting region.
This place covers:
Roughened surface or roughened interface on or within the semiconductor bodies.
Illustrative example:
[n-conducting region 1 has a roughening 101 produced on its outer surface]
Attention is drawn to the following places, which may be of interest for search:
Scattering means formed in or on the semiconductor bodies or semiconductor body packages |
This place covers:
Particular shape of the light emitting region or within the light emitting region, e.g. interface or junction, wherein the shape is periodic and ordered and not a roughened surface with random order and structure.
Illustrative example:
[light emitting region comprising first semiconductor layer 300, active layer 400 and second semiconductor layer 500, having a particular shape, specifically second semiconductor layer 500]
Attention is drawn to the following places, which may be of interest for search:
Roughened surfaces |
Particular patterns for optical field shaping in or on the semiconductor body are additionally classified in indexing subgroup H01L 2933/0083.
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Material of the light emitting region being only group II-VI compounds with or without impurities.
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Dopants specially adapted for group II-VI compound semiconductors, forming part of the light emitting region.
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Material of the light emitting region being only group III-V compounds with or without impurities.
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Dopants specially adapted for group III-V compound semiconductors, forming part of the light emitting region.
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Material of the light emitting region being group III-nitride compounds with or without impurities.
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Dopants specially adapted for the group III-nitride compounds.
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Material of the light emitting region being only group IV materials with or without impurities.
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Dopants specially adapted for the group IV materials.
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Material of the light emitting region containing porous silicon.
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Electrodes for inorganic light emissive devices; methods of their manufacturing.
Processes related to the making of electrodes are classified as additional information in H01L 2933/0016.
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Electrodes with a particular shape or disposition.
This place covers:
The electrodes of a light emitting device extending from at least a surface of the semiconductor body at least to an internal region of the semiconductor body and being surrounded by the semiconductor body.
Illustrative example:
[electrode 70 extends into the semiconductor body]
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Light emitting devices where at least one of the anode and cathode is formed along a side surface of the semiconductor body.
Illustrative examples:
[electrode including a reflective layer 70 and an additional conductive layer 82 extends to cover a side surface of the semiconductor body]
[electrode 18 formed on the side of semiconductor layer 12]
This place covers:
Electrode structures having at least two segments connected together by another separate electrode.
Illustrative examples:
[a plurality of electrode regions 850 are in direct contact with the semiconductor body including p-type region 840 and are electrically interconnected by conductive layer 860]
[plurality of electrodes 250 commonly connected to electrode 241 through conductive layer 242]
This place covers:
Materials of electrodes of light emissive devices.
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Reflective electrodes for light emissive devices.
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Transparent electrodes for light emissive devices.
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Coatings that are not reflective, e.g. passivating coating.
Processes related to the making of coatings are classified as additional information in H01L 2933/0025.
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Coatings that are reflective, e.g. dielectric Bragg reflectors, metallic coatings.
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Reflective structures consisting of two or more mirrors with varying reflectivity that improve (narrow) the linewidth and spectral purity of the emission having incoherence or low coherence, without promoting or generating stimulated lasing emission.
This place covers:
"First-level" packaging elements such as a containers, encapsulation, wavelength conversion elements, optical field shaping elements, electrical arrangements, or heat extraction or cooling elements, which are structurally associated with the semiconductor bodies, electrodes, or coatings of the light emitting devices.
Attention is drawn to the following places, which may be of interest for search:
Details of a semiconductor or other solid state device in general | |
Details of an organic light emitting device |
Processes related to the semiconductor body packages are classified as additional information in H01L 2933/0033, H01L 2933/0041, H01L 2933/005, H01L 2933/0058, H01L 2933/0066, and H01L 2933/0075.
This place covers:
Enclosures forming part of the packaged devices, which essentially have a rigid construction, into which the body of the light emitting device is placed. It is often used as a physical protection structure. The enclosures may include a structure with a recess for receiving the light emitting device, a lid or a cover. The recesses may contain a filling, encapsulant or wavelength conversion material.
Illustrative example:
[Can-type package for light emitting device 1 comprises base 2, cup 3, pins 4, and cap 5. Pins 4 are adapted to be inserted into holes in a substrate]
Attention is drawn to the following places, which may be of interest for search:
Containers for a semiconductor or other solid state devices in general | |
Assembly of semiconductor or solid state devices not having separate containers | |
Assembly of semiconductor or solid state devices with separate containers | |
"Second level" base or cap for electric lamps, the electric lamp using a semiconductor device as a light generating element | |
"Second level" housing for electric lamps, the electric lamp using a semiconductor device as a light generating element | |
Housings for semiconductor laser | |
Semiconductor laser with a Can-type housing | |
Containers for organic light emitting devices | |
Sealing arrangements for organic light emitting devices |
This place covers:
Containers that are specially adapted for being mounted, e.g. soldered, onto the surface of another element, e.g. circuit boards.
Illustrative examples:
[container comprises package body 411 and leads 415 and 416 which are bent to allow for surface mounting of the package]
[container comprises casing 12 and leads 16 and 26 which are adapted for surface mounting to substrate 94 by soldering]
This place covers:
Luminescent elements formed in or on light emitting device packages, meant for converting an emitted wavelength into a different wavelength. The elements often comprise wavelength conversion materials, e.g. phosphorescent or fluorescent materials, and a matrix material, e.g. a binder material.
Attention is drawn to the following places, which may be of interest for search:
Coatings | |
Encapsulations | |
Encapsulations or coatings for organic light emitting devices |
Processes related to the making of wavelength conversion elements are classified as additional information in H01L 2933/0041.
This place covers:
Wavelength conversion elements characterized by a specific material, a specific material composition, or specific function of the material, including constituents of the wavelength conversion element which are not wavelength conversion materials, e.g. binder.
Attention is drawn to the following places, which may be of interest for search:
Polymer compositions in general | |
Use of a particular material as a binder |
This place covers:
Wavelength conversion elements characterized by a specific wavelength conversion material, e.g. a specific phosphor or fluorescent material, or a specific function of a wavelength conversion material.
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Wavelength conversion elements characterized by two or more wavelength conversion materials, e.g. two or more specific phosphor or fluorescent materials. The wavelength conversion materials may be in the same layer or in distinct layers.
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Wavelength conversion elements characterized by their shape.
Illustrative examples:
[wavelength conversion element 4 for light emitting device 2 is characterized by a vertically long triangular shape]
[wavelength conversion element 104 for light emitting device 102 is characterized by the non-uniform shape of the top surface 108]
[wavelength conversion element 234 for light emitting element 22 is characterized by the patterned microstructures shape 231]
Attention is drawn to the following places, which may be of interest for search:
Encapsulation having a particular shape | |
Field shaping elements, which are not wavelength conversion elements |
This place covers:
Wavelength conversion elements, which are not in intimate contact with, e.g. spaced away from, the light emitting devices, e.g. remote phosphor configuration.
Attention is drawn to the following places, which may be of interest for search:
"Second level" wavelength conversion means for electric lamps, the electric lamp using a semiconductor device as a light generating element |
This place covers:
Wavelength conversion elements not having a uniform concentration.
Examples include wavelength conversion elements, in which the wavelength conversion material, e.g. phosphorescent or fluorescent material, has a concentration gradient within the binder material (i.e. matrix material).
This place covers:
A sealing material in direct contact with and formed on the light emitting devices. An encapsulation may contain one or more layers and is primarily used as physical protection for the light emissive device.
Attention is drawn to the following places, which may be of interest for search:
Process for the manufacture of an encapsulation of solid state devices in general | |
Encapsulation of solid state devices in general | |
Process relating to encapsulation | |
Shaping of a plastic by casting | |
Encapsulation for organic light emitting devices |
Processes related to encapsulations are classified as additional information in H01L 2933/005.
This place covers:
Encapsulation characterized by their shape.
Illustrative examples:
[encapsulation 400 is characterized by a lens shape]
[encapsulation 3 is characterized by the shape of the textured and tapered sidewalls]
Attention is drawn to the following places, which may be of interest for search:
Wavelength conversion elements characterized by their shape | |
Element that provides field shaping element (e.g. due to its shape) that is not an encapsulation |
This place covers:
An encapsulation characterized by its material.
Attention is drawn to the following places, which may be of interest for search:
Polymer compositions in general | |
Use of a particular material as a binder for fluorescent particles |
This place covers:
Elements formed in or on light emitting device packages that are specially adapted for altering the path of the light emitted from the light emitting device.
Examples include lenses, refractors, diffraction gratings, matrix including scattering particles, diffuser, prism, or shader.
Attention is drawn to the following places, which may be of interest for search:
Scattering means in or on the semiconductor bodies or the semiconductor body packages | |
"Second level" optical arrangements for electric lamps, the electric lamp using a semiconductor device as a light generating element | |
Refractors for light sources of lens shape | |
Optical elements in general, e.g. lenses | |
Arrangements for extracting light from organic light emitting devices | |
Arrangements for contrast improvement of organic light emitting devices |
The optical field shaping element must be a "first level" optical element. "Second level" optical elements are classified in F21K 9/00 or G02B.
Periodic patterns for optical-field shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures are classified as additional information in H01L 2933/0083.
Processes related to the manufacturing of optical field-shaping elements are classified as additional information in H01L 2933/0058.
This place covers:
An optical field shaping element which is reflective.
Attention is drawn to the following places, which may be of interest for search:
Reflective means for extracting light for organic light emitting devices |
This place covers:
Electrical arrangements of "first-level" package elements, conducting electric current to or from an electrode of the light emitting device.
Examples include lead frames, insulating substrates with metallization layers thereon, solder balls, or a wire bond.
Attention is drawn to the following places, which may be of interest for search:
Arrangements for conducting electrical current to or from semiconductor or solid state devices in general | |
Lead-frames for semiconductor or other solid state devices in general | |
Arrangements for connecting or disconnecting semiconductor or solid states device in general |
Processes related to the manufacturing of arrangements for conducting electric current to or from the semiconductor body are classified as additional information in H01L 2933/0066.
This place covers:
Elements or arrangement of elements in or on packages, the elements being specially adapted for heating or cooling of the light emitting device.
Attention is drawn to the following places, which may be of interest for search:
Arrangements for cooling or heating of semiconductor devices in general |
Processes relating to the manufacturing of heat extraction or cooling elements are classified as additional information in H01L 2933/0075.
This place covers:
Heat extraction or cooling elements, characterized by their specific material.
This place covers:
Heat extraction or cooling elements, characterized by their shape.
This place covers:
Heat extraction or cooling elements, which are in direct physical contact, or integrated with, at least a part of the devices other than the semiconductor body, e.g. electrodes, package structures or coatings.
This place covers:
Thermoelectric heat extraction or cooling elements in or on a package.
Attention is drawn to the following places, which may be of interest for search:
Cooling arrangements using the Peltier effect for semiconductor or solid state devices in general | |
Thermoelectric devices | |
Integrated devices including thermoelectric devices formed in or on a common substrate |
This place covers:
Heat extraction or cooling elements, which also conduct electric current to or from an electrode of the light emitting devices.
Attention is drawn to the following places, which may be of interest for search:
Arrangements for conducting electrical current for semiconductor or solid state devices in general | |
Lead-frames for semiconductor or other solid state devices in general | |
Arrangements for connecting or disconnecting semiconductor or solid state devices in general |
This place covers:
Heat extraction or cooling elements, which facilitate heat transfer by a fluid, i.e. gas or liquid.
Attention is drawn to the following places, which may be of interest for search:
Heating or cooling elements comprising a fluid for semiconductor or solid state devices in general |