in general

This includes the following kind of devices:

Microstructural devices or systems are classified in subclass B81B, and the processes and apparatus specially adapted for the manufacture or treatment thereof are classified in subclass B81C. So, by way of example, microelectro-mechanical devices (MEMS), containing microelectronic and mechanical components, are classified in group B81B 7/02, and their manufacture, treatment or assembling in the relevant groups of B81C. Microstructural devices or systems working purely electrically or electronically, or related processes or apparatus for the manufacture or treatment thereof are, however, not covered by B81B or B81C and are classified in section H, for example in the groups of the current subclass H01L.

Microstructural devices or systems being of other than purely electrical or electronically type, and apparatus or processes for the manufacture or treatment thereof, which are normally classified in the subclasses B81B and B81C, may be also classified in those groups of H01L providing for their structural or functional features, whenever such features are of interest per se.

Nanostructures, which are normally classified in subclass B82B, may be also classified in those groups of H01L providing for their structural or functional features, whenever such features are of interest per se.

In this subclass, Indexing Codes are mainly attributed with a view to allow retrieval of documents comprising a combination of technical characteristics, some of them being unimportant per se, and, hence, identified as additional information rather than invention information.

In this subclass, both the process and apparatus for the manufacture or treatment of a device and the device itself are classified, whenever both of these are described sufficiently to be of interest.

Processes and apparatus that are specially adapted for the manufacturing of semiconductor or solid state devices belonging to the type:

This main group includes;

Single mono-steps for which a provision exists elsewhere in CPC need not to be classified in H01L 21/00, except if they are specific to the fabrication of semiconductor devices as defined under H01L 21/00. E.g., apparatuses which are not specific to the fabrication of these devices, e.g. apparatuses for depositing layers, are classified in C23C or C30B.

Direct pre-treatment or direct post-treatment of a specific step is classified under the specific step if no other place exists in H01L 21/00. Example: annealing after layer coating is classified together with the coating. Exception: cleaning, see H01L 21/02041

In H01L 21/00, poly-silicon is generally considered as a conductive material for classification purposes, except for its deposition (H01L 21/02365) where it is considered as semiconducting.

Polishing or chemical-mechanical polishing are not distinguished for classification.

Machines and apparatuses for which a provision exists somewhere else in CPC are not classified In H01L 21/00. For example apparatus for deposition of materials are classified in C23C or C30B.

Machines and apparatuses for which no particular provision exists in CPC are classified in H01L 21/67 and subgroups. See also the notes under H01L 21/67.

Processes mainly consisting of features of the use of the elements of the apparatus and which are necessary to operate said apparatus (like for example rotating the turntable of a polisher, evacuating the chamber of a plasma appraratus etc...) need not to be classified in H01L 21/00.

Subject matter relating to processes and apparatus which are clearly suitable for manufacture or treatment of devices whose bodies comprise elements of the fourth group of the Periodic Table (silicon, germanium), and where the material used is not explicitly specified, is classified in the subgroups relating to semiconductors of the fourth group of the Periodic Table (silicon, germanium).

For multistep processes, a junction between two regions of the same material but in a different crystalline state, e.g. amorphous silicon or polysilicon emitters on single crystalline silicon, is not considered as a heterojunction.

Multi-step processes for the manufacture of semiconductor wafers for the fabrication of semiconductor devices as defined under H01L 21/00, prior to the fabrication of any device or part of device, i.e. between the sawing of ingots (covered by B28D) and the cleaning of the wafers (H01L 21/02041), e.g. grinding followed by lapping and polishing.

Covers the preparation of bulk semiconductor wafers (e.g. bulk silicon wafers).

See also H10D 84/00, which has been used for classifying the fabrication of substrates containing parts of Group-IV and Group AIII-BV semiconductors.

See also C30B 33/00.

Bulk, homogeneous wafers:

Multistep process for preparing wafers where the accent is put on a specific step.

Multistep process for preparing wafers where the accent is put on the grinding or lapping, e.g. multiple grinding steps.

Multistep process for preparing wafers where the accent is put on the backside treatment.

Includes backside treatment for recognition purposes

Multistep process for preparing wafers where the accent is put on the chemical etching step or steps.

Multistep process for preparing wafers where the accent is put on the edge treatment, e.g. chamfering.

Multistep process for preparing wafers where the accent is put on the mirror polishing.

In case a mechanical mirror polishing is completed by a chemical flattening step, e.g. a gaseous flattening step, the latter is classified independently.

Multistep processes for preparing wafers having a specific orientation planes as useful plane, or a specific orientation plane in a plane parallel to the surface.

Making a surface of the wafer porous. Includes formation of internal porous regions.

Multistep processes for reclaiming or re-processing, a wafer containing more than a cleaning process. Also contains the re-processing of Smart-Cut donor substrates.

Processes adapted to change the shape of a wafer, either in the surface plane (e.g. square, rectangular wafers), or in cross section (bone cross section).

Cleaning of wafers before or during manufacturing;

Cleaning is the removal of entities which were always unwanted, like particles, impurities, stringers, fences etc. Also includes the removal of edge beads or unwanted coatings on edges or backside of the wafers etc., except photoresist edge beads and photoresist on backside.

Removal of entities which have had a use or a function (sidewalls, resists etc.) is not considered to be a cleaning.

Includes the removal of natural oxide, see also the section "Special rules for classification within this group" below.

Starts with the deep cleaning carried out before first fabrication step (Piranha-RCA) up to cleaning after singulation.

Rinsing and drying are seen as a post-treatment of a wet cleaning, classified together with wet cleaning in H01L 21/02052.

Removal of only natural oxide is also classified in H01L 21/311 if the process is of special relevance for thick oxides.

Removal of impurities, e.g. side walls after RIE, together with the photoresist is classified in H01L 21/02041, and additionally in H01L 21/311, if the resist removal method is peculiar.

Cleaning of the wafer before any manufacturing step for the device is carried out.

All cleaning steps are dry, or when the invention is focussed on a dry cleaning aspect, the cleaning also containing more classical wet steps, like RCA.

Wet cleaning.

Rinsing and drying are seen as a post-treatment of a wet cleaning, classified together with wet cleaning in H01L 21/02052.

The sequence of combining wet and dry steps.

Rinsing and drying are seen as a post-treatment of a wet cleaning, classified together wet cleaning in H01L 21/02052.

Cleaning when at least a fabrication step for a device (for example, first oxidation) has been carried out.

Reclaiming of semiconductor wafers as well as donor semiconductor wafers, e.g. donors in Smart-Cut®

Special products to be cleaned, including particular materials as well as substrates comprising particular features, like vertical features, isolated sidewalls, etc.

Removal of edge beads.

Removal of impurities or unwanted materials on backside, including parasitic coatings.

The group covers inventions wherein the mechanical aspect is of particular importance. Does not exclude some enhancement by chemical means.

Covers processes wherein the laser action has a primary function, with or without chemical, mechanical or electrical assistance.

Covers processes wherein the supercritical fluid has a primary function, with or without chemical, mechanical or electrical assistance.

Processes for the formation of inorganic and organic layers on a substrate, except photoresist layers (see H01L 21/027), for the fabrication of semiconductor devices as defined under H01L 21/00.

In situ pre- and post-treatments of these processes.

Processes for the formation of a multiplicity of these layers.

Processes for coating materials in general: C23C

Processes for the electrolytic coating of materials in general: C25D

Processes for the single-crystal growth of materials in general: C30B

Processes for the formation of inorganic and organic insulating layers on a substrate, except photoresist layers (see H01L 21/027), for the fabrication of semiconductor devices as defined under H01L 21/00.

In situ pre- and post-treatments of these processes.

Processes for the formation of a multiplicity of these layers.

Includes fabrication of insulating

Processes for coating materials in general, including insulating materials: C23C

Processes for the electrolytic coating of materials in general: C25D

Organic or polymer layer composition: see C08G

The process must be adapted or specific to the fabrication of semiconductor devices as defined under H01L 21/00. The mere mentioning of an intended use in semiconductor fabrication does not require that the document being given a group symbol in H01L 21/02107.

If the deposition is specifically adapted to a specific application, with details as to this specific application, e.g. the fabrication of a MIS or MOS electrode or interconnections, the document should additionally be classified in this specific application, for example in H01L 21/28 for the MIS or MOS aspect.

Carbon Nitride.

Carbon based polymeric material

Halogen containing materials, e.g. fluorine, containing BPSG, PSG, BSG, are additionally classified in H01L 21/02131

The formation of silicon oxide layers is classified in this group regardless of the precursor or of the process of formation.

Perovskites are not classified in H01L 21/02175 and subgroups thereof.

Subject matter classified in the range H01L 21/0223 - H01L 21/02249 is additionally classified in H01L 21/02252, H01L 21/02255, and H01L 21/02258 depending on the type of reaction.

Deposition methods in which the gas or vapour is produced by physical means, e.g. ablation from targets or heating of source materials.

Deposition methods in which the gas or vapour is produced by physical means, i.e. by ablation from targets.

Subject matter relating to cyclic plasma CVD is additionally classified in H01L 21/02274

Treatments, carried out just before or just after the formation of an insulating layer, which do not participate in the formation of the layer itself, but which are directly linked to the layer formation.

Pre- or post treatments of general nature (pre-, post-cleaning, pre-, post conditioning etc.) without details or routine annealing steps, i.e. thermal treatment without further features as to a special atmosphere, presence of a plasma, thermally induced chemical reactions, change of phase or crystal structure, need not to be given this group symbol.

The definition should read "post-treatment" instead of after-treatment.

Only covers processes that are part of the layer formation.

Functionalization just after formation should be classified here.

In case the process would also be of interest as an after treatment (H01L 21/3105), both group symbols should be given.

Processes for introducing substances into the formed insulating layer e.g. introduction of phosphorus into silicon oxide, or introduction of nitrogen into silicon nitride to change stoichiometry.

Introduction of substances into the formed insulating layer is classified both here and in H01L 21/3115

Oxidation of silicon nitride to form silicon oxynitride.

Nitridation of silicon oxide to form silicon oxynitride.

Processes for the formation of inorganic semiconductors on a substrate.

Processes for forming doped inorganic semiconductors.

In situ pre-and post-treatments of inorganic semiconductor materials.

Processes for the formation of multiple layers of inorganic semiconductors, comprising heterostructures.

The formed semiconductor layer may be crystalline (mono-, poly-, microcrystalline) or amorphous.

Attention is drawn to the groups C23C, C25D, C30B and their subdivisions for general aspects of these techniques.

This group is not used for classification; subject matter relating to the formation of conductive material on a semiconductor substrate is classified in H01L 21/283 - H01L 21/288, H01L 21/3205 and H01L 21/768.

Formation of masks to be used for etching or patterning, formed out of a layer formed or deposited on the wafer. Includes inorganic masks (metallic or insulating materials) as well as organic masks.

Composition of photosensitive polymers, see G03F 7/00.

Photographic masks of the stencil tape or originals per se: G03F 1/00

Registration or positioning of photographic masks or originals: G03F 9/00

Photographic cameras G03B

Control of position G05D 3/00

In main group H01L 21/00 and subgroup thereof, a mask is defined as a layer, which is coated directly onto the surface of the wafer.

A free standing mask (stencil mask) laid on the wafer is not considered as a mask in the sense of H01L 21/00.

Masks are classified in H01L 21/00 only under the condition that its treatment or structure has been specially adapted to the fabrication of a device covered by H01L 21/00. Examples are:

Covers polymeric masks, including photo-sensitive masks (photoresist) as well as non photo-sensitive masks, e.g., wax, polyimide etc.

Treatment of photoresist layers peculiar to fabrication of electronic devices.

H01L 21/0273 covers the treatment of photoresist which is not peculiar to the type of resist (UV, e-beam, ion beam resist), for example:

Anti-reflective coatings specially adapted for devices as defined under H01L 21/00.

Covers organic as well as inorganic anti-reflective coatings

Multilayer structures and special structures adapted to evacuate charges, e.g. multilayer resists with a conductive layer.

Multilayer resists for electrolithography should additionally be classified in G03F 7/00.

Includes multilayer structures.

Multilayer resists for Röntgenlithography should additionally be classified in G03F 7/00

Processes for forming masks comprising inorganic layers.

This group H01L 21/033 acts as a head group for inorganic masks for patterning layers. Multiple classification with H01L 21/31144 (masks for etching insulating layers), H01L 21/32139 (masks for etching conductive layers and polysilicon layers) and H01L 21/308 (masks for etching semiconductors) is possible.

Processes for forming masks to be used for lifting off another layer (for example having a multilayer structure or special profile) irrespective of their fabrication process

Example:

EP2132770

Mask having a shape being directly affected by and during the patterning process, e.g. erosion or re-deposition, such that the shape of the mask changes during the patterning process.

Processes for forming masks involving special processes, like lift-off, or sidewall formation, e.g. deposition on a step followed by anisotropic etching, or to modify the mask, e.g. oxidation of an Aluminium layer, hardening, before etching step.

Process specially adapted to provide a mask below the lithographic resolution limit.

Sidewall masks may also be classified in H01L 21/0337. As a sidewall spacer has inherently a sub lithographic size, it does not require an automatic group symbol here.

The group range from H01L 21/04 - H01L 21/326 covers processes for fabrication of semiconductor devices on substrates belonging to the semiconductors of

thermal treatments, e.g. gettering

electroforming

mechanical treatments of these semiconductor materials

hydrogenation of these materials

treatments of insulating layers formed on these materials, including planarisation, etching,

deposition conductive or resistive layers on these semiconductor materials

treatment of these conductive layers, like planarisation, oxidation, etching, doping,

treatment of the insulating or conductive layers formed thereon,

planarisation of these semiconductor materials, or of the insulating and conductive layers formed thereon

The presence of a potential jump barrier need not to be specified. Inventions intended to be used in the fabrication of devices having a potential barrier may be classified under H01L 21/04.

Passivation of semiconducting carbon, e.g. diamond

Processes for fabricating devices having bodies of diamond not covered by H01L 21/041 - H01L 21/0425 are classified in H01L 21/18 - H01L 21/326 and are also mandatoril y classified in H10D 62/8303 as invention information or additional information whenever appropriate.

Processes for fabricating devices having bodies comprising crystalline silicon carbide not covered by H01L 21/045 - H01L 21/048 are classified in H01L 21/18 - H01L 21/326 and are also mandatorily classified in H10D 62/8325 as invention information or additional information whenever appropriate.

Processes where ion implantation of boron and subsequent annealing does produce a p-doped region in a silicon carbide.

Processes where ion implantation of boron and subsequent annealing does not produce a p-doped region are classified elsewhere, e.g. H01L 21/0445

Processes and apparatus which, by using the appropriate technology, are clearly suitable for manufacture or treatment of devices whose bodies comprise elements of the fourth group of the Periodic Table or AIII-BV compounds, even if the material used is not explicitly specified.

Joining through a metal layer or eutectic layer.

Direct bonding of semiconductor bodies without intermediate layer

Plasma doping.

Plasma doping is considered as doping from a gas phase, as is the case in Plasma Immersion Ion Implantation. Nevertheless, plasma doping can have ion implantation aspects like the type of ions. These aspects should be classified in ion implantation, H01L 21/265. But a group symbol e.g. H01L 21/2236 or an index code e.g. H01L 21/2236 should always be allocated to track the fact it uses a plasma.

In the range H01L 21/2254 - H01L 21/2257 the main compositional part of the applied layer just before the diffusion step has to be considered for classification

There is no exact border defining high energy. It is meant to cover alpha, beta, gamma, Röntgen... rays. The sub group H01L 21/2633 is incorrectly placed as a subgroup.

Includes processes for forming

Multistep processes for manufacturing electrodes on semiconductor bodies characterised by

Formation of electrodes only involving an etching of conductive materials, including silicide on polysilicon: H01L 21/3213 and subgroups.

Information peculiar to single-step processes should also be classified in the corresponding group, e.g.

Processes for the fabrication of conductor-insulator-semiconductor structure, e.g. wherein the conductor is part of the interconnect (gate level interconnect).

Deposition of the insulators, using epitaxiy

Deposition of the conductor and the insulator within the same process chamber.

When the final conductor comprises a superconductor, subject matter is not classified according to H01L 21/28035 - H01L 21/28097, but instead it is classified in H01L 21/28026.

A very thin, e.g. silicon, adhesion or seed layer is not considered as the one next to the insulator

To assess the coverage of groups H01L 21/28052 and H01L 21/28061, barrier layers, e.g. TaSiN, are not considered]

To assess the coverage of groups H01L 21/28052 and H01L 21/28061, barrier layers, e.g. TaSiN, are not considered]

Documents are also classified in groups H01L 21/28035 - H01L 21/28105 when the composition is also relevant

In case the formation of the insulator would be of general interest, a group symbol should be given in H01L 21/02107.

Thin oxidation layers used as a barrier layer or as a buffer layer, e.g. before the fomation of a high-k insulator, are classified here only if important per se.

In case the transformation would be of general interest it should be classified in

H01L 21/283 - H01L 21/2885 cover the deposition of conductive layers directly in contact with the semiconductor for forming electrodes.

Application to contacts must be mentioned with details. Moreover, details of deposition processes of conductive layers covered by H01L 21/3205 are additionally classified in this group and subgroups thereof. If a document discloses information relevant for any of the groups H01L 21/768 - H01L 21/76898, one or more of these groups should also be assigned.

Methods for depositing conductive layers using gases or vapours of metals or metal-containing precursors.

The deposition process (PVD, CVD, ALD etc.) must be specially adapted for forming contacts or interconnects within semiconductor devices and must be disclosed in detail, i.e. include details on deposition parameters, precursor materials, particular apparatus details etc.

If a document discloses information relevant for any of the groups H01L 21/768 - H01L 21/76898, one or more of these groups should also be assigned.

Deposition of polysilicon on silicon classified there only if application to contacts is mentioned. Otherwise H01L 21/02365

Deposition of polysilicon on silicon classified there only if application to contacts is mentioned. Otherwise H01L 21/02365

The deposition of conductive layers directly in contact with semiconductors for forming electrodes using liquid deposition techniques, e.g. electroless plating.

The deposition process must be specially adapted for forming contacts or interconnects within semiconductor devices and must be disclosed in detail, i.e. include details on deposition parameters, precursor materials, particular apparatus details etc.

If a document discloses information relevant for any of the groups H01L 21/768 - H01L 21/76898, one or more of these groups should also be assigned.

Mechanical treatment of semiconductor wafers or semiconductor layers, except the mechanical treatment of insulating or conductive layers on semiconductor wafers.

Mechanical treatment in general:

The mere use of a machine is classified with the machine only.

Process for the mechanical treatment, enhanced by chemical treatment, is classified in chemical treatment, but may be given a group symbol in mechanical treatment if the mechanical treatment itself is of importance for the invention.

Purely mechanical polishing is considered as chemical-mechanical polishing, and is classified accordingly.

Making grooves, which may result in cutting

Anisotropic liquid etching, i.e. "crystal orientation dependant" etching, using basic (pH>7) compositions. The etch composition is often composed of KOH, amines, azines, quaternary ammonium compounds

Reactive Ion Etching [RIE] of III-V

Processes for polishing semiconductors not being part of the sequence for preparing wafers from an ingot (H01L 21/02013 or H01L 21/02024).

Covers polishing or CMP of semiconductor layers deposited on a substrate, like epitaxial layers.

Chemical-mechanical polishing also includes purely mechanical polishing.

A mask in H01L 21/00 is formed of a layer coated directly onto the surface of the wafer.

A free standing mask (stencil mask) laid on the wafer is not considered as a mask in the sense of H01L 21/00.

Masks are classified in H01L 21/308 only under the condition that its treatment or structure has been specially adapted to the fabrication of a device covered by H01L 21/00. Examples are:

The takes precedence rule (stemming from IPC) pointing to H01L 21/3065 is not valid for CPC: masks for etching by plasma or reactive ion etching are given a group symbol here.

Masks for electrolytic etching are classified with the electrochemical etching in H01L 21/3063.

Using stencil masks for ion implantation is classified in H01L 21/266.

Masks having a specific behaviour during etching process. e.g. erodible mask, shrinking mask etc.

Covers pre-treatment for the formation of a mask, post treatment of the mask before etching, treatments to modify the mask before use, e.g. hardening, formation of sidewalls, multiple sidewalls etc.

Process specially adapted to go below resolution limit of lithography.

Processes for forming insulating layers and their direct post-treatment.

To be used in any process, formation of interconnects, isolation oxides etc.when the invention is focussed on the insulator.

Covers special treatments of insulating layers, wherein the special treatment is not a post-treatment as defined under H01L 21/00, i.e. the classical annealing of the insulating layer to improve its characteristics, but is for example

planarisation, patterning, functionalization after etching.

Functionalization just after formation should be classified with the formation.

In case the process would also be of interest as a post treatment, both classes should be given.

Planarisation involving a removal step not being a chemical etch step: this is the group for polishing and chemical-mechanical polishing (CMP) of insulating materials.

Planarisation by non selective etching, e.g. by a blanket etching reducing the protrusions.

Processes where protrusions are selectively etched through a mask.

Etching by wet process, or by processes wherein gaseous reactants are condensed on the surface.

Gaseous etch with HF is classified in H01L 21/31116

Removal of organic layers or polymers, including photoresists peculiar to semiconductor wafers or devices.

Removal of photoresist being not peculiar to semiconductors is classified in G03F 7/42.

Peculiar to semiconductor devices means that particular precautions are taken to avoid influence of the removal of the photoresist on the semiconductor wafer or device.

Etching by wet process, or by processes wherein gaseous reactants are condensed on the surface.

Etching involving a specially adapted mask

In case the mask would be of general interest, it should also be classified in H01L 21/033

Implantation or diffusion into insulating layers is also classified under H01L 21/02318 and subgroups.

H01L 21/312 - H01L 21/3128 are no longer used for classification of new documents, see H01L 21/02112.

H01L 21/314 - H01L 21/3185 are no longer used for classification of new documents. See H01L 21/02112.

Deposition of conductive layers exclusively on insulating layers, when the process of deposition is relevant.

When the technique of deposition is particular (CVD, PVD or electroplating), also classify in H01L 21/283, H01L 21/285 or H01L 21/288. When an interconnection is concerned, see also H01L 21/768 and subgroups.

Treatment of formed conductive layers. Includes:

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups.

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. After treatment of layers of these materials is thus classified here.

For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Oxidation of non-monocrystalline silicon, e.g. polycrystalline, microcrystalline or amorphous silicon.

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Oxidation of layers of these materials is thus classified here.

For classifying in the group range H01L 21/321 - H01L 21/3215, the presence of an insulating layer below the conductive or resistive layers is not mandatory.

Nitridation of non-monocrystalline silicon, e.g. polycrystalline, microcrystalline or amorphous silicon.

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Nitridation of layers of these materials is thus classified here.

For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Planarisation of conductive or resistive layers.

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Planarisation of these layers is thus classified here.

For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Physical or chemical etching of conductive or resistive layers.

Etching of polysilicon layers

Etching of amorphous silicon layers

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Etching of layers of these materials is thus classified here.

For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Etching processes, where no chemical reaction is involved, e.g.

sputtering, ion milling, laser ablation, pure ion beam etching.

For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Silicides and silicon alloys.

Use of Plasmas, e.g. RIE, and chemically assisted particle (ion or electron, photon) beam etching

For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Etching with supercritical fluids

Etching assisted by electrons, ions and laser beams.

Polysilicon, amorphous, silicides, multilayers containing silicon

Pre-treatments before etching, including removal of natural oxide.

Anti-corrosion post-treatments.

In case the pre-treatment is a removal of natural oxide and is of general interest, a group symbol in H01L 21/02041 should be given.

In case the post treatment is a passivation by oxidation or nitridation this step should be classified independently.

For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Etching involving a mask specifically adapted to the etching operation.

In case the mask would be of general interest, it should also be classified in H01L 21/033.

For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Doping of these layers is thus classified here.

For classifying in the group range H01L 21/321 - H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Extrinsic gettering

Gettering using both extrinsic and intrinsic gettering techniques is classified in both H01L 21/3221 and H01L 21/3225.

Intrinsic gettering

Gettering using both extrinsic and intrinsic gettering techniques is classified in both H01L 21/3221 and H01L 21/3225.

Processes for fabricating devices having semiconductor bodies not belonging to group IV, IV-IV, III-V materials, or to Se, Te, CuO.

Processes for fabricating devices having semiconductor bodies based on II-VI materials.

Doping of II-VI materials.

Radiation covers corpuscular as well as electromagnetic radiation

Processes for implantation wherein the invention is focused on the mask aspect, e.g. mask having a specific topography.

Electrodes on semiconductor materials as defined under H01L 21/34.

Covers the direct deposition of conductive materials on the semiconductor and on an insulating layer overlying the semiconductor (e.g. Tunnel contact).

The group H01L 21/44 includes specific treatments of the semiconductor before formation of the contact (e.g. degenerescence by bombardment etc.).

Insulating materials, only if the contact is a tunnelling contact.

Classification is made in this group only if specific to the semiconductor material, or adapted to the type of device.

Classification is made in this group only if specific to the semiconductor material, or adapted to the type of device.

The treatment of semiconductor bodies including

In this group, the expression "treatment" also covers the removal of leads from parts.

the apparatus of the title and also the use of those apparatus

Thermal apparatus comprising lamps, infrared light irradiation means or ultraviolet light irradiation means

Pick and Place apparatus (picking a die from a wafer and placing it on a different location).

Apparatus for moving substrates on a liquid track

Multistep processes for the fabrication of buried regions, like buried collector layers, buried connections between zones, substrate contacts, as part of a component, e.g. formation of buried silicides.

Fabrication of buried metallic or near metallic regions, like buried silicides, buried eutectic conductors.

For subject matter classified in the range H01L 21/76 - H01L 21/765, when the isolation combines several techniques, both techniques are given a group symbol.

When the combination of several techniques involves the fabrication of SOI, a group symbol within the range H01L 21/76264 - H01L 21/76291 is given.

Single steps, like etching a trench, when they present a general interest or are specifically disclosed, should be given a group symbol in the corresponding single step covered by H01L 21/02 and sub groups.

Covers the formation of dielectric regions by

The groups H01L 21/7624 - H01L 21/76291 cover the fabrication of a buried isolation region

Multi-steps processes for manufacturing interconnections on the surface of a device or through the wafer.

Information peculiar to single-step processes should also be classified in the corresponding sub group of H01L 21/02 (see informative references below).

Processes for fabricating fuses and anti-fuses are classified with the fuses and anti-fuses in H01L 23/525.

Methods specially adapted for forming via or contact holes having a wider top or bottom region, e.g. "cup-shaped" vias

Methods of forming via or contact holes including a step of etching the conductor at the bottom of the hole so as to form e.g. a gouging feature;

methods of forming contact holes having a portion reaching into conductive regions (e.g. source and drain) of the semiconductor substrate

Methods of dual damascene processing involving intermediate temporary filling of the opening first formed in the process with material, e.g. planarisation to facilitate lithography of the second opening

Examples:

US2006094221.

US2005110145

Methods of dual damascene processing involving one or more buried masks, i.e. one or more pre-patterned mask or etch stop layers are fabricated prior to deposition of the trench-level dielectric.

Examples:

WO2005109473

Methods of dual damascene processing involving multiple stacked pre-patterned masks on the trench-level dielectric, i.e. mask stacks pre-defining the trench and via patterns before the actual etching process

Examples:

Layers 135, 140, 150 are hardmask layers, layer 180 is a photoresist for patterning layer 150. The dual damascene structure is transferred into the ILD 130 with the help of the stack of pre-patterned hardmasks 135, 140, 150:

US2003207207

All dual damascene processes in which in an early stage a via is formed partially through the dielectric stack. The via etch is completed later in the process, e.g. during the etching step for forming the trench.

Examples:

US2006166482

First, the via is partially etched into the dielectric stack. In a later step, the via etch is completed together with the trench etch.

Dual damascene processing also involving a stack of pre-patterned hard mask layers, the group symbol H01L 21/76811 is also assigned.

If the partial via process also includes a step of intermediate filling the partial via with a planarising material, the document needs to be classified in H01L 21/76808, too.

Particular method steps designed for improving the result of a process of forming an interconnect opening in a dielectric, e.g. removal of oxides from the surface of a conductor at the bottom of a via hole, removal of etching residues, or treatments restoring the dielectric at the sidewalls.

Examples:

After formation of the opening 10, the photoresist mask and etch residues are removed using a reducing plasma. During this treatment an undesired coating layer 14 forms on the sidewalls of opening 10. Layer 14 is eventually removed by the directional beam of charged oxidizing particles having its main axis 20 parallel to the sidewalls of opening 10:

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Note that in this case the sidewall layer 14 is an undesired by-product of a plasma treatment process. The document should therefore not be classified in H01L 21/76831.

After forming an opening in a low-k dielectric, a degassing treatment and a plasma treatment are carried out in order to remove methyl groups from the dielectric and an oxide from the underlying conductor 22A:

US2005272247

If the method of after-treatment comprises aspects which are classified in any one of the subgroups H01L 21/76822+ (see below), the corresponding group should also be given. If the after-treatment leads to the formation of a sidewall layer in the opening comprising modified dielectric material, the group H01L 21/76831 should also be assigned (note, however, that if the sidewall insulation is formed by a conventional deposition step, H01L 21/76831 is the only relevant group).

H01L 21/76814 is essentially a multistep group, i.e. the after treatment step is only one of several steps to be carried out in order to form an interconnection. If a document exclusively relates to cleaning of openings in dielectrics (in a single-step fashion), the main group symbol is H01L 21/02063.

The geometrical "aspects" to be classified in this group are mainly methodological aspects, e.g. step sequences leading to a reduction of the pitch between via holes, step sequences for incorporating a plurality of vias of different depth, methods of forming vias having a particular cross-sectional shape.

Examples:

Layer 230 is introduced into the structure to enable the simultaneous formation of a deep and a not-so-deep via. Although the formation of the vias themselves contains no special features at all, there is an aspect related "to the size of the vias":

US2006281290

Method for decreasing the pitch between adjacent contact holes by using a sequence of steps involving among other things a sacrificial pattern (13 in the figure below) and a conformal hardmask layer (14') to create an array of vias having a pitch below what is possible by standard lithography:

EP1818977

Imprinting or stamping techniques for forming openings in dielectrics.

Methods using a stamp either to pattern a mask, e.g. a resist mask, for forming the opening or to imprint the opening directly into a dielectric

Example:

US7148142

All aspects related to forming or after-treatment steps which lead to a modification of the material of a dielectric layer within an interconnection structure.

Manufacture of "graded" dielectric layers having a varying composition throughout its thickness, no matter if said grading is achieved by a modified deposition process or an after-treatment.

Examples:

Graded dielectric layer: density and permittivity characteristics vary uniformly from a top portion to a bottom portion of the layer. The variation is achieved through varying deposition parameters such as flow rate of constituent process gases or deposition chamber pressure, or through a post deposition treatment, such as plasma treatment or curing:

US2006003598

The surface of the PSG layer 704 is made hydrophilic by a "scrubbing treatment" 710:

US2006003582

It is not important whether the various treatment steps are conducted on a "main" interlevel or intralevel dielectric or on a "thin functional dielectric layer" as defined in H01L 21/76829 and subgroups.

If the treatment involves a patterned layer including an opening, the group H01L 21/76814 should also be given.

Processes designed for rendering a dielectric layer of an interconnect stack conductive

Examples:

A diamond etch-stop layer (66 in the figure below) is rendered conductive by implanting Ti followed by thermal treatment.

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A document classified in this group is additionally classified in H01L 21/76822 and subgroups thereof, whenever appropriate, the method of conversion involves a plasma treatment, or an ion implantation.

After-treatment or post-treatment process of dielectric layers of the interconnect stack involving particle radiation, e.g. removal of moisture etc. by UV or e-beam radiation, processes for modifying the dielectric constant of the layer, introduction of dopants into the dielectric by particle irradiation.

Examples:

A layer of silane is deposited onto a polymer dielectric layer 16. This layer is then exposed to UV light to initiate polymerization of the silane molecules to form an adhesion promoter layer 18 (or an etch stop or hard mask layer), and to react the adhesion promoter layer with low dielectric constant polymer layer 16:

US2005221606

The upper surface of the porous MSQ film 105 is treated by electron beam irradiation or by UV irradiation to reinforce the upper portion in the film 105:

US2006211235

If the treatment is performed to form or modify a "thin functional" dielectric layer, e.g. an etch stop, one of the groups H01L 21/76829 is additionally assigned.

Curing of a dielectric precursor material is generally not considered an "after-treatment" but characterizes the formation of the dielectric layer per se, covered by H01L 21/02348.

Processes involving contacting a dielectric of an interconnect stack with gases, liquids or plasmas in order to modify the internal structure and/or properties of the dielectric, e.g. nitridation, removal of organic groups from the layer, introduction of dopants into the dielectric using gases, liquids or plasmas.

Examples:

a low-k dielectric is treated in a supercritical fluid after deposition, after via etching, to improve mechanical strength or repair plasma damage:

US2006073697

Plasma treatment 130 is carried out in order to decrease the C- or F- concentration in an upper layer 120a of the ILD 120:

US2006286793

Plasma treatment is carried out in order to modify the sidewalls of a damascene opening 218:

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If the plasma treatment is carried out to form a modified sidewall layer in an opening, the group symbol H01L 21/76831 must also be assigned.

Thermal treatment for modifying the internal structure and/or properties of the dielectric of an interconnect stack, e.g. removal of moisture.

Example:

After completion of the deposition, the low-k dielectric layer 206 is subjected to a heat treatment in a nitrogen-free atmosphere to promote the out-gassing of the volatile materials 220 and especially of nitrogen and nitrogen compounds:

US2004121265

If the heat treatment is carried out in reactive atmospheres, i.e. inevitably involves modification of the dielectric material by e.g. introducing a further chemical element into the layer, e.g. plasma annealing, the group symbol H01L 21/76826 is additionally assigned.