Version: 2025.01
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This area was updated. Please refer to the CPC Notices of Changes and Notices of Editorial Corrections for more information.
CPC | COOPERATIVE PATENT CLASSIFICATION | |||
| H10D | INORGANIC ELECTRIC SEMICONDUCTOR DEVICES [2025-01] NOTES
|
Individual devices [2025-01] |
| H10D 1/00 | Resistors, capacitors or inductors [2025-01] NOTE
|
| H10D 1/01 | . | {Manufacture or treatment} [2025-01] WARNING
|
H10D 1/021 | . . | {of resistors having no potential barriers} [2025-01] |
| H10D 1/025 | . . | {of resistors having potential barriers} [2025-01] WARNING
|
H10D 1/041 | . . | {of capacitors having no potential barriers} [2025-01] |
H10D 1/042 | . . . | {using deposition processes to form electrode extensions} [2025-01] |
H10D 1/043 | . . . | {using patterning processes to form electrode extensions, e.g. etching} [2025-01] |
| H10D 1/045 | . . | {of capacitors having potential barriers, e.g. varactors} [2025-01] WARNING
|
H10D 1/047 | . . . | {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors} [2025-01] |
H10D 1/048 | . . . . | {having PN junctions, e.g. hybrid capacitors with MOS control} [2025-01] |
H10D 1/20 | . | Inductors [2025-01] |
| H10D 1/40 | . | Resistors [2025-01] WARNING
|
H10D 1/43 | . . | Resistors having PN junctions [2025-01] |
H10D 1/47 | . . | Resistors having no potential barriers [2025-01] |
H10D 1/472 | . . . | {having an active material comprising carbon, e.g. diamond or diamond-like carbon [DLC]} [2025-01] |
H10D 1/474 | . . . | {comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides} [2025-01] |
H10D 1/476 | . . . | {comprising conducting organic materials, e.g. conducting polymers} [2025-01] |
H10D 1/60 | . | Capacitors [2025-01] |
H10D 1/62 | . . | Capacitors having potential barriers [2025-01] |
H10D 1/64 | . . . | Variable-capacitance diodes, e.g. varactors [2025-01] |
H10D 1/66 | . . . | Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors [2025-01] |
H10D 1/665 | . . . . | {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors} [2025-01] |
H10D 1/68 | . . | Capacitors having no potential barriers [2025-01] |
H10D 1/682 | . . . | {having dielectrics comprising perovskite structures} [2025-01] |
H10D 1/684 | . . . . | {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers} [2025-01] |
H10D 1/688 | . . . . | {comprising barrier layers to prevent diffusion of hydrogen or oxygen} [2025-01] |
H10D 1/692 | . . . | {Electrodes} [2025-01] |
H10D 1/694 | . . . . | {comprising noble metals or noble metal oxides} [2025-01] |
H10D 1/696 | . . . . | {comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D 1/688)} [2025-01] |
H10D 1/711 | . . . . | {having non-planar surfaces, e.g. formed by texturisation} [2025-01] |
H10D 1/712 | . . . . . | {being rough surfaces, e.g. using hemispherical grains} [2025-01] |
H10D 1/714 | . . . . . | {having horizontal extensions} [2025-01] |
H10D 1/716 | . . . . . | {having vertical extensions} [2025-01] |
| H10D 8/00 | NOTE
WARNING |
| H10D 8/01 | . | Manufacture or treatment [2025-01] WARNING
|
H10D 8/021 | . . | {of breakdown diodes} [2025-01] |
H10D 8/022 | . . . | {of Zener diodes} [2025-01] |
H10D 8/024 | . . . | {of Avalanche diodes} [2025-01] |
H10D 8/041 | . . | {of multilayer diodes} [2025-01] |
| H10D 8/043 | . . | {of planar diodes} [2025-01] WARNING
|
H10D 8/045 | . . | {of PN junction diodes} [2025-01] |
| H10D 8/051 | . . | {of Schottky diodes} [2025-01] WARNING
|
| H10D 8/053 | . . | {of heterojunction diodes or of tunnel diodes} [2025-01] WARNING
|
H10D 8/055 | . . | {of transit-time diodes, e.g. IMPATT or TRAPATT diodes} [2025-01] |
| H10D 8/20 | . |
H10D 8/25 | . . | Zener diodes [2025-01] |
H10D 8/30 | . | Point-contact diodes [2025-01] |
H10D 8/40 | . | Transit-time diodes, e.g. IMPATT or TRAPATT diodes [2025-01] |
H10D 8/411 | . | {PN diodes having planar bodies} [2025-01] |
H10D 8/422 | . | {PN diodes having the PN junctions in mesas} [2025-01] |
H10D 8/50 | . | PIN diodes [2025-01] |
H10D 8/60 | . | Schottky-barrier diodes [2025-01] |
H10D 8/605 | . . | {of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]} [2025-01] |
H10D 8/70 | . | Tunnel-effect diodes [2025-01] |
H10D 8/75 | . . | Tunnel-effect PN diodes, e.g. Esaki diodes [2025-01] |
H10D 8/755 | . . | {Resonant tunneling diodes [RTD]} [2025-01] |
H10D 8/80 | . | PNPN diodes, e.g. Shockley diodes or break-over diodes [2025-01] |
H10D 8/812 | . | {Charge-trapping diodes} [2025-01] |
H10D 8/825 | . | {Diodes having bulk potential barriers, e.g. Camel diodes, planar doped barrier diodes or graded bandgap diodes} [2025-01] |
| H10D 10/00 | Bipolar junction transistors [BJT] [2025-01] NOTE
|
| H10D 10/01 | . | Manufacture or treatment [2025-01] WARNING
|
| H10D 10/021 | . . | {of heterojunction BJTs [HBT]} [2025-01] WARNING
|
| H10D 10/031 | . . | {of Schottky BJTs} [2025-01] WARNING
|
| H10D 10/041 | . . | {of thin-film BJTs (of heterojunction BJTs H10D 10/021)} [2025-01] WARNING
|
| H10D 10/051 | . . | {of vertical BJTs (of heterojunction BJTs H10D 10/021; of Schottky BJTs H10D 10/031; of thin film BJTs H10D 10/041)} [2025-01] WARNING
|
| H10D 10/052 | . . . | {of inverted vertical BJTs} [2025-01] WARNING
|
| H10D 10/054 | . . . | {Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions} [2025-01] WARNING
|
H10D 10/056 | . . . | {of vertical BJTs having the main current going through the whole substrate, e.g. power BJTs} [2025-01] |
H10D 10/058 | . . . . | {having multi-emitter structures, e.g. interdigitated, multi-cellular or distributed emitters} [2025-01] |
| H10D 10/061 | . . | {of lateral BJTs (of heterojunction BJTs H10D 10/021; of thin film BJTs H10D 10/041)} [2025-01] WARNING
|
H10D 10/211 | . | {Point-contact BJTs} [2025-01] |
H10D 10/221 | . | {Schottky barrier BJTs} [2025-01] |
H10D 10/231 | . | {Tunnel BJTs} [2025-01] |
H10D 10/241 | . | {Avalanche BJTs} [2025-01] |
H10D 10/311 | . | {Thin-film BJTs} [2025-01] |
H10D 10/40 | . |
H10D 10/421 | . . | {having both emitter-base and base-collector junctions ending at the same surface of the body} [2025-01] |
H10D 10/441 | . . | {having an emitter-base junction ending at a main surface of the body and a base-collector junction ending at a lateral surface of the body} [2025-01] |
H10D 10/461 | . . | {Inverted vertical BJTs} [2025-01] |
H10D 10/60 | . | Lateral BJTs [2025-01] |
H10D 10/80 | . | Heterojunction BJTs [2025-01] |
H10D 10/821 | . . | {Vertical heterojunction BJTs} [2025-01] |
H10D 10/841 | . . . | {having a two-dimensional base, e.g. modulation-doped base, inversion layer base or delta-doped base} [2025-01] |
H10D 10/861 | . . . | {having an emitter region comprising one or more non-monocrystalline elements of Group IV, e.g. amorphous silicon} [2025-01] |
H10D 10/881 | . . . | {Resonant tunnelling transistors} [2025-01] |
H10D 10/891 | . . . | {comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors} [2025-01] |
| H10D 12/00 | Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT] [2025-01] NOTE
|
| H10D 12/01 | . | Manufacture or treatment [2025-01] WARNING
|
| H10D 12/021 | . . | {of gated diodes, e.g. field-controlled diodes [FCD]} [2025-01] WARNING
|
| H10D 12/031 | . . | {of IGBTs} [2025-01] WARNING
|
| H10D 12/032 | . . . | {of vertical IGBTs} [2025-01] WARNING
|
| H10D 12/035 | . . . . | {Etching a recess in the emitter region (having a recessed gate H10D 12/038)} [2025-01] WARNING
|
| H10D 12/038 | . . . . | {having a recessed gate, e.g. trench-gate IGBTs} [2025-01] WARNING
|
| H10D 12/211 | . | {Gated diodes} [2025-01] WARNING
|
H10D 12/212 | . . | {having PN junction gates, e.g. field controlled diodes} [2025-01] |
| H10D 12/411 | . | {Insulated-gate bipolar transistors [IGBT]} [2025-01] WARNING
|
| H10D 12/415 | . . | {having edge termination structures} [2025-01] WARNING
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| H10D 12/416 | . . | {Bidirectional devices, e.g. trench-gate IGBTs having additional gates at the anode side} [2025-01] WARNING
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| H10D 12/417 | . . | {having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region} [2025-01] WARNING
|
| H10D 12/418 | . . | {having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region} [2025-01] WARNING
|
| H10D 12/421 | . . | {on insulating layers or insulating substrates, e.g. thin-film IGBTs} [2025-01] WARNING
|
H10D 12/441 | . . | {Vertical IGBTs} [2025-01] |
| H10D 12/461 | . . . | {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions} [2025-01] WARNING
|
H10D 12/481 | . . . . | {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} [2025-01] |
| H10D 12/491 | . . . | {having both emitter contacts and collector contacts in the same substrate side} [2025-01] WARNING
|
| H10D 18/00 | Thyristors [2025-01] NOTE
|
| H10D 18/01 | . | Manufacture or treatment [2025-01] WARNING
|
H10D 18/021 | . . | {of bidirectional devices, e.g. triacs} [2025-01] |
H10D 18/031 | . . | {of lateral or planar thyristors} [2025-01] |
H10D 18/211 | . | {having built-in localised breakdown or breakover regions, e.g. self-protected against destructive spontaneous firing} [2025-01] |
H10D 18/221 | . | {having amplifying gate structures, e.g. cascade configurations} [2025-01] |
H10D 18/241 | . | {Asymmetrical thyristors} [2025-01] |
H10D 18/251 | . | {Lateral thyristors} [2025-01] |
| H10D 18/40 | . | with turn-on by field effect [2025-01] WARNING
|
| H10D 18/60 | . | Gate-turn-off devices [2025-01] WARNING
|
H10D 18/65 | . . | with turn-off by field effect [2025-01] |
H10D 18/655 | . . . | {produced by insulated gate structures} [2025-01] |
H10D 18/80 | . | Bidirectional devices, e.g. triacs [2025-01] |
| H10D 30/00 | NOTE
WARNING
|
| H10D 30/01 | . | Manufacture or treatment [2025-01] WARNING
|
| H10D 30/012 | . . | {of static induction transistors [SIT], e.g. permeable base transistors [PBT]} [2025-01] WARNING
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| H10D 30/014 | . . | {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors} [2025-01] WARNING
|
| H10D 30/015 | . . | {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT} [2025-01] WARNING
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| H10D 30/017 | . . | {of FETs having two-dimensional material channels, e.g. TMD FETs} [2025-01] WARNING
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| H10D 30/019 | . . | {of FETs having stacked nanowire, nanosheet or nanoribbon channels} [2025-01] WARNING
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| H10D 30/0191 | . . . | {forming stacked channels, e.g. changing their shapes or sizes} [2025-01] WARNING
|
H10D 30/0193 | . . . . | {by modifying properties of the stacked channels} [2025-01] |
H10D 30/0194 | . . . . | {the stacked channels having different properties} [2025-01] |
| H10D 30/0195 | . . . | {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes} [2025-01] WARNING
|
H10D 30/0196 | . . . . | {by modifying properties of the inner spacers} [2025-01] |
H10D 30/0197 | . . . . | {the inner spacers having different properties} [2025-01] |
| H10D 30/0198 | . . . | {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers} [2025-01] WARNING
|
| H10D 30/021 | . . | {of FETs having insulated gates [IGFET]} [2025-01] WARNING
|
H10D 30/0212 | . . . | {using self-aligned silicidation} [2025-01] |
H10D 30/0213 | . . . . | {providing different silicide thicknesses on gate electrodes and on source regions or drain regions} [2025-01] |
H10D 30/0215 | . . . | {using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions} [2025-01] |
H10D 30/0217 | . . . | {forming self-aligned punch-through stoppers or threshold implants under gate regions} [2025-01] |
| H10D 30/0218 | . . . | {having pocket halo regions selectively formed at the sides of the gates} [2025-01] WARNING
|
| H10D 30/022 | . . . | {having lightly-doped source or drain extensions selectively formed at the sides of the gates} [2025-01] WARNING
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H10D 30/0221 | . . . | {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]} [2025-01] |
| H10D 30/0223 | . . . | {having source and drain regions or source and drain extensions self-aligned to sides of the gate} [2025-01] WARNING
|
H10D 30/0225 | . . . . | {using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes} [2025-01] |
H10D 30/0227 | . . . . | {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} [2025-01] |
H10D 30/0229 | . . . . . | {forming drain regions and lightly-doped drain [LDD] simultaneously, e.g. using implantation through a T-shaped mask} [2025-01] |
H10D 30/023 | . . . | {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D 30/031)} [2025-01] |
| H10D 30/024 | . . . | {of fin field-effect transistors [FinFET]} [2025-01] WARNING
|
| H10D 30/0241 | . . . . | {doping of vertical sidewalls, e.g. using tilted or multi-angled implants} [2025-01] WARNING
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H10D 30/0243 | . . . . | {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability} [2025-01] |
| H10D 30/0245 | . . . . | {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins} [2025-01] WARNING
|
H10D 30/025 | . . . | {of vertical IGFETs (of VDMOS H10D 30/0291; of vertical TFTs H10D 30/0318)} [2025-01] |
H10D 30/026 | . . . | {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D 30/0289)} [2025-01] |
H10D 30/027 | . . . | {of lateral single-gate IGFETs} [2025-01] |
| H10D 30/0273 | . . . . | {forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology} [2025-01] WARNING
|
H10D 30/0275 | . . . . | {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions} [2025-01] |
H10D 30/0277 | . . . . | {forming conductor-insulator-semiconductor or Schottky barrier source or drain regions} [2025-01] |
H10D 30/0278 | . . . . | {forming single crystalline channels on wafers after forming insulating device isolations} [2025-01] |
| H10D 30/028 | . . . | {of double-diffused metal oxide semiconductor [DMOS] FETs} [2025-01] WARNING
|
H10D 30/0281 | . . . . | {of lateral DMOS [LDMOS] FETs} [2025-01] |
H10D 30/0285 | . . . . . | {using formation of insulating sidewall spacers} [2025-01] |
H10D 30/0287 | . . . . . | {using recessing of the source electrodes} [2025-01] |
H10D 30/0289 | . . . . . | {using recessing of the gate electrodes, e.g. to form trench gate electrodes} [2025-01] |
H10D 30/0291 | . . . . | {of vertical DMOS [VDMOS] FETs} [2025-01] |
H10D 30/0293 | . . . . . | {using formation of insulating sidewall spacers} [2025-01] |
H10D 30/0295 | . . . . . | {using recessing of the source electrodes} [2025-01] |
H10D 30/0297 | . . . . . | {using recessing of the gate electrodes, e.g. to form trench gate electrodes} [2025-01] |
| H10D 30/031 | . . . | {of thin-film transistors [TFT]} [2025-01] WARNING
|
| H10D 30/0312 | . . . . | {characterised by the gate electrodes} [2025-01] WARNING
|
| H10D 30/0314 | . . . . . | {of lateral top-gate TFTs comprising only a single gate} [2025-01] WARNING
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| H10D 30/0316 | . . . . . | {of lateral bottom-gate TFTs comprising only a single gate} [2025-01] WARNING
|
| H10D 30/0318 | . . . . | {of vertical TFTs} [2025-01] WARNING
|
| H10D 30/0321 | . . . . | {comprising silicon, e.g. amorphous silicon or polysilicon} [2025-01] WARNING
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| H10D 30/0323 | . . . . . | {comprising monocrystalline silicon} [2025-01] WARNING
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| H10D 30/0327 | . . . . . . | {on sapphire substrates, e.g. of silicon-on-sapphire [SOS] transistor} [2025-01] WARNING
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| H10D 30/0411 | . . . | {of FETs having floating gates} [2025-01] WARNING
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H10D 30/0413 | . . . | {of FETs having charge-trapping gate insulators, e.g. MNOS transistors} [2025-01] |
| H10D 30/0415 | . . . | {of FETs having ferroelectric gate insulators} [2025-01] WARNING
|
| H10D 30/051 | . . | {of FETs having PN junction gates (H10D 30/015 takes precedence)} [2025-01] WARNING
|
H10D 30/0512 | . . . | {of FETs having PN homojunction gates} [2025-01] |
H10D 30/0515 | . . . . | {of vertical FETs having PN homojunction gates} [2025-01] |
H10D 30/0516 | . . . | {of FETs having PN heterojunction gates} [2025-01] |
| H10D 30/061 | . . | {of FETs having Schottky gates (H10D 30/015 takes precedence)} [2025-01] WARNING
|
| H10D 30/0612 | . . . | {of lateral single-gate Schottky FETs} [2025-01] WARNING
|
H10D 30/0614 | . . . . | {using processes wherein the final gate is made after the completion of the source and drain regions, e.g. gate-last processes using dummy gates} [2025-01] |
H10D 30/0616 | . . . . | {using processes wherein the final gate is made before the completion of the source and drain regions, e.g. gate-first processes} [2025-01] |
| H10D 30/0618 | . . . | {of lateral Schottky gate FETs having multiple independently-addressable gate electrodes} [2025-01] WARNING
|
H10D 30/202 | . | {FETs having static field-induced regions, e.g. static-induction transistors [SIT] or permeable base transistors [PBT]} [2025-01] |
H10D 30/204 | . | {Velocity modulation transistors [VMT]} [2025-01] |
| H10D 30/40 | . | FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels [2025-01] WARNING
|
H10D 30/402 | . . | {Single electron transistors; Coulomb blockade transistors} [2025-01] |
| H10D 30/43 | . . | having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels [2025-01] WARNING
|
| H10D 30/435 | . . . | {having multiple laterally adjacent 1D material channels} [2025-01] WARNING
|
| H10D 30/47 | . . | having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] [2025-01] WARNING
|
| H10D 30/471 | . . . | {High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]} [2025-01] WARNING
|
H10D 30/472 | . . . . | {having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT} [2025-01] |
H10D 30/473 | . . . . | {having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT} [2025-01] |
H10D 30/4732 | . . . . . | {using Group III-V semiconductor material} [2025-01] |
| H10D 30/4735 | . . . . . . | {having delta-doped or planar-doped donor layers} [2025-01] WARNING
|
| H10D 30/4738 | . . . . . . | {having multiple donor layers} [2025-01] WARNING
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H10D 30/474 | . . . . | {having multiple parallel 2D charge carrier gas channels} [2025-01] |
H10D 30/475 | . . . . | {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} [2025-01] |
H10D 30/4755 | . . . . . | {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs} [2025-01] |
H10D 30/476 | . . . . | {having gate trenches interrupting the 2D charge carrier gas channels, e.g. hybrid MOS-HEMTs} [2025-01] |
| H10D 30/477 | . . . . | {Vertical HEMTs or vertical HHMTs} [2025-01] WARNING
|
| H10D 30/478 | . . . . | {the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body} [2025-01] WARNING
|
| H10D 30/481 | . . . | {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs} [2025-01] WARNING
|
| H10D 30/485 | . . . . | {Vertical FETs having two-dimensional material channels} [2025-01] WARNING
|
| H10D 30/501 | . | {FETs having stacked nanowire, nanosheet or nanoribbon channels} [2025-01] WARNING
|
H10D 30/502 | . . | {characterised by the stacked channels} [2025-01] |
| H10D 30/503 | . . . | {having non-rectangular cross-sections} [2025-01] WARNING
|
| H10D 30/504 | . . . | {wherein the stacked channels have different properties} [2025-01] WARNING
|
H10D 30/506 | . . . . | {having different thicknesses, sizes or shapes} [2025-01] |
H10D 30/507 | . . | {characterised by inner spacers between adjacent channels} [2025-01] |
H10D 30/508 | . . . | {characterised by the relative sizes, shapes or dispositions of the inner spacers} [2025-01] |
H10D 30/509 | . . . | {characterised by the material of the inner spacers} [2025-01] |
H10D 30/60 | . |
H10D 30/601 | . . | {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D 30/6715)} [2025-01] |
| H10D 30/603 | . . . | {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} [2025-01] WARNING
|
| H10D 30/605 | . . . | {having significant overlap between the lightly-doped extensions and the gate electrode} [2025-01] WARNING
|
| H10D 30/608 | . . . | {having non-planar bodies, e.g. having recessed gate electrodes} [2025-01] WARNING
|
H10D 30/611 | . . | {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D 30/6215; multi-gate TFT H10D 30/6733)} [2025-01] |
H10D 30/615 | . . . | {comprising a MOS gate electrode and at least one non-MOS gate electrode} [2025-01] |
| H10D 30/62 | . . | Fin field-effect transistors [FinFET] [2025-01] WARNING
|
| H10D 30/6211 | . . . | {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates} [2025-01] WARNING
|
| H10D 30/6212 | . . . | {having fin-shaped semiconductor bodies having non-rectangular cross-sections} [2025-01] WARNING
|
| H10D 30/6213 | . . . . | {having rounded corners} [2025-01] WARNING
|
| H10D 30/6215 | . . . | {having multiple independently-addressable gate electrodes} [2025-01] WARNING
|
| H10D 30/6217 | . . . | {having non-uniform gate electrodes, e.g. gate conductors having varying doping} [2025-01] WARNING
|
| H10D 30/6218 | . . . | {of the accumulation type} [2025-01] WARNING
|
| H10D 30/6219 | . . . | {characterised by the source or drain electrodes} [2025-01] WARNING
|
H10D 30/63 | . . |
H10D 30/635 | . . . | {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs} [2025-01] |
H10D 30/637 | . . | {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs} [2025-01] |
| H10D 30/64 | . . | Double-diffused metal-oxide semiconductor [DMOS] FETs [2025-01] WARNING
|
| H10D 30/645 | . . . | {Bidirectional devices} [2025-01] WARNING
|
H10D 30/65 | . . . | Lateral DMOS [LDMOS] FETs [2025-01] |
H10D 30/655 | . . . . | {having edge termination structures} [2025-01] |
H10D 30/657 | . . . . | {having substrates comprising insulating layers, e.g. SOI-LDMOS transistors} [2025-01] |
H10D 30/658 | . . . . | {having trench gate electrodes} [2025-01] |
H10D 30/659 | . . . . | {having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells} [2025-01] |
| H10D 30/66 | . . . | Vertical DMOS [VDMOS] FETs [2025-01] WARNING
|
| H10D 30/662 | . . . . | {having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region} [2025-01] WARNING
|
H10D 30/663 | . . . . | {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS} [2025-01] |
H10D 30/664 | . . . . | {Inverted VDMOS transistors, i.e. source-down VDMOS transistors} [2025-01] |
H10D 30/665 | . . . . | {having edge termination structures} [2025-01] |
H10D 30/667 | . . . . | {having substrates comprising insulating layers, e.g. SOI-VDMOS transistors} [2025-01] |
H10D 30/668 | . . . . | {having trench gate electrodes, e.g. UMOS transistors} [2025-01] |
H10D 30/669 | . . . . | {having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells} [2025-01] |
H10D 30/67 | . . | Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D 30/501)} [2025-01] |
| H10D 30/6704 | . . . | {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device} [2025-01] WARNING
|
H10D 30/6706 | . . . . | {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D 30/6713)} [2025-01] |
H10D 30/6708 | . . . . | {for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect} [2025-01] |
H10D 30/6711 | . . . . . | {by using electrodes contacting the supplementary regions or layers} [2025-01] |
H10D 30/6713 | . . . . | {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} [2025-01] |
H10D 30/6715 | . . . . . | {characterised by the doping profiles, e.g. having lightly-doped source or drain extensions} [2025-01] |
H10D 30/6717 | . . . . . . | {the source and the drain regions being asymmetrical} [2025-01] |
H10D 30/6719 | . . . . . . | {having significant overlap between the lightly-doped drains and the gate electrodes, e.g. gate-overlapped LDD [GOLDD] TFTs} [2025-01] |
H10D 30/6721 | . . . . . . | {having lightly-doped extensions consisting of multiple lightly doped zones or having non-homogeneous dopant distributions, e.g. graded LDD} [2025-01] |
H10D 30/6723 | . . . . | {having light shields} [2025-01] |
H10D 30/6725 | . . . . | {having supplementary regions or layers for improving the flatness of the device} [2025-01] |
H10D 30/6727 | . . . . | {having source or drain regions connected to bulk conducting substrates} [2025-01] |
| H10D 30/6728 | . . . | {Vertical TFTs} [2025-01] WARNING
|
H10D 30/6729 | . . . | {characterised by the electrodes} [2025-01] |
H10D 30/673 | . . . . | {characterised by the shapes, relative sizes or dispositions of the gate electrodes} [2025-01] |
H10D 30/6731 | . . . . . | {Top-gate only TFTs} [2025-01] |
H10D 30/6732 | . . . . . | {Bottom-gate only TFTs} [2025-01] |
| H10D 30/6733 | . . . . . | {Multi-gate TFTs} [2025-01] WARNING
|
| H10D 30/6734 | . . . . . . | {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} [2025-01] WARNING
|
| H10D 30/6735 | . . . . . | {having gates fully surrounding the channels, e.g. gate-all-around} [2025-01] WARNING
|
H10D 30/6736 | . . . . . | {characterised by the shape of gate insulators} [2025-01] |
H10D 30/6737 | . . . . | {characterised by the electrode materials} [2025-01] |
H10D 30/6738 | . . . . . | {Schottky barrier electrodes} [2025-01] |
H10D 30/6739 | . . . . . | {Conductor-insulator-semiconductor electrodes} [2025-01] |
| H10D 30/674 | . . . | {characterised by the active materials} [2025-01] WARNING
|
| H10D 30/6741 | . . . . | {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D 30/6755)} [2025-01] WARNING
|
H10D 30/6743 | . . . . . | {Silicon} [2025-01] |
H10D 30/6744 | . . . . . . | {Monocrystalline silicon} [2025-01] |
H10D 30/6745 | . . . . . . | {Polycrystalline or microcrystalline silicon} [2025-01] |
H10D 30/6746 | . . . . . . | {Amorphous silicon} [2025-01] |
| H10D 30/6748 | . . . . . | {having a multilayer structure or superlattice structure} [2025-01] WARNING
|
H10D 30/675 | . . . . | {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium} [2025-01] |
H10D 30/6755 | . . . . | {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} [2025-01] |
H10D 30/6756 | . . . . . | {Amorphous oxide semiconductors} [2025-01] |
| H10D 30/6757 | . . . | {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D 30/6708; TFTs having lightly-doped source or drain extensions H10D 30/6715)} [2025-01] WARNING
|
H10D 30/6758 | . . . | {characterised by the insulating substrates} [2025-01] |
H10D 30/6759 | . . . . | {Silicon-on-sapphire [SOS] substrates} [2025-01] |
| H10D 30/68 | . . | Floating-gate IGFETs [2025-01] WARNING
|
H10D 30/681 | . . . | {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D 30/688)} [2025-01] |
H10D 30/682 | . . . . | {programmed by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction} [2025-01] |
H10D 30/683 | . . . . | {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling} [2025-01] |
H10D 30/684 | . . . . | {programmed by hot carrier injection} [2025-01] |
H10D 30/685 | . . . . . | {from the channel} [2025-01] |
H10D 30/686 | . . . . . | {using hot carriers produced by avalanche breakdown of PN junctions, e.g. floating gate avalanche injection MOS [FAMOS]} [2025-01] |
H10D 30/687 | . . . | {having more than two programming levels} [2025-01] |
H10D 30/688 | . . . | {programmed by two single electrons} [2025-01] |
H10D 30/689 | . . . | {Vertical floating-gate IGFETs} [2025-01] |
H10D 30/6891 | . . . | {characterised by the shapes, relative sizes or dispositions of the floating gate electrode} [2025-01] |
H10D 30/6892 | . . . . | {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate} [2025-01] |
H10D 30/6893 | . . . . | {wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate} [2025-01] |
H10D 30/6894 | . . . . | {having one gate at least partly in a trench} [2025-01] |
H10D 30/69 | . . | IGFETs having charge trapping gate insulators, e.g. MNOS transistors [2025-01] |
H10D 30/691 | . . . | {having more than two programming levels} [2025-01] |
H10D 30/693 | . . . | {Vertical IGFETs having charge trapping gate insulators} [2025-01] |
H10D 30/694 | . . . | {characterised by the shapes, relative sizes or dispositions of the gate electrodes} [2025-01] |
H10D 30/696 | . . . . | {having at least one additional gate, e.g. program gate, erase gate or select gate} [2025-01] |
H10D 30/697 | . . . . | {having trapping at multiple separated sites, e.g. multi-particles trapping sites} [2025-01] |
H10D 30/699 | . . . . | {having the gate at least partly formed in a trench} [2025-01] |
| H10D 30/701 | . . | {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs} [2025-01] WARNING
|
H10D 30/711 | . . | {having floating bodies} [2025-01] |
H10D 30/721 | . . | {having a gate-to-body connection, i.e. bulk dynamic threshold voltage IGFET (TFTs having gate-to-body connection H10D 30/6708)} [2025-01] |
| H10D 30/751 | . . | {having composition variations in the channel regions} [2025-01] WARNING
|
H10D 30/791 | . . | {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions} [2025-01] |
H10D 30/792 | . . . | {comprising applied insulating layers, e.g. stress liners} [2025-01] |
H10D 30/794 | . . . | {comprising conductive materials, e.g. silicided source, drain or gate electrodes} [2025-01] |
H10D 30/795 | . . . | {being in lateral device isolation regions, e.g. STI} [2025-01] |
H10D 30/796 | . . . | {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates} [2025-01] |
H10D 30/797 | . . . | {being in source or drain regions, e.g. SiGe source or drain} [2025-01] |
| H10D 30/798 | . . . | {being provided in or under the channel regions} [2025-01] WARNING
|
H10D 30/80 | . |
H10D 30/801 | . . | {FETs having heterojunction gate electrodes} [2025-01] |
H10D 30/803 | . . . | {Programmable transistors, e.g. having charge-trapping quantum well} [2025-01] |
H10D 30/83 | . . | FETs having PN junction gate electrodes [2025-01] |
H10D 30/831 | . . . | {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D 30/202)} [2025-01] |
H10D 30/832 | . . . | {Thin-film junction FETs [JFET]} [2025-01] |
H10D 30/87 | . . | FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D 30/801)} [2025-01] |
H10D 30/871 | . . . | {Vertical FETs having Schottky gate electrodes (Vertical SIT or PBT H10D 30/202)} [2025-01] |
H10D 30/873 | . . . | {having multiple gate electrodes} [2025-01] |
H10D 30/875 | . . . | {having thin-film semiconductor bodies} [2025-01] |
H10D 30/877 | . . . | {having recessed gate electrodes} [2025-01] |
| H10D 44/00 | Charge transfer devices [2025-01] NOTE
|
H10D 44/01 | . | Manufacture or treatment [2025-01] |
H10D 44/041 | . . | {having insulated gates} [2025-01] |
H10D 44/061 | . . | {having Schottky gates} [2025-01] |
H10D 44/40 | . | Charge-coupled devices [CCD] [2025-01] |
H10D 44/45 | . . | having field effect produced by insulated gate electrodes [2025-01] |
H10D 44/452 | . . . | {Input structures} [2025-01] |
H10D 44/454 | . . . | {Output structures} [2025-01] |
H10D 44/456 | . . . | {Structures for regeneration, refreshing or leakage compensation} [2025-01] |
H10D 44/462 | . . . | {Buried-channel CCD} [2025-01] |
H10D 44/464 | . . . . | {Two-phase CCD} [2025-01] |
H10D 44/466 | . . . . | {Three-phase CCD} [2025-01] |
H10D 44/468 | . . . . | {Four-phase CCD} [2025-01] |
H10D 44/472 | . . . | {Surface-channel CCD} [2025-01] |
H10D 44/474 | . . . . | {Two-phase CCD} [2025-01] |
H10D 44/476 | . . . . | {Three-phase CCD} [2025-01] |
H10D 44/478 | . . . . | {Four-phase CCD} [2025-01] |
| H10D 48/00 | Individual devices not covered by groups H10D 1/00 - H10D 44/00 [2025-01] NOTE
WARNING
|
H10D 48/01 | . | Manufacture or treatment [2025-01] |
| H10D 48/021 | . . | {of two-electrode devices} [2025-01] WARNING
|
| H10D 48/031 | . . | {of three-or-more electrode devices} [2025-01] WARNING
|
H10D 48/032 | . . . | {of unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]} [2025-01] |
H10D 48/04 | . . | of devices having bodies comprising selenium or tellurium in uncombined form [2025-01] |
H10D 48/042 | . . . | Preparation of foundation plates [2025-01] |
H10D 48/043 | . . . | Preliminary treatment of the selenium or tellurium, its application to foundation plates or the subsequent treatment of the combination [2025-01] |
H10D 48/0431 | . . . . | {Application of the selenium or tellurium to the foundation plate} [2025-01] |
H10D 48/044 | . . . . | Conversion of the selenium or tellurium to the conductive state [2025-01] |
H10D 48/045 | . . . . | Treatment of the surface of the selenium or tellurium layer after having been made conductive [2025-01] |
H10D 48/046 | . . . . | Provision of discrete insulating layers [2025-01] |
H10D 48/047 | . . . | Application of an electrode to the exposed surface of the selenium or tellurium after the selenium or tellurium has been applied to foundation plates [2025-01] |
H10D 48/048 | . . . | Treatment of the complete device, e.g. by electroforming to form a barrier [2025-01] |
H10D 48/049 | . . . . | Ageing [2025-01] |
H10D 48/07 | . . | of devices having bodies comprising cuprous oxide [Cu2O] or cuprous iodide [CuI] [2025-01] |
H10D 48/071 | . . . | {Preparation of the foundation plate, preliminary treatment oxidation of the foundation plate or reduction treatment} [2025-01] |
H10D 48/073 | . . . . | {Preliminary treatment of the foundation plate} [2025-01] |
H10D 48/074 | . . . . | {Oxidation and subsequent heat treatment of the foundation plate (Reduction of copper oxide H10D 48/075)} [2025-01] |
H10D 48/075 | . . . . | {Reduction of the copper oxide or treatment of the oxide layer} [2025-01] |
H10D 48/076 | . . . . | {Application of a non-genetic conductive layer} [2025-01] |
H10D 48/078 | . . . | {Treatment of the complete device, e.g. electroforming or ageing} [2025-01] |
| H10D 48/30 | . | Devices controlled by electric currents or voltages [2025-01] WARNING
|
H10D 48/32 | . . | Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched [2025-01] |
H10D 48/34 | . . . | Bipolar devices [2025-01] |
H10D 48/341 | . . . . | {Unijunction transistors, i.e. double base diodes} [2025-01] |
H10D 48/345 | . . . . | {Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions} [2025-01] |
H10D 48/36 | . . . | Unipolar devices [2025-01] |
H10D 48/362 | . . . . | {Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]} [2025-01] |
H10D 48/366 | . . . | {Multistable devices; Devices having two or more distinct operating states} [2025-01] |
| H10D 48/38 | . . | Devices controlled only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched [2025-01] WARNING
|
H10D 48/381 | . . . | {Multistable devices; Devices having two or more distinct operating states} [2025-01] |
| H10D 48/383 | . | {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects} [2025-01] WARNING
|
| H10D 48/3835 | . . | {Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits} [2025-01] WARNING
|
H10D 48/385 | . | {Devices using spin-polarised carriers} [2025-01] |
H10D 48/387 | . | {Devices controllable only by the variation of applied heat} [2025-01] |
H10D 48/40 | . | Devices controlled by magnetic fields [2025-01] |
H10D 48/50 | . | Devices controlled by mechanical forces, e.g. pressure [2025-01] |
Constructional details [2025-01] |
| H10D 62/00 | Semiconductor bodies, or regions thereof, of devices having potential barriers [2025-01] WARNING
|
| H10D 62/01 | . | {Manufacture or treatment} [2025-01] WARNING
|
H10D 62/021 | . . | {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} [2025-01] |
| H10D 62/051 | . . | {Forming charge compensation regions, e.g. superjunctions} [2025-01] WARNING
|
H10D 62/052 | . . . | {by forming stacked epitaxial layers} [2025-01] |
H10D 62/054 | . . . | {by high energy implantations in bulk semiconductor bodies, e.g. forming pillars} [2025-01] |
H10D 62/056 | . . . | {by out-diffusing dopants from applied layers} [2025-01] |
H10D 62/058 | . . . | {by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches} [2025-01] |
| H10D 62/10 | . | Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies [2025-01] WARNING
|
H10D 62/102 | . . | {Constructional design considerations for preventing surface leakage or controlling electric field concentration} [2025-01] |
H10D 62/103 | . . . | {for increasing or controlling the breakdown voltage of reverse-biased devices} [2025-01] |
H10D 62/104 | . . . . | {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats} [2025-01] |
H10D 62/105 | . . . . | {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D 30/601)} [2025-01] |
H10D 62/106 | . . . . . | {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} [2025-01] |
H10D 62/107 | . . . . . . | {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D 62/111)} [2025-01] |
H10D 62/108 | . . . . . | {having localised breakdown regions, e.g. built-in avalanching regions (in self-protected thyristors H10D 18/211)} [2025-01] |
H10D 62/109 | . . . . . | {Reduced surface field [RESURF] PN junction structures} [2025-01] |
| H10D 62/111 | . . . . . . | {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} [2025-01] WARNING
|
H10D 62/112 | . . . | {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers} [2025-01] |
H10D 62/113 | . . | {Isolations within a component, i.e. internal isolations} [2025-01] |
H10D 62/114 | . . . | {PN junction isolations} [2025-01] |
H10D 62/115 | . . . | {Dielectric isolations, e.g. air gaps} [2025-01] |
H10D 62/116 | . . . . | {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} [2025-01] |
H10D 62/117 | . . | {Shapes of semiconductor bodies} [2025-01] |
H10D 62/118 | . . . | {Nanostructure semiconductor bodies} [2025-01] |
H10D 62/119 | . . . . | {Nanowire, nanosheet or nanotube semiconductor bodies} [2025-01] |
H10D 62/121 | . . . . . | {oriented parallel to substrates} [2025-01] |
H10D 62/122 | . . . . . | {oriented at angles to substrates, e.g. perpendicular to substrates} [2025-01] |
H10D 62/123 | . . . . . | {comprising junctions} [2025-01] |
H10D 62/124 | . . | {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions} [2025-01] |
H10D 62/125 | . . . | {Shapes of junctions between the regions} [2025-01] |
H10D 62/126 | . . . | {Top-view geometrical layouts of the regions or the junctions} [2025-01] |
H10D 62/127 | . . . . | {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} [2025-01] |
| H10D 62/128 | . . | {Anode regions of diodes} [2025-01] WARNING
|
| H10D 62/129 | . . | {Cathode regions of diodes} [2025-01] WARNING
|
| H10D 62/13 | . . | Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions [2025-01] NOTE
|
H10D 62/133 | . . . | {Emitter regions of BJTs} [2025-01] |
H10D 62/134 | . . . . | {of lateral BJTs} [2025-01] |
H10D 62/135 | . . . . | {Non-interconnected multi-emitter structures} [2025-01] |
H10D 62/136 | . . . . | {of heterojunction BJTs (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D 10/861)} [2025-01] |
H10D 62/137 | . . . | {Collector regions of BJTs} [2025-01] |
H10D 62/138 | . . . . | {Pedestal collectors} [2025-01] |
| H10D 62/141 | . . . | {Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs} [2025-01] WARNING
|
H10D 62/142 | . . . . | {Anode regions of thyristors or collector regions of gated bipolar-mode devices} [2025-01] |
| H10D 62/145 | . . . . | {Emitter regions of IGBTs} [2025-01] WARNING
|
H10D 62/148 | . . . . | {Cathode regions of thyristors} [2025-01] |
H10D 62/149 | . . . | {Source or drain regions of field-effect devices} [2025-01] |
H10D 62/151 | . . . . | {of IGFETs (of IGFETs having LDD or DDD structure H10D 30/601; of thin film transistors H10D 30/6713)} [2025-01] |
| H10D 62/152 | . . . . . | {Source regions of DMOS transistors} [2025-01] WARNING
|
H10D 62/153 | . . . . . . | {Impurity concentrations or distributions} [2025-01] |
H10D 62/154 | . . . . . . | {Dispositions} [2025-01] |
H10D 62/155 | . . . . . . | {Shapes (cell layout of DMOS H10D 62/127)} [2025-01] |
| H10D 62/156 | . . . . . | {Drain regions of DMOS transistors} [2025-01] WARNING
|
H10D 62/157 | . . . . . . | {Impurity concentrations or distributions} [2025-01] |
H10D 62/158 | . . . . . . | {Dispositions} [2025-01] |
H10D 62/159 | . . . . . . | {Shapes} [2025-01] |
H10D 62/161 | . . . . | {of FETs having Schottky gates} [2025-01] |
H10D 62/165 | . . . | {Tunnel injectors} [2025-01] |
H10D 62/17 | . . | Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions [2025-01] |
H10D 62/177 | . . . | {Base regions of bipolar transistors, e.g. BJTs or IGBTs} [2025-01] |
H10D 62/184 | . . . . | {of lateral BJTs} [2025-01] |
H10D 62/192 | . . . | {Base regions of thyristors} [2025-01] |
H10D 62/199 | . . . . | {Anode base regions of thyristors} [2025-01] |
H10D 62/206 | . . . . | {Cathode base regions of thyristors} [2025-01] |
H10D 62/213 | . . . | {Channel regions of field-effect devices} [2025-01] |
H10D 62/221 | . . . . | {of FETs} [2025-01] |
H10D 62/228 | . . . . . | {having delta-doped channels} [2025-01] |
H10D 62/235 | . . . . . | {of IGFETs (IGFETs having buried channels H10D 30/637)} [2025-01] |
H10D 62/292 | . . . . . . | {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D 64/512)} [2025-01] |
| H10D 62/299 | . . . . . . | {having lateral doping variations (IGFETs having lightly doped source or drain extensions H10D 30/601)} [2025-01] WARNING
|
H10D 62/307 | . . . . . . . | {the doping variations being parallel to the channel lengths} [2025-01] |
| H10D 62/314 | . . . . . . | {having vertical doping variations (vertical IGFETs H10D 30/63)} [2025-01] WARNING
|
H10D 62/328 | . . . . . | {having PN junction gates} [2025-01] |
H10D 62/335 | . . . . | {of charge-coupled devices} [2025-01] |
H10D 62/343 | . . . | {Gate regions of field-effect devices having PN junction gates} [2025-01] |
H10D 62/351 | . . . | {Substrate regions of field-effect devices} [2025-01] |
H10D 62/357 | . . . . | {of FETs} [2025-01] |
H10D 62/364 | . . . . . | {of IGFETs} [2025-01] |
H10D 62/371 | . . . . . . | {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current} [2025-01] |
| H10D 62/378 | . . . . . . | {Contact regions to the substrate regions} [2025-01] WARNING
|
H10D 62/386 | . . . . | {of charge-coupled devices} [2025-01] |
H10D 62/393 | . . . | {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D 62/127)} [2025-01] |
H10D 62/40 | . | Crystalline structures [2025-01] |
H10D 62/402 | . . | {Amorphous materials} [2025-01] |
H10D 62/405 | . . | {Orientations of crystalline planes} [2025-01] |
H10D 62/50 | . | Physical imperfections [2025-01] |
H10D 62/53 | . . | the imperfections being within the semiconductor body [2025-01] |
H10D 62/57 | . . | the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface [2025-01] |
H10D 62/60 | . | Impurity distributions or concentrations [2025-01] |
H10D 62/605 | . . | {Planar doped, e.g. atomic-plane doped or delta-doped} [2025-01] |
| H10D 62/80 | . | characterised by the materials [2025-01] NOTES
WARNING
|
| H10D 62/81 | . . | of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation [2025-01] WARNING
|
H10D 62/812 | . . . | {Single quantum well structures} [2025-01] |
H10D 62/813 | . . . . | {Quantum wire structures} [2025-01] |
H10D 62/814 | . . . . | {Quantum box structures} [2025-01] |
H10D 62/815 | . . . | of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] [2025-01] |
H10D 62/8161 | . . . . | {potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices (lateral superlattices, lateral surface superlattices H10D 62/8181)} [2025-01] |
H10D 62/8162 | . . . . . | {having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation} [2025-01] |
H10D 62/8163 | . . . . . . | {comprising long-range structurally-disordered materials, e.g. one-dimensional vertical amorphous superlattices} [2025-01] |
H10D 62/8164 | . . . . . . | {comprising only semiconductor materials (potential variation in long-range structurally-disordered materials H10D 62/8163)} [2025-01] |
H10D 62/8171 | . . . . | {Doping structures, e.g. doping superlattices or nipi superlattices} [2025-01] |
H10D 62/8181 | . . . . | {Structures having no potential periodicity in the vertical direction, e.g. lateral superlattices or lateral surface superlattices [LSS]} [2025-01] |
| H10D 62/82 | . . | Heterojunctions [2025-01] WARNING
|
| H10D 62/822 | . . . | comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions [2025-01] WARNING
|
| H10D 62/824 | . . . | comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions [2025-01] WARNING
|
| H10D 62/826 | . . . | comprising only Group II-VI materials heterojunctions, e.g. CdTe/HgTe heterojunctions [2025-01] WARNING
|
| H10D 62/8271 | . . . | {comprising only oxide semiconductor materials heterojunctions, e.g. IGZO/IZO} [2025-01] WARNING
|
| H10D 62/8281 | . . . | {comprising only transition metal dichalcogenide materials heterojunctions, e.g. MoS2/WSe2} [2025-01] WARNING
|
| H10D 62/83 | . . | being Group IV materials, e.g. B-doped Si or undoped Ge [2025-01] WARNING
|
| H10D 62/8303 | . . . | {Diamond} [2025-01] WARNING
|
| H10D 62/832 | . . . | being Group IV materials comprising two or more elements, e.g. SiGe [2025-01] WARNING
|
H10D 62/8325 | . . . . | {Silicon carbide} [2025-01] |
| H10D 62/834 | . . . | further characterised by the dopants [2025-01] WARNING
|
| H10D 62/84 | . . | being selenium or tellurium only [2025-01] NOTE
|
| H10D 62/85 | . . | being Group III-V materials, e.g. GaAs [2025-01] WARNING
|
| H10D 62/8503 | . . . | {Nitride Group III-V materials, e.g. AlN or GaN} [2025-01] WARNING
|
| H10D 62/852 | . . . | being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP [2025-01] WARNING
|
| H10D 62/854 | . . . | further characterised by the dopants [2025-01] WARNING
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| H10D 62/86 | . . | being Group II-VI materials, e.g. ZnO [2025-01] WARNING
|
| H10D 62/8603 | . . . | {Binary Group II-VI materials wherein cadmium is the Group II element, e.g. CdTe} [2025-01] WARNING
|
| H10D 62/862 | . . . | being Group II-VI materials comprising three or more elements, e.g. CdZnTe [2025-01] WARNING
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| H10D 62/864 | . . . | further characterised by the dopants [2025-01] WARNING
|
| H10D 62/871 | . . | {being Group I-VI materials, e.g. Cu2O; being Group I-VII materials, e.g. CuI} [2025-01] WARNING
|
| H10D 62/874 | . . | {being Pb compounds or alloys, e.g. PbO} [2025-01] WARNING
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| H10D 62/875 | . . | {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D 62/86; Group I-VI materials H10D 62/871; Pb compounds or alloys H10D 62/874)} [2025-01] WARNING
|
| H10D 62/881 | . . | {being a two-dimensional material} [2025-01] WARNING
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| H10D 62/882 | . . . | {Graphene} [2025-01] WARNING
|
| H10D 62/883 | . . . | {Transition metal dichalcogenides, e.g. MoSe2} [2025-01] WARNING
|
H10D 64/00 | Electrodes of devices having potential barriers [2025-01] |
H10D 64/01 | . | Manufacture or treatment [2025-01] |
H10D 64/015 | . . | {removing at least parts of gate spacers, e.g. disposable spacers} [2025-01] |
| H10D 64/017 | . . | {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} [2025-01] WARNING
|
H10D 64/018 | . . | {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates} [2025-01] |
H10D 64/021 | . . | {using multiple gate spacer layers, e.g. bilayered sidewall spacers} [2025-01] |
H10D 64/025 | . . | {forming recessed gates, e.g. by using local oxidation} [2025-01] |
H10D 64/027 | . . . | {by etching at gate locations} [2025-01] |
H10D 64/031 | . . | {of data-storage electrodes} [2025-01] |
H10D 64/033 | . . . | {comprising ferroelectric layers} [2025-01] |
H10D 64/035 | . . . | {comprising conductor-insulator-conductor-insulator-semiconductor structures} [2025-01] |
H10D 64/037 | . . . | {comprising charge-trapping insulators} [2025-01] |
H10D 64/111 | . | {Field plates} [2025-01] |
H10D 64/112 | . . | {comprising multiple field plate segments} [2025-01] |
H10D 64/115 | . . | {Resistive field plates, e.g. semi-insulating field plates} [2025-01] |
H10D 64/117 | . . | {Recessed field plates, e.g. trench field plates or buried field plates} [2025-01] |
H10D 64/118 | . | {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges} [2025-01] |
H10D 64/20 | . | Electrodes characterised by their shapes, relative sizes or dispositions [2025-01] |
H10D 64/205 | . . | {Nanosized electrodes, e.g. nanowire electrodes} [2025-01] |
| H10D 64/23 | . . | Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes [2025-01] WARNING
|
H10D 64/231 | . . . | {Emitter or collector electrodes for bipolar transistors} [2025-01] |
| H10D 64/232 | . . . | {Emitter electrodes for IGBTs} [2025-01] WARNING
|
H10D 64/233 | . . . | {Cathode or anode electrodes for thyristors} [2025-01] |
H10D 64/251 | . . . | {Source or drain electrodes for field-effect devices} [2025-01] |
| H10D 64/252 | . . . . | {for vertical or pseudo-vertical devices} [2025-01] WARNING
|
| H10D 64/2523 | . . . . . | {for vertical devices wherein the source or drain electrodes extend entirely through semiconductor bodies} [2025-01] WARNING
|
| H10D 64/2527 | . . . . . | {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies} [2025-01] WARNING
|
| H10D 64/254 | . . . . | {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts} [2025-01] WARNING
|
| H10D 64/256 | . . . . | {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D 30/673)} [2025-01] WARNING
|
| H10D 64/2565 | . . . . . | {wherein the source or drain regions are on a top side of the semiconductor bodies and the recessed source or drain electrodes are on a bottom side of the semiconductor bodies} [2025-01] WARNING
|
| H10D 64/257 | . . . . | {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D 30/673)} [2025-01] WARNING
|
H10D 64/258 | . . . . | {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode} [2025-01] |
H10D 64/259 | . . . . . | {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric} [2025-01] |
H10D 64/27 | . . | Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates [2025-01] |
H10D 64/281 | . . . | {Base electrodes for bipolar transistors} [2025-01] |
H10D 64/291 | . . . | {Gate electrodes for thyristors} [2025-01] |
H10D 64/311 | . . . | {Gate electrodes for field-effect devices} [2025-01] |
H10D 64/411 | . . . . | {for FETs} [2025-01] |
H10D 64/511 | . . . . . | {for IGFETs} [2025-01] |
H10D 64/512 | . . . . . . | {Disposition of the gate electrodes, e.g. buried gates} [2025-01] |
H10D 64/513 | . . . . . . . | {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} [2025-01] |
H10D 64/514 | . . . . . . | {characterised by the insulating layers} [2025-01] |
H10D 64/516 | . . . . . . . | {the thicknesses being non-uniform} [2025-01] |
H10D 64/517 | . . . . . . | {characterised by the conducting layers} [2025-01] |
H10D 64/518 | . . . . . . . | {characterised by their lengths or sectional shapes} [2025-01] |
H10D 64/519 | . . . . . . . | {characterised by their top-view geometrical layouts} [2025-01] |
| H10D 64/529 | . . . | {Electrodes for IGFETs contacting substrate regions, e.g. for grounding or preventing parasitic effects} [2025-01] WARNING
|
H10D 64/60 | . | Electrodes characterised by their materials [2025-01] |
H10D 64/602 | . . | {Heterojunction gate electrodes for FETs} [2025-01] |
H10D 64/605 | . . | {Source, drain, or gate electrodes for FETs comprising highly resistive materials} [2025-01] |
H10D 64/608 | . . | {being superconducting} [2025-01] |
H10D 64/62 | . . | Electrodes ohmically coupled to a semiconductor [2025-01] |
H10D 64/64 | . . | Electrodes comprising a Schottky barrier to a semiconductor [2025-01] |
H10D 64/647 | . . . | {Schottky drain or source electrodes for IGFETs} [2025-01] |
H10D 64/649 | . . . | {Schottky drain or source electrodes for FETs having rectifying junction gate electrodes} [2025-01] |
H10D 64/66 | . . | Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes [2025-01] |
H10D 64/661 | . . . | {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D 64/671)} [2025-01] |
H10D 64/662 | . . . . | {the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures} [2025-01] |
H10D 64/663 | . . . . . | {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates} [2025-01] |
H10D 64/664 | . . . . . | {the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer} [2025-01] |
H10D 64/665 | . . . | {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D 64/671)} [2025-01] |
H10D 64/666 | . . . . | {the conductor further comprising additional layers} [2025-01] |
| H10D 64/667 | . . . | {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D 64/671)} [2025-01] WARNING
|
| H10D 64/668 | . . . . | {the layer being a silicide, e.g. TiSi2} [2025-01] WARNING
|
| H10D 64/669 | . . . . | {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN} [2025-01] WARNING
|
| H10D 64/671 | . . . | {the conductor having lateral variation in doping or structure} [2025-01] WARNING
|
| H10D 64/675 | . . . | {Gate sidewall spacers} [2025-01] WARNING
|
H10D 64/679 | . . . . | {comprising air gaps} [2025-01] |
H10D 64/68 | . . . | characterised by the insulator, e.g. by the gate insulator [2025-01] |
H10D 64/681 | . . . . | {having a compositional variation, e.g. multilayered} [2025-01] |
H10D 64/683 | . . . . . | {being parallel to the channel plane} [2025-01] |
H10D 64/685 | . . . . . | {being perpendicular to the channel plane} [2025-01] |
H10D 64/687 | . . . . | {having cavities, e.g. porous gate dielectrics having gasses therein} [2025-01] |
H10D 64/689 | . . . . | {having ferroelectric layers} [2025-01] |
H10D 64/691 | . . . . | {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D 64/693)} [2025-01] |
H10D 64/693 | . . . . | {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials} [2025-01] |
Integrated devices; Assemblies of multiple devices [2025-01] |
H10D 80/00 | Assemblies of multiple devices comprising at least one device covered by this subclass [2025-01] |
H10D 80/20 | . | the at least one device being covered by groups H10D 1/00 - H10D 48/00, e.g. assemblies comprising capacitors, power FETs or Schottky diodes [2025-01] |
H10D 80/211 | . . | {Resistors, capacitors or inductors covered by H10D 1/00} [2025-01] |
H10D 80/213 | . . . | {Resistors} [2025-01] |
H10D 80/215 | . . . | {Capacitors} [2025-01] |
H10D 80/231 | . . | {Diodes covered by H10D 8/00} [2025-01] |
H10D 80/251 | . . | {FETs covered by H10D 30/00, e.g. power FETs} [2025-01] |
H10D 80/30 | . | the at least one device being covered by groups H10D 84/00 - H10D 86/00, e.g. assemblies comprising integrated circuit processor chips [2025-01] |
| H10D 84/00 | Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers [2025-01] NOTE
|
| H10D 84/01 | . | Manufacture or treatment [2025-01] WARNING
|
H10D 84/0102 | . . | {of thyristors having built-in components, e.g. thyristor having built-in diode} [2025-01] |
H10D 84/0105 | . . . | {the built-in components being field-effect devices} [2025-01] |
| H10D 84/0107 | . . | {Integrating at least one component covered by H10D 12/00 or H10D 30/00 with at least one component covered by H10D 8/00, H10D 10/00 or H10D 18/00, e.g. integrating IGFETs with BJTs} [2025-01] WARNING
|
H10D 84/0109 | . . . | {the at least one component covered by H10D 12/00 or H10D 30/00 being a MOS device} [2025-01] |
| H10D 84/0112 | . . | {Integrating together multiple components covered by H10D 8/00, H10D 10/00 or H10D 18/00, e.g. integrating multiple BJTs} [2025-01] WARNING
|
H10D 84/0114 | . . . | {the components including vertical BJTs and lateral BJTs} [2025-01] |
H10D 84/0116 | . . . | {the components including integrated injection logic [I2L]} [2025-01] |
H10D 84/0119 | . . . | {the components including complementary BJTs} [2025-01] |
H10D 84/0121 | . . . . | {the complementary BJTs being vertical BJTs} [2025-01] |
| H10D 84/0123 | . . | {Integrating together multiple components covered by H10D 12/00 or H10D 30/00, e.g. integrating multiple IGBTs} [2025-01] WARNING
|
H10D 84/0126 | . . . | {the components including insulated gates, e.g. IGFETs} [2025-01] |
H10D 84/0128 | . . . . | {Manufacturing their channels} [2025-01] |
H10D 84/013 | . . . . | {Manufacturing their source or drain regions, e.g. silicided source or drain regions} [2025-01] |
H10D 84/0133 | . . . . . | {Manufacturing common source or drain regions between multiple IGFETs} [2025-01] |
H10D 84/0135 | . . . . | {Manufacturing their gate conductors} [2025-01] |
H10D 84/0137 | . . . . . | {the gate conductors being silicided} [2025-01] |
H10D 84/014 | . . . . . | {the gate conductors having different materials or different implants} [2025-01] |
H10D 84/0142 | . . . . . | {the gate conductors having different shapes or dimensions} [2025-01] |
H10D 84/0144 | . . . . | {Manufacturing their gate insulating layers} [2025-01] |
H10D 84/0147 | . . . . | {Manufacturing their gate sidewall spacers} [2025-01] |
H10D 84/0149 | . . . . | {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} [2025-01] |
| H10D 84/0151 | . . . . | {Manufacturing their isolation regions} [2025-01] WARNING
|
| H10D 84/0153 | . . . . . | {using gate cut processes} [2025-01] WARNING
|
| H10D 84/0156 | . . . . | {Manufacturing their doped wells} [2025-01] WARNING
|
H10D 84/0158 | . . . . | {the components including FinFETs} [2025-01] |
H10D 84/016 | . . . . | {the components including vertical IGFETs} [2025-01] |
H10D 84/0163 | . . . . | {the components including enhancement-mode IGFETs and depletion-mode IGFETs} [2025-01] |
H10D 84/0165 | . . . . | {the components including complementary IGFETs, e.g. CMOS devices} [2025-01] |
H10D 84/0167 | . . . . . | {Manufacturing their channels} [2025-01] |
H10D 84/017 | . . . . . | {Manufacturing their source or drain regions, e.g. silicided source or drain regions} [2025-01] |
H10D 84/0172 | . . . . . | {Manufacturing their gate conductors} [2025-01] |
H10D 84/0174 | . . . . . . | {the gate conductors being silicided} [2025-01] |
H10D 84/0177 | . . . . . . | {the gate conductors having different materials or different implants} [2025-01] |
H10D 84/0179 | . . . . . . | {the gate conductors having different shapes or dimensions} [2025-01] |
H10D 84/0181 | . . . . . | {Manufacturing their gate insulating layers} [2025-01] |
H10D 84/0184 | . . . . . | {Manufacturing their gate sidewall spacers} [2025-01] |
H10D 84/0186 | . . . . . | {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} [2025-01] |
H10D 84/0188 | . . . . . | {Manufacturing their isolation regions} [2025-01] |
H10D 84/0191 | . . . . . | {Manufacturing their doped wells} [2025-01] |
H10D 84/0193 | . . . . . | {the components including FinFETs} [2025-01] |
H10D 84/0195 | . . . . . | {the components including vertical IGFETs} [2025-01] |
| H10D 84/0198 | . . | {Integrating together multiple components covered by H10D 44/00, e.g. integrating charge coupled devices} [2025-01] WARNING
|
| H10D 84/02 | . . | characterised by using material-based technologies [2025-01] WARNING
|
| H10D 84/03 | . . . | using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology [2025-01] WARNING
|
| H10D 84/032 | . . . . | {using diamond technology} [2025-01] WARNING
|
| H10D 84/035 | . . . . | {using silicon carbide [SiC] technology} [2025-01] WARNING
|
| H10D 84/038 | . . . . | {using silicon technology, e.g. SiGe} [2025-01] WARNING
|
| H10D 84/05 | . . . | using Group III-V technology [2025-01] WARNING
|
| H10D 84/07 | . . . | using Group II-VI technology [2025-01] WARNING
|
| H10D 84/08 | . . . | using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies [2025-01] WARNING
|
| H10D 84/101 | . | {Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode} [2025-01] WARNING
|
H10D 84/121 | . . | {BJTs having built-in components} [2025-01] |
H10D 84/125 | . . . | {the built-in components being resistive elements, e.g. BJT having a built-in ballasting resistor} [2025-01] |
H10D 84/131 | . . | {Thyristors having built-in components} [2025-01] |
H10D 84/133 | . . . | {the built-in components being capacitors or resistors} [2025-01] |
H10D 84/135 | . . . | {the built-in components being diodes} [2025-01] |
H10D 84/136 | . . . . | {in anti-parallel configurations, e.g. reverse current thyristor [RCT]} [2025-01] |
H10D 84/138 | . . . | {the built-in components being FETs} [2025-01] |
H10D 84/141 | . . | {VDMOS having built-in components} [2025-01] |
H10D 84/143 | . . . | {the built-in components being PN junction diodes} [2025-01] |
H10D 84/144 | . . . . | {in antiparallel diode configurations} [2025-01] |
H10D 84/146 | . . . | {the built-in components being Schottky barrier diodes} [2025-01] |
H10D 84/148 | . . . | {the built-in components being breakdown diodes, e.g. Zener diodes} [2025-01] |
H10D 84/151 | . . | {LDMOS having built-in components} [2025-01] |
H10D 84/153 | . . . | {the built-in component being PN junction diodes} [2025-01] |
H10D 84/154 | . . . . | {in antiparallel diode configurations} [2025-01] |
H10D 84/156 | . . . | {the built-in components being Schottky barrier diodes} [2025-01] |
H10D 84/158 | . . . | {the built-in components being breakdown diodes, e.g. Zener diodes} [2025-01] |
| H10D 84/161 | . . | {IGBT having built-in components} [2025-01] WARNING
|
| H10D 84/201 | . | {characterised by the integration of only components covered by H10D 1/00 or H10D 8/00, e.g. RLC circuits} [2025-01] WARNING
|
H10D 84/204 | . . | {of combinations of diodes or capacitors or resistors} [2025-01] |
| H10D 84/206 | . . . | {of combinations of capacitors and resistors} [2025-01] WARNING
|
| H10D 84/209 | . . . | {of only resistors} [2025-01] WARNING
|
| H10D 84/212 | . . . | {of only capacitors} [2025-01] WARNING
|
H10D 84/215 | . . . . | {of only varactors} [2025-01] |
H10D 84/217 | . . . . | {of only conductor-insulator-semiconductor capacitors} [2025-01] |
H10D 84/221 | . . . | {of only diodes} [2025-01] |
| H10D 84/40 | . | characterised by the integration of at least one component covered by groups H10D 12/00 or H10D 30/00 with at least one component covered by groups H10D 10/00 or H10D 18/00, e.g. integration of IGFETs with BJTs [2025-01] WARNING
|
| H10D 84/401 | . . | {Combinations of FETs or IGBTs with BJTs} [2025-01] WARNING
|
H10D 84/403 | . . . | {Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors} [2025-01] |
H10D 84/406 | . . . . | {Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors} [2025-01] |
H10D 84/409 | . . . . | {Combinations of FETs or IGBTs with lateral BJTs and with one or more of diodes, resistors or capacitors} [2025-01] |
H10D 84/60 | . | characterised by the integration of at least one component covered by groups H10D 10/00 or H10D 18/00, e.g. integration of BJTs (H10D 84/40 takes precedence) [2025-01] |
H10D 84/611 | . . | {Combinations of BJTs and one or more of diodes, resistors or capacitors} [2025-01] |
H10D 84/613 | . . . | {Combinations of vertical BJTs and one or more of diodes, resistors or capacitors} [2025-01] |
H10D 84/615 | . . . . | {Combinations of vertical BJTs and one or more of resistors or capacitors} [2025-01] |
H10D 84/617 | . . . . | {Combinations of vertical BJTs and only diodes} [2025-01] |
H10D 84/619 | . . . | {Combinations of lateral BJTs and one or more of diodes, resistors or capacitors} [2025-01] |
H10D 84/63 | . . | Combinations of vertical and lateral BJTs [2025-01] |
H10D 84/641 | . . | {Combinations of only vertical BJTs (vertical complementary BJTs H10D 84/673)} [2025-01] |
H10D 84/642 | . . . | {Combinations of non-inverted vertical BJTs of the same conductivity type having different characteristics, e.g. Darlington transistors} [2025-01] |
H10D 84/643 | . . . | {Combinations of non-inverted vertical BJTs and inverted vertical BJTs} [2025-01] |
| H10D 84/645 | . . | {Combinations of only lateral BJTs} [2025-01] WARNING
|
H10D 84/65 | . . | Integrated injection logic [2025-01] |
H10D 84/652 | . . . | {using vertical injector structures} [2025-01] |
H10D 84/655 | . . . | {using field effect injector structures} [2025-01] |
H10D 84/658 | . . . | {integrated in combination with analog structures} [2025-01] |
| H10D 84/67 | . . | Complementary BJTs [2025-01] WARNING
|
H10D 84/673 | . . . | {Vertical complementary BJTs} [2025-01] |
H10D 84/676 | . . | {Combinations of only thyristors} [2025-01] |
| H10D 84/80 | . | characterised by the integration of at least one component covered by groups H10D 12/00 or H10D 30/00, e.g. integration of IGFETs (H10D 84/40 takes precedence) [2025-01] WARNING
|
| H10D 84/811 | . . | {Combinations of field-effect devices and one or more diodes, capacitors or resistors} [2025-01] WARNING
|
| H10D 84/813 | . . . | {Combinations of field-effect devices and capacitor only} [2025-01] WARNING
|
| H10D 84/817 | . . . | {Combinations of field-effect devices and resistors only} [2025-01] WARNING
|
H10D 84/82 | . . | of only field-effect components [2025-01] |
| H10D 84/83 | . . . | of only insulated-gate FETs [IGFET] [2025-01] WARNING
|
| H10D 84/8311 | . . . . | {the IGFETs characterised by having different channel structures} [2025-01] WARNING
|
| H10D 84/8312 | . . . . | {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions} [2025-01] WARNING
|
| H10D 84/83125 | . . . . | {the IGFETs characterised by having shared source or drain regions} [2025-01] WARNING
|
| H10D 84/83135 | . . . . | {the IGFETs characterised by having different gate conductor materials or different gate conductor implants} [2025-01] WARNING
|
| H10D 84/83138 | . . . . | {the IGFETs characterised by having different shapes or dimensions of their gate conductors} [2025-01] WARNING
|
| H10D 84/8314 | . . . . | {the IGFETs characterised by having gate insulating layers with different properties} [2025-01] WARNING
|
| H10D 84/8316 | . . . . | {the IGFETs characterised by having gate sidewall spacers specially adapted for integration} [2025-01] WARNING
|
| H10D 84/832 | . . . . | {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} [2025-01] WARNING
|
H10D 84/833 | . . . . . | {comprising forksheet IGFETs} [2025-01] |
| H10D 84/834 | . . . . | {comprising FinFETs} [2025-01] WARNING
|
| H10D 84/835 | . . . . | {comprising LDMOS} [2025-01] WARNING
|
| H10D 84/836 | . . . . | {comprising EDMOS} [2025-01] WARNING
|
| H10D 84/837 | . . . . | {comprising vertical IGFETs} [2025-01] WARNING
|
H10D 84/839 | . . . . . | {comprising VDMOS} [2025-01] |
| H10D 84/84 | . . . . | Combinations of enhancement-mode IGFETs and depletion-mode IGFETs [2025-01] WARNING
|
| H10D 84/85 | . . . . | Complementary IGFETs, e.g. CMOS [2025-01] WARNING
|
| H10D 84/851 | . . . . . | {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} [2025-01] WARNING
|
H10D 84/852 | . . . . . . | {comprising forksheet IGFETs} [2025-01] |
| H10D 84/853 | . . . . . | {comprising FinFETs} [2025-01] WARNING
|
H10D 84/854 | . . . . . | {comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention} [2025-01] |
| H10D 84/856 | . . . . . | {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} [2025-01] WARNING
|
H10D 84/857 | . . . . . | {comprising an N-type well but not a P-type well} [2025-01] |
H10D 84/858 | . . . . . | {comprising a P-type well but not an N-type well} [2025-01] |
H10D 84/859 | . . . . . | {comprising both N-type and P-type wells, e.g. twin-tub} [2025-01] |
H10D 84/86 | . . | of Schottky-barrier gate FETs [2025-01] |
H10D 84/87 | . . | of PN-junction gate FETs [2025-01] |
H10D 84/891 | . | {characterised by the integration of only components covered by H10D 44/00, e.g. integration of charge-coupled devices [CCD] or charge injection devices [CID} [2025-01] |
H10D 84/895 | . . | {comprising bucket-brigade charge-coupled devices} [2025-01] |
H10D 84/90 | . | Masterslice integrated circuits [2025-01] |
H10D 84/901 | . . | {comprising bipolar technology} [2025-01] |
H10D 84/903 | . . | {comprising field effect technology} [2025-01] |
H10D 84/905 | . . . | {A3B5 or A3B6 gate arrays} [2025-01] |
H10D 84/907 | . . . | {CMOS gate arrays} [2025-01] |
H10D 84/909 | . . . . | {Microarchitecture} [2025-01] |
H10D 84/911 | . . . . . | {Basic cell P to N transistor counts} [2025-01] |
H10D 84/912 | . . . . . . | {4-T CMOS basic cells} [2025-01] |
H10D 84/914 | . . . . . . | {5-T CMOS basic cells} [2025-01] |
H10D 84/916 | . . . . . . | {6-T CMOS basic cells} [2025-01] |
H10D 84/918 | . . . . . . | {7-T CMOS basic cells} [2025-01] |
H10D 84/921 | . . . . . . | {8-T CMOS basic cells} [2025-01] |
H10D 84/922 | . . . . . | {relative P to N transistor sizes} [2025-01] |
H10D 84/924 | . . . . . . | {for current drive capability} [2025-01] |
H10D 84/925 | . . . . . . | {for delay time adaptation} [2025-01] |
H10D 84/927 | . . . . . . | {for capacitive loading} [2025-01] |
H10D 84/929 | . . . . . | {Isolations} [2025-01] |
H10D 84/931 | . . . . . . | {FET isolation} [2025-01] |
H10D 84/933 | . . . . . . | {LOCOS} [2025-01] |
H10D 84/935 | . . . . . | {Degree of specialisation for implementing specific functions} [2025-01] |
H10D 84/937 | . . . . . . | {Implementation of digital circuits} [2025-01] |
H10D 84/938 | . . . . . . . | {Implementation of memory functions} [2025-01] |
H10D 84/941 | . . . . . . | {Implementation of analog circuits} [2025-01] |
H10D 84/942 | . . . . . . . | {Resistors and capacitors} [2025-01] |
H10D 84/944 | . . . . . . | {Hybrid analog or digital} [2025-01] |
H10D 84/946 | . . . . . . | {Embedded IO cells} [2025-01] |
H10D 84/948 | . . . . . . | {Transmission gates} [2025-01] |
H10D 84/949 | . . . . . . | {Porous cells, i.e. pass-through elements} [2025-01] |
H10D 84/951 | . . . . . | {Technology used, i.e. design rules} [2025-01] |
H10D 84/953 | . . . . . . | {Sub-micron technology} [2025-01] |
H10D 84/955 | . . . . . . | {Twin-tub technology} [2025-01] |
H10D 84/957 | . . . . . . | {SOS or SOI technology} [2025-01] |
H10D 84/959 | . . . . . | {Connectability characteristics, i.e. diffusion and polysilicon geometries} [2025-01] |
H10D 84/961 | . . . . . . | {Substrate and well contacts} [2025-01] |
H10D 84/962 | . . . . . . | {Horizontal or vertical grid line density} [2025-01] |
H10D 84/964 | . . . . . . | {Yield or reliability} [2025-01] |
H10D 84/966 | . . . . . . | {Gate electrode terminals or contacts} [2025-01] |
H10D 84/968 | . . . . | {Macro-architecture} [2025-01] |
H10D 84/971 | . . . . . | {Number of core or basic cells in the macro (RAM or ROM)} [2025-01] |
H10D 84/972 | . . . . . | {Distribution functions, e.g. sea of gates} [2025-01] |
H10D 84/974 | . . . . . | {Layout specifications, i.e. inner core regions} [2025-01] |
H10D 84/975 | . . . . . . | {Wiring regions or routing} [2025-01] |
H10D 84/977 | . . . . . . | {Avoiding clock-skew or clock-delays} [2025-01] |
H10D 84/979 | . . . . . . | {Data lines, e.g. buses} [2025-01] |
H10D 84/981 | . . . . . . | {Power supply lines} [2025-01] |
H10D 84/983 | . . . . | {Levels of metallisation} [2025-01] |
H10D 84/985 | . . . . . | {Two levels of metal} [2025-01] |
H10D 84/987 | . . . . . | {Three levels of metal} [2025-01] |
H10D 84/988 | . . . . . | {Four or more levels of metal} [2025-01] |
H10D 84/991 | . . . . | {Latch-up prevention} [2025-01] |
H10D 84/992 | . . . . | {Noise prevention, e.g. preventing crosstalk} [2025-01] |
H10D 84/994 | . . . . | {Radiation hardened circuits} [2025-01] |
H10D 84/996 | . . | {using combined field effect technology and bipolar technology} [2025-01] |
H10D 84/998 | . . | {Input and output buffer/driver structures} [2025-01] |
| H10D 86/00 | Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates [2025-01] NOTE
|
H10D 86/01 | . | Manufacture or treatment [2025-01] |
H10D 86/011 | . . | {comprising FinFETs} [2025-01] |
H10D 86/021 | . . | {of multiple TFTs} [2025-01] |
H10D 86/0212 | . . . | {comprising manufacture, treatment or coating of substrates} [2025-01] |
H10D 86/0214 | . . . | {using temporary substrates} [2025-01] |
H10D 86/0221 | . . . | {comprising manufacture, treatment or patterning of TFT semiconductor bodies} [2025-01] |
H10D 86/0223 | . . . . | {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials} [2025-01] |
H10D 86/0225 | . . . . . | {using crystallisation-promoting species, e.g. using a Ni catalyst} [2025-01] |
H10D 86/0227 | . . . . . | {using structural arrangements to control crystal growth, e.g. placement of grain filters} [2025-01] |
H10D 86/0229 | . . . . . | {characterised by control of the annealing or irradiation parameters} [2025-01] |
H10D 86/0231 | . . . | {using masks, e.g. half-tone masks} [2025-01] |
H10D 86/0241 | . . . | {using liquid deposition, e.g. printing} [2025-01] |
H10D 86/0251 | . . . | {characterised by increasing the uniformity of device parameters} [2025-01] |
H10D 86/03 | . . | wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS] [2025-01] |
H10D 86/201 | . | {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D 86/40 take precedence)} [2025-01] |
H10D 86/215 | . . | {comprising FinFETs} [2025-01] |
H10D 86/40 | . | characterised by multiple TFTs [2025-01] |
H10D 86/411 | . . | {characterised by materials, geometry or structure of the substrates} [2025-01] |
H10D 86/421 | . . | {having a particular composition, shape or crystalline structure of the active layer} [2025-01] |
H10D 86/423 | . . . | {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} [2025-01] |
H10D 86/425 | . . . | {having different crystal properties in different TFTs or within an individual TFT} [2025-01] |
H10D 86/427 | . . . | {having different thicknesses of the semiconductor bodies in different TFTs} [2025-01] |
H10D 86/431 | . . | {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs} [2025-01] |
H10D 86/441 | . . | {Interconnections, e.g. scanning lines} [2025-01] |
H10D 86/443 | . . . | {adapted for preventing breakage, peeling or short circuiting} [2025-01] |
H10D 86/451 | . . | {characterised by the compositions or shapes of the interlayer dielectrics} [2025-01] |
H10D 86/471 | . . | {having different architectures, e.g. having both top-gate and bottom-gate TFTs} [2025-01] |
H10D 86/481 | . . | {integrated with passive devices, e.g. auxiliary capacitors} [2025-01] |
H10D 86/60 | . . | wherein the TFTs are in active matrices [2025-01] |
H10D 86/80 | . | characterised by multiple passive components, e.g. resistors, capacitors or inductors [2025-01] |
| H10D 86/85 | . . | characterised by only passive components [2025-01] WARNING
|
H10D 87/00 | Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate [2025-01] |
H10D 88/00 | Three-dimensional [3D] integrated devices [2025-01] |
| H10D 88/01 | . | {Manufacture or treatment} [2025-01] WARNING
|
H10D 88/101 | . | {comprising components on opposite major surfaces of semiconductor substrates} [2025-01] |
H10D 89/00 | Aspects of integrated devices not covered by groups H10D 84/00 - H10D 88/00 [2025-01] |
H10D 89/011 | . | {Division of wafers or substrates to produce devices, each consisting of a single electric circuit element} [2025-01] |
H10D 89/013 | . . | {the wafers or substrates being semiconductor bodies} [2025-01] |
H10D 89/015 | . . | {the wafers or substrates being other than semiconductor bodies, e.g. insulating bodies} [2025-01] |
H10D 89/10 | . | Integrated device layouts [2025-01] |
H10D 89/105 | . . | {adapted for thermal considerations} [2025-01] |
H10D 89/211 | . | {Design considerations for internal polarisation (integrated injection logic H10D 84/65)} [2025-01] |
H10D 89/213 | . . | {in field-effect devices} [2025-01] |
H10D 89/215 | . . . | {comprising arrangements for charge pumping or biasing substrates} [2025-01] |
H10D 89/217 | . . . | {comprising arrangements for charge injection in static induction transistor logic [SITL] devices} [2025-01] |
H10D 89/311 | . . | {in bipolar devices} [2025-01] |
H10D 89/60 | . | Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] [2025-01] |
H10D 89/601 | . . | {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs} [2025-01] |
H10D 89/611 | . . . | {using diodes as protective elements} [2025-01] |
H10D 89/711 | . . . | {using bipolar transistors as protective elements} [2025-01] |
H10D 89/713 | . . . . | {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices} [2025-01] |
H10D 89/811 | . . . | {using FETs as protective elements} [2025-01] |
H10D 89/813 | . . . . | {specially adapted to provide an electrical current path other than the field-effect induced current path} [2025-01] |
H10D 89/814 | . . . . . | {involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the FET, e.g. gate coupled transistors} [2025-01] |
H10D 89/815 | . . . . . | {involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor} [2025-01] |
H10D 89/817 | . . . . | {FETs in a Darlington configuration} [2025-01] |
H10D 89/819 | . . . . | {Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D 89/817)} [2025-01] |
H10D 89/911 | . . . | {using passive elements as protective elements} [2025-01] |
H10D 89/921 | . . . | {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses} [2025-01] |
H10D 89/931 | . . . | {characterised by the dispositions of the protective arrangements} [2025-01] |
H10D 99/00 | Subject matter not provided for in other groups of this subclass [2025-01] |