CPC Definition - Subclass H10P
This place covers:
Processes or apparatus specially adapted for the manufacture or treatment of devices, or parts thereof, covered by class H10, which are generically applicable to these devices.
Processes or apparatus specially adapted for the manufacture or treatment of devices, or parts thereof, which are covered by a single subclass of H10B - H10N, are classified in the subclass in question. For example, the manufacture of a transistor is classified in subclass H10D.
Processes or apparatus specially adapted for the manufacture or treatment of generic packages, interconnections, connectors or other constructional details of devices, which are covered by subclass H10W, are classified in that subclass. For example, the formation of a copper pillar bump connector is classified in subclass H10W.
Examples of places where the subject matter of this place is covered when specially adapted, used for a particular purpose, or incorporated in a larger system:
Electronic memory devices | |
Inorganic electric semiconductor devices | |
Inorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation | |
Inorganic light-emitting semiconductor devices having potential barriers | |
Organic electric solid-state devices | |
Electric solid-state devices not otherwise provided for |
Attention is drawn to the following places, which may be of interest for search:
Processes or apparatus specially adapted for the manufacture or treatment of generic packages, interconnections, connectors or other constructional details of devices |
In this place, the following terms or expressions are used with the meaning indicated:
bipolar | refers to semiconductor technology that involves multi-carrier-type operation, i.e. which simultaneously uses both electrons and holes as charge carriers |
body | the region of semiconductor (resp. solid-state) material(s) within which, or at the surface of which, the physical effects that are characteristic of the device occur, and any bordering semiconductor (resp. solid-state) material(s) that are contiguous with this region.Examples: in a field-effect transistor [FET], the physical effects occur in the channel region between the source and the drain. The semiconductor body includes the channel region, the source and drain regions, and any contiguous semiconductor material; in a light-emitting diode [LED], the physical effects occur at a junction of active semiconductor layers. The semiconductor body includes these active semiconductor layers and any contiguous semiconductor layers, such as buffer layers, possibly a growth substrate, etc., that are between the cathode and anode electrodes;in a thermoelectric device, the solid-state body includes all solid-state materials in the path of current between the electrodes. |
chip | a piece of a wafer or a substrate that has been processed to contain devices therein or thereon.The expression "diced chip" refers to the result of dicing a wafer or a substrate into a plurality of chips, whereas "undiced chip" refers to a chip before dicing or with no dicing. |
component | an electric circuit element (e.g. diode, transistor, LED, etc.) that is one of a plurality of elements formed in or on a common substrate, e.g. in an integrated device |
container | a solid construction in which (one or more) devices are placed, or which is formed around the devices, for forming packaged devices. A container requires a partial or total enclosure and it may also comprise a filling. |
device | an electric circuit element (e.g. diode, transistor, LED, etc.); (depending on the context) can also refer to an integrated device (e.g. CMOS-IC, DRAM device, etc.). A device may be in the form of a bare or packaged chip. |
dopant | the atoms or compounds added to a material during doping |
doping | the intentional addition of a small quantity of atoms or compounds into a material to achieve a desired characteristic, e.g. to produce an n-type or p-type material |
electrode | a conductive region in or on the semiconductor body or solid-state body of a device (and other than the body itself) which exerts an electrical influence on the body, irrespective of whether or not an external electrical connection is made thereto. The term covers metallic regions which exert electrical influence on the body through an insulating region (e.g. in intentional non-parasitic capacitive coupling), or inductive coupling arrangements. In a capacitive coupling arrangement, the dielectric region is regarded as part of the electrode. The overall conductive wiring may comprise multiple portions. In such a case, only the wiring portions that exert an electrical influence on the body are considered portions of the electrode. Examples: conductive layer(s) in direct physical contact with the body; conductive region(s) exerting an inductive coupling onto the body; a multilayer structure which exerts influence on the body through an insulating region, e.g. in intentional non-parasitic capacitive coupling. |
encapsulation | an enclosure consisting of (one or more) layers, e.g. comprising organic polymers, which at least partially enclose the (one or more) devices, thereby protecting them. An encapsulation is often used to hermetically seal devices. |
FET | field-effect transistor |
field-effect | refers to semiconductor technology wherein a voltage applied to a gate electrode creates an electric field that allows for control of current near the interface of the gate and the body, e.g. to create an inversion channel between the source and drain of a MOSFET |
individual | refers to: an electric circuit element not being an integrated device; or a component of an integrated device. Examples of individual devices include: diodes, transistors, photovoltaic cells, Josephson-junction devices, light-emitting diodes [LED], organic LEDs or a single LED component within an integrated device. |
integrated circuit | an integrated device where all the electric circuit elements (e.g. diodes, transistors, LEDs, etc.) are formed in or on a common substrate, including interconnections between the elements |
integrated device | a device consisting of a plurality of semiconductor or other solid-state electric circuit elements formed in or on a common substrate |
interconnection | a conductive arrangement for conducting electric current from an electrode of a circuit element to another part of the circuit. Examples include metal wirings. |
MIS | metal-insulator-semiconductor |
MISFET | metal-insulator-semiconductor field-effect transistor |
MOS | metal-oxide-semiconductor |
package | the collection of all elements, which are external to the chip, that protect the chip or connect it to another object. Package therefore covers encapsulations, containers, package substrates, interposers, heatsinks or the like. Package does not include objects at a higher system level, like circuit boards and beyond, e.g. a housing in which the circuit board is enclosed. |
TFT | thin-film transistor |
unipolar | refers to semiconductor technology that primarily involves one type only of charge carrier, i.e. it involves either holes or electrons but not both |
wafer | It can be one of the following: (a) a slice of semiconductor or electric solid-state active material.For example: a slice of silicon; a slice of a semiconducting compound, e.g. gallium nitride [GaN]; a slice of lithium tantalate [LiTaO3] for superconductor applications. (b) a multilayered laminate, having at least one layer of semiconductor or electric solid-state active material, the layer being meant to be processed into devices.For example: silicon-on-insulator [SOI]; silicon-on-glass [SOG]; silicon-on-sapphire [SOS]; a composite wafer comprising silicon carbide [SiC] on polycrystalline silicon [Si] support; a layer of semiconducting nanowires on glass. A wafer is typically processed by (e.g.) deposition, etching, doping or diffusion, and is then typically diced into chips. |
This place covers:
The bonding of wafers, substrates or parts of devices covered by class H10.
This group covers bonding of wafers or substrates either (i) before the step of making of any interconnections, or (ii) before the step of packaging of devices, whichever step comes first.
Aspects of bonding involving chips, package parts or interconnections, e.g. chip-on-chip bonding or chip-on-wafer bonding, are classified in subclass H10W, e.g. in group H10W 80/00.
Attention is drawn to the following places, which may be of interest for search:
Debonding of wafers, substrates or parts of devices | |
Bonding of package parts | |
Direct bonding of chips, wafers or substrates |
This place covers:
The formation of materials, e.g. in the shape of layers or pillars, over wafers or substrates or parts of devices covered by class H10.
The materials can be semiconductor, conductive, resistive or insulating.
The techniques include physical vacuum deposition, sputtering, chemical vapour deposition [CVD], physical vapour deposition [PVD], electrolytic deposition (i.e. electroplating) and electroless plating.
Attention is drawn to the following places, which may be of interest for search:
Processes for applying liquids or other fluent materials | |
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material | |
Chemical coating | |
Electroplating | |
Electrolytic or electrophoretic coating | |
Single crystal growth; Epitaxy |
This place covers:
Ion implantation into wafers, substrates or parts of devices covered by class H10.
The ion implantation can take place into semiconductor materials (e.g. for doping) or into insulating materials.
Attention is drawn to the following places, which may be of interest for search:
Electron-beam or ion-beam tubes for localised changing of properties of objects or for applying thin layers thereon, e.g. ion implantation |
This place covers:
Etching specially adapted for wafers, substrates or parts of devices covered by class H10.
The etching techniques include dry etching, plasma etching, reactive-ion etching, wet etching and electrolytic etching.
The etched materials can be semiconductor, conductive, resistive or insulating materials.
Attention is drawn to the following places, which may be of interest for search:
Cleaning of wafers, substrates or parts of devices | |
Etching, surface-brightening or pickling compositions | |
Etching metallic material by chemical means | |
Electrolytic etching or polishing |
This place covers:
Grinding, lapping or polishing specially adapted for wafers, substrates or parts of devices covered by class H10. These processes aim to remove material from a surface of a workpiece, e.g. using loose abrasive materials.
The techniques include:
- electromechanical polishing [EMP];
- electrochemical mechanical polishing [ECMP]; and
- chemomechanical polishing [CMP].
This place covers:
Cutting or separating of wafers or substrates having semiconductor or solid-state devices formed, or to be formed, therein or thereon. The cutting may be partial, e.g. for making a groove.
The techniques include:
- laser cutting;
- forming weakened zones for subsequent cutting or separating, e.g. by laser treatment or by ion implantation;
- sawing, e.g. using revolving or reciprocating blades;
- scoring, breaking or cleaving.
Auxiliary processes or arrangements in relation to cutting or separating of wafers or substrates having semiconductor or solid-state devices formed, or to be formed, therein or thereon.
The auxiliary processes or arrangements include:
- protecting or reinforcing the surface of wafers or substrates during cutting or separating, e.g. using adhesive tapes;
- after-treatments, e.g. removal of adhesive tapes or supports.
Examples of places where the subject matter of this place is covered when specially adapted, used for a particular purpose, or incorporated in a larger system:
Singulating wafers or substrates into multiple chips, i.e. dicing |
Attention is drawn to the following places, which may be of interest for search:
Etching of wafers, substrates or parts of devices | |
Debonding of wafers, substrates or parts of devices | |
Fine working, e.g. cutting, of crystalline semiconductor material; Apparatus therefor |
This place covers:
Debonding specially adapted for wafers, substrates or parts of devices covered by class H10.
Attention is drawn to the following places, which may be of interest for search:
Bonding of wafers, substrates or parts of devices | |
Cutting or separating of wafers, substrates or parts of devices |
Attention is drawn to the following places, which may be of interest for search:
Cutting or separating of wafers, substrates or parts of devices | |
Fine working, e.g. cutting, of crystalline semiconductor material; Apparatus therefor |
When classifying in this group, any process step involving cutting or separating, which is considered to represent information of interest for search, may also be classified in group H10P 54/00.
This place covers:
Cleaning processes or arrangements specially adapted for the wafers, substrates or parts of devices covered by class H10.
This group does not cover the cleaning of package elements, package parts or other constructional details, e.g. cleaning of packages after moulding, which are covered by the related groups of subclass H10W.
Attention is drawn to the following places, which may be of interest for search:
Etching of wafers, substrates or parts of devices | |
Cleaning in general by methods involving the use or presence of liquid or steam | |
Cleaning in general by methods involving the use of air flow or gas flow | |
Cleaning in general by electrostatic means | |
Detergent compositions | |
Electrolytic cleaning, degreasing, pickling or descaling |
Attention is drawn to the following places, which may be of interest for search:
Marks applied to devices, e.g. for alignment or identification |
This place covers:
Testing or measuring during manufacture or treatment of wafers, substrates or devices covered by class H10, e.g. with the aim to detect defects, repair defects or sort defective devices.
The testing or measuring processes must be performed during the semiconductor device fabrication phase, e.g. up to and including end point determination.
Attention is drawn to the following places, which may be of interest for search:
Means for detecting end-point in lapping or polishing machines | |
Investigating or analysing materials by determining their chemical or physical properties | |
Measuring electrical or magnetic variables | |
Measuring leads; Measuring probes | |
Testing electric properties of individual semiconductor devices after their manufacture | |
Testing electric properties of semiconductor devices without physical removal from the circuit of which they form part, after their manufacture | |
Testing electric properties of electronic circuits after their manufacture | |
Contactless testing of electric properties of integrated circuits after their manufacture | |
Marks applied to devices, e.g. for alignment or identification |
Attention is drawn to the following places, which may be of interest for search:
Photolithography, in general |
This place covers:
Multistep processes for the preparation of wafers before the subsequent manufacture of semiconductor devices or solid-state devices therein or thereon.
The following specific multistep processes are included:
- wafer reinforcement.
This place does not cover:
Single-crystal growth of semiconductor ingots |
Attention is drawn to the following places, which may be of interest for search:
Fine working, e.g. cutting, of crystalline semiconductor material; Apparatus therefor |