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 [Search a list of Patent Appplications for class 711]   CLASS 711,ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MEMORY
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SECTION I - CLASS DEFINITION

This class provides, within an electrical computer or digital data processing system, for the following subject matter:

A. Processes and apparatus for addressing memory wherein the processes and apparatus involve significant address manipulating (e.g., combining, translating, or mapping and other techniques for formatting and modifying address data) and are combined with specific memory configurations or memory systems;

B. Processes and apparatus for accessing and controlling memory (e.g., transferring and modifying address data, selecting storage devices, scheduling access); and

C. Processes and apparatus for forming memory addresses (e.g., virtual memory addressing, address translating, translation-lookaside buffers (TLBs), boundary checking, and page mode).

SCOPE OF THE CLASS

(1) Note. In the instance where a peripheral is a memory, classification herein is proper.
(2) Note. Classification herein requires more than nominal recitation of addressing techniques or of memory accessing or controlling in combination with digital data processing systems or data processing. A nominal combination refers to a combination wherein one or more of the means or steps thereof are recited so broadly, and without details, as to constitute a mere identification rather than a description of each means or step.
(3) Note. Memory devices, per se, are classified in their respective device classes. More specifically, registers and data bearing records (e.g., smart cards) are classified elsewhere. Static memory devices including internal elements of memories are classified elsewhere. Display memory organizations and structures (i.e., selective visual display systems) such as memories defined by graphics processing systems and graphics processing that involves interfacing with memory are classified elsewhere. Devices (e.g., printers) that include memory for processing data for static presentation (i.e., for viewing on a fixed medium such as paper) are classified elsewhere. Dynamic magnetic information storage or retrieval devices (e.g., magnetic disks, tapes, drums, etc.) are classified elsewhere. Dynamic information storage or retrieval devices (e.g., optical disks, CD-ROMs, jukebox mechanics, and other storage devices having magnetic and mechanical components) are classified elsewhere. See the SEARCH CLASS notes below.
(4) Note. Processes and apparatus for transferring data between memories of different computers directly (i.e., with minimum or no intervention from main processors of the computers) are classified elsewhere. See the SEARCH CLASS notes below.
(5) Note. Processes and apparatus for direct memory access (DMA) (i.e., the transferring of data between peripherals and memories of a computer or digital data processing system with minimal or no intervention from the main processor of the computer or digital data processing system) are classified elsewhere. See the SEARCH CLASS notes below.
(6) Note. Processes and apparatus for accessing and retrieving instruction data of a fixed or variable length from a memory or buffer and for shifting such instruction data to align it with a physical memory or buffer boundary are classified elsewhere. See the SEARCH CLASS notes below.

SECTION II - REFERENCES TO OTHER CLASSES

SEE OR SEARCH CLASS:

235Registers,   various subclasses for basic machines and associated indicating mechanisms for ascertaining the number of movements of various devices and machines; machines made from these basic machines alone (e.g., cash registers, voting machines) and in combination with various perfecting features such as printers and recording means; and various systems controlled by data bearing records (e.g., smart cards).
257Active Solid-State Devices (e.g., Transistors, Solid-State Diodes),   subclass 202 for repeating geometric arrangement of individual structural elements of solid-state devices, and subclasses 368 and 390 for matrix or array of field effect transistors (FETs).
326Electronic Digital Logic Circuitry,   subclasses 37+ for multifunctional or programmable logic (e.g., gate arrays) and subclasses 52+ and 104+ for generic logic functions such as EXOR, AND, OR, NOT and decoding in general.
340Communications: Electrical,   subclasses 1.1 through 16.1for controlling one or more devices to obtain a plurality of results by transmission of a designated one of plural distinctive control signals over a smaller number of communication lines or channels, particularly subclasses 2.1-2.8 for path selection, subclass 2.81 for tree or cascade selective communication, subclasses 3.1-3.9 for communication systems where status of a controlled device is communicated, subclasses 4.1-4.14 for synchronizing selective communication systems, subclasses 9.1-9.17 for selective communication addressing, subclasses 12.1-12.55 for pulse responsive actuation, and subclasses 14.1-14.69 for selective decoder matrix.
341Coded Data Generation or Conversion,   various subclasses for electrical pulse and digit code converters (e.g., systems for originating or emitting a coded set of discrete signals or translating one code into another code wherein the meaning of the data remains the same but formats may differ).
345Computer Graphics Processing and Selective Visual Display Systems,   subclasses 1.1 through 3.4for visual display systems with selective electrical control including display memory organization and structure for storing image data and manipulating image data between a display memory and display peripheral, subclasses 530-574 for memory organization and structure for storing images to be displayed, and subclass 521 for graphic processing that involves interfacing with memory.
353Optics: Image Projectors,   subclasses 25+ for selective data retrieval of stored information viewed by a projection means.
358Facsimile and Static Presentation Processing,   subclasses 1.16 and 1.17 for process and apparatus (e.g., printer) that includes memory for processing data for static presentation (i.e., for viewing on a fixed medium such as paper).
360Dynamic Magnetic Information Storage or Retrieval,   (which is an integral part of Class 369 following subclass 18 ), for record carriers and systems wherein data are stored and retrieved by interaction with a medium and there is relative motion between a medium and a transducer (e.g., magnetic disk drives, tapes, and drums and control thereof, per se), particularly subclasses 72.1+ for locating a specific area in storage.
361Electricity: Electrical Systems and Devices,   subclasses 679.31 through 679.39for computer storage component combined with housing or mounting arrangement having no data processing or calculating procedures.
365Static Information Storage and Retrieval,   various subclasses for static memory devices including internal elements of the memory, particularly subclass 189.011 for read/write circuits and subclasses 230.01+ for addressing of addressable, static single storage elements or plural elements; subclass 189.05 for buffering or latching data being read from or written to memory; subclass 189.08 for logic devices in combination with memory systems; subclasses 200 and 201 for testing of memory systems; and subclass 230.08 for buffering and latching address data being employed to access memory.
369Dynamic Information Storage or Retrieval,   various subclasses for record carriers and systems wherein data are stored and retrieved by interaction with a medium and there is relative motion between a medium and a transducer (e.g., optical disks, CD-ROMs, jukeboxes), particularly subclasses 30.01 through 41.01,69, and 176-271 for designating or selecting storage media to be used for storage and retrieval.
370Multiplex Communications,   appropriate subclasses for multiplex switching techniques similar to addressing and the handling of memory information signals and for the simultaneous transmission of two or more signals over a common medium, particularly 351 for time division multiplex (TDM) switching, subclass 395.7 for an ATM network with detail of storage access and control, subclasses 475+ for asynchronous TDM communications including addressing, and subclasses 498+ for time division bus transmission.
377Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems,   subclasses 64+ for shift registers.
701Data Processing: Vehicles, Navigation, and Relative Location,   appropriate subclasses for applications of computers in vehicular and navigational environments.
700Data Processing: Generic Control Systems or Specific Applications,   appropriate subclasses and particularly subclasses 1 through 89for data processing generic control systems and subclasses 90-306 for computer and data processing system applications.
702Data Processing: Measuring, Calibrating, or Testing,   subclass 80 for specified memory location generation for storage of an electrical signal parameter measurement.
704Data Processing: Speech Signal Processing, Linguistics, Language Translation, and Audio Compression/Decompression,   subclasses 1+ for applications of computers in linguistics, subclasses 200+ for applications of computers in speech signal processing, and subclasses 500 through 504 for applications of computers in audio compression/decompression.
705Data Processing: Financial, Business Practice, Management, or Cost/Price Determination,   appropriate subclasses for applications of computers and calculators in business and management environments.
706Data Processing: Artificial Intelligence,   appropriate subclasses for artificial intelligence, per se.
707Data Processing: Database, Data Mining, and File Management or Data Structures,   subclasses 781 through 789for access control to a database or file in a computer environment; subclasses 790 through 812 for database design including data structures and data structure management; subclasses 813 through 820 for garbage collection in database environments, and subclasses 821 through 831 for file management, file systems and file directory structures.
708Electrical Computers: Arithmetic Processing and Calculating,   subclasses 1+ for electric hybrid computers; subclasses 100+ for electric digital calculating computers; and subclasses 800+ for electric analog computers.
709Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring or Plural or Processor Synchronization,   appropriate subclassesfor multiple computer data transfer, particularly subclass 212 for computer-to-computer direct memory accessing and subclasses 213-216 for multicomputer data transfer via shared memory.
710Electrical Computers And Digital Data Processing Systems: Input/Output,   subclasses 1+ for transferring data from one or more peripherals to one or more computers for the latter to process, store, or further transfer or for transferring data from the computers to the peripherals, particularly subclasses 22+ for direct memory access (DMA) (i.e., the transferring of data between peripherals and memories of a computer or digital data processing system with minimal or no intervention from the main processor of the computer or digital data processing system).
712Electrical Computers And Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 1+ for processing architectures such as MIMD, vector, or array processors; subclass 204 for instruction alignment; subclasses 205+ for instruction fetching;and subclasses 200 through 248 for various instruction processing not involving I/O such as executing.
713Electrical Computers and Digital Processing Systems: Support,   subclass 150 and 181 for multiple computer communication using cryptography; and subclasses 187 and 188 for software program protection or computer virus detection in combination with data encryption.
714Error Detection/Correction and Fault Detection/Recovery,   various subclasses for detecting or correcting errors in generic electrical pulse or pulse coded data and for detecting and recovering from faults of computers, digital data processing systems, and logic level based systems, particularly subclass 702 for memory access (e.g., address permutation); subclasses 710+ for replacement with spare memory components or portion thereof; subclasses 718+ for memory testing; and subclasses 763+ for memory access with error correction, error pointer, or error checking.
726Information Security,   subclasses 1 through 36for information security in computers or digital processing system.
901Robots,   appropriate cross-reference art collections for reprogrammable, multifunction manipulators designed to move devices.

SECTION III - GLOSSARY

The terms below have been defined for purposes of classification in this class and are shown in underlined type when used in the class and subclass definitions. When these terms are not underlined in the definitions, the meaning is not restricted to the glossary definitions below.

ADDRESS DATA

Data that specify a location in a memory.

BUS

A conductor used for transferring data, signals, or power.

COMPUTER

A machine that inputs data, processes data, stores data, and outputs data.

DATA

Representation of information in a coded manner suitable for communication, interpretation, or processing. See ADDRESS DATA, INSTRUCTION DATA, STATUS DATA, and USER DATA in this glossary,

DATA PROCESSING

See PROCESSING below.

DIGITAL DATA PROCESSING SYSTEM

An arrangement of processor(s) in combination with either memory or peripherals, or both, performing data processing.

INFORMATION

Meaning that a human being assigns to data by means of the conventions applied to that data.

INSTRUCTION DATA

Data that represent an operation and identify its operands, if any.

MEMORY

A functional unit to which data can be stored and from which data can be retrieved.

PERIPHERAL

A functional unit that transmits data to or receives data from a computer to which it is coupled (e.g., modems, keyboards, monitors, touch tablet, printers, joy stick, disk and tape drives, etc.).

PROCESSING

Methods or apparatus performing systematic operations upon data or information exemplified by functions such as data or information transferring, merging, sorting, and calculating (i.e., arithmetic operations or logical operations).

Note: In an effort to avoid redundant constructions, in this class, where appropriate, the term address data processing is used in place of address data data processing.

PROCESSOR

A functional unit that interprets and executes instruction data.

STATUS DATA

Data that represent conditions of data, computers, peripherals, memory, etc.

USER DATA

Data other than address data, instruction data, or status data.

SUBCLASSES

[List of Patents for class 711 subclass 1]    1ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION OR SYSTEM:
 This subclass is indented under the class definition.  Subject matter comprising means or steps for determining one or more values (i.e., address data) that specify one or more locations in a storage medium wherein the means or steps are claimed in combination with a particular configuration or system for storing data.
(1) Note. Classification herein requires significant address manipulating (i.e., more than nominal recitation of an addressing technique). Significant address manipulating is exemplified by address dataprocessing functions such as combining, translating, mapping, and other techniques associated with forming or modifying address data.
(2) Note. Means or steps for determining a value that specifies a memory location (i.e., address data) must include more than nominal recitation of processing functions and memory components for classification herein.
(3) Note. This subclass and those indented below provide for combinations of data processing, particular memory systems, and significant address data manipulating. Generalized addressing in a digital data processing system is classified elsewhere in this class. See the SEARCH THIS CLASS, SUBCLASS notes below.
(4) Note. This subclass and those indented below may include means (e.g., processor, controller, etc.) or steps for control of a memory of a digital data processing system in combination with memory accessing (e.g., reading, writing). Memory accessing and control for specific memory compositions, hierarchical memory configurations, and shared memory, however, is classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS notes below.
(5) Note. Means or steps for accessing and controlling plural memory configurations (e.g., data farms, "library" systems) that include significant data processing are classified herein. Control systems for delivering storage media (e.g., delivery of robotics or automated tapes or cartridges, selection and delivery of platters), however, are properly classified elsewhere under automated control or another appropriate subclass in the respective device, robotics, and generic control classes. In instances involving significant data processing and significant details of media delivery systems, classification herein is proper.

SEE OR SEARCH THIS CLASS, SUBCLASS:

3,for cache memory addressing.
101,through 116, for storage accessing and control for various memory compositions (e.g., ROM, RAM, CAM, dynamic, detachable, bubble, etc.) with more than nominal data processing.
117,through 146, for storage accessing and control for hierarchical memory with nominal address forming.
147,through 154, for storage accessing and control for shared memory with nominal address forming.
200+,for generalized address forming in data processing systems.

SEE OR SEARCH CLASS:

326Electronic Digital Logic Circuitry,   subclasses 105+ for digital logic decoding circuits in general.
340Communications: Electrical,   subclasses 14.1 through 14.69for selective matrix which may be used for control or as a switching means.
345Computer Graphics Processing and Selective Visual Display Systems,   subclasses 530 through 574for processing indices to locations (or addresses) of stored data elements in a computer graphic processing system.
365Static Information Storage and Retrieval,   subclasses 189.011 for read/write circuits, and subclasses 230.01+ for addressing of addressable, static single storage elements or plural elements of the same type.
369Dynamic Information Storage or Retrieval,   subclasses 30.01 through 41.01,69, and 176-271, as appropriate, for subject matter related to designation or selection of storage medium to be used for storage and retrieval.
370Multiplex Communications,   appropriate subclasses for multiplex switching techniques similar to addressing or the handling of memoryinformation signals.
704Data Processing: Speech Signal Processing, Linguistics, Language Translation and Audio Compression/Decompression,   subclasses 2+ for memory control scheme combined with linguistics.
707Data Processing: Database, Data Mining, and File Management or Data Structures,   subclasses 781 through 789for access control to a database or file in a computer environment and subclasses 790 through 812 for database design including data structures and data structure management, subclasses 813 through 820 for garbage collection in database environments and subclasses 821 through 831 for file management, file systems and file directory structures.
710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclasses 3 through 4for Input/Out addressing, subclass 9 for address assignment for configuring peripherals, subclasses 22-28 for direct memory accessing (DMA) and subclass 316 for system intra-connecting switching.
901Robots,   appropriate cross-reference art collections for reprogrammable, multifunction manipulators designed to move devices.
  
[List of Patents for class 711 subclass 2]    2Addressing extended or expanded memory:
 This subclass is indented under subclass 1.  Subject matter wherein addresses are determined for memory not normally accessible by a base operating system, computer, or digital data processing system components.
(1) Note. Classification here may include virtual addressing techniques; however, virtual memory addressing art which deals with logical addressing techniques as opposed to addressing for physical enhancements, such as extended and expanded memory, is classified elsewhere in this class.

SEE OR SEARCH THIS CLASS, SUBCLASS:

203+,for virtual addressing, per se.
  
[List of Patents for class 711 subclass 3]    3Addressing cache memories:
 This subclass is indented under subclass 1.  Subject matter wherein addresses are generated for memory nearest a processor in a hierarchical memory arrangement (i.e., a cache memory arrangement).
(1) Note. This subclass accommodates particular addressing techniques for cache memory systems. Cache memory accessing and control (i.e., reading and writing) are classified elsewhere in this class. See the SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

117+,for hierarchical memory arrangement accessing and control, including cache memory in subclasses 118 through 146.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclass 49.1 for internal aspects of associative memory.
  
[List of Patents for class 711 subclass 4]    4Dynamic-type storage device (e.g., disk, tape, drum):
 This subclass is indented under subclass 1.  Subject matter wherein address schemes are particular to a data storage device requiring relative motion between a data holding medium and a recording mechanism such as disk, tape, or drum memory.

SEE OR SEARCH CLASS:

360Dynamic Magnetic Information Storage or Retrieval,   which is an integral part of Class 369, following subclass 18 , for record carriers and systems wherein information is stored and retrieved by interaction with a medium and there is relative motion between a medium and a transducer (e.g., magnetic disk drive devices and control thereof, per se). See Class 360, subclass 72.2 for addressing and control of recording mechanism to locate the selected area.
369Dynamic Information Storage or Retrieval,   various subclasses for record carriers and systems wherein information is stored and retrieved by interaction with a medium and there is relative motion between a medium and a transducer. Particularly, see subclasses 30.01 through 41.01for selective addressing of dynamic storage medium.
  
[List of Patents for class 711 subclass 5]    5For multiple memory modules (e.g., banks, interleaved memory):
 This subclass is indented under subclass 1.  Subject matter wherein logical addresses are determined and mapped (e.g., interleaving) across different physical memory arranged in blocks, banks, partitions, etc.
(1) Note. This subclass includes subject matter directed to static column or static row handling in multiple physical memory module addressing.

SEE OR SEARCH THIS CLASS, SUBCLASS:

127,for interleaved cache.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclasses 230.03 and 230.04 for subject matter including plural banks or blocks and alternating between them.
  
[List of Patents for class 711 subclass 6]    6Virtual machine memory addressing:
 This subclass is indented under subclass 1.  Subject matter wherein addresses are determined in a memory system accommodating addressing requirements for software emulation of a target computer or digital data processing system on a base computer or digital data processing system.
(1) Note. Classification here includes virtual addressing techniques (that is, for example, processing logical to physical (real, absolute) address translation entries. Virtual memory addressing deals with logical addressing techniques. Classificaiton here is proper if there is significant virtual memory processing for systems accomodating emulation of a tarte computer of digital data processin system on a base computer or digital data processing system. Logical addressing for physical enhancements, such as extended and expanded memory, is classified elsewhere in theis class.

SEE OR SEARCH THIS CLASS, SUBCLASS:

202through 210, for address mapping and virtual addressing, per se.

SEE OR SEARCH CLASS:

703Data Processing: Structural Design, Modeling, Simulation, and Emulation,   appropriate subclasses.
718Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   subclass 1 for virtual machine task or process management.
  
[List of Patents for class 711 subclass 100]    100STORAGE ACCESSING AND CONTROL:
 This subclass is indented under the class definition.  Subject matter comprising means (e.g., a processor, a controller, etc.) or steps for governing memory in a computer or digital data processing system or the passage (e.g., reading, writing) of data thereto.
(1) Note. The subject matter of this subclass and the subclasses thereunder provides for details of how memory is accessed and controlled. Classification herein requires more than nominal recitation of accessing or controlling memory in the context of digital data processing systems or data processing. Examples of significant memory accessing and control data processing include transferring and modifying memoryaddress data, selecting memory devices or memory locations, and scheduling memory accesses.
(2) Note. Storage devices such as static memory devices, holographic stores, disk drives (and the mechanical control of disk drives, e.g., head positioning, substrate speed, etc.), and optical stores, are classified, per se, in their respective device classes.
(3) Note. Subject matter classified herein may include nominal recitations of address data generation, manipulation, and modification. Combinations of a particular memory construct (e.g., cache) with accessing and control and significant addressing as exemplified by data processing functions such as combining, translating, mapping, and other techniques associated with forming and modifying addresses, however, are classified in superior subclasses directed to such combinations. See the SEARCH THIS CLASS, SUBCLASS notes below.
(4) Note. Classification herein requires more than nominal recitation of means or steps for controlling memory.
(5) Note. This subclass and the subclasses thereunder also provide for subject matter wherein static or dynamic storage forms part of a digital data processing system.
(6) Note. Subject matter classified herein may include nominal recitations of reliability and availability in combination with memory accessing and control. The species of reliability and availability related to data archiving, backup, and device access limiting and security combined with memory accessing and controlling is classified herein. Other species of reliability and availability combined with memory accessing and controlling are classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS notes below.
(7) Note. Memories known as display memory, display buffers, frame buffers, VRAMs, etc., functioning in combination to store image data for image processing are properly classified elsewhere. Subject matter for interfacing between a graphics processor and a memory is classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS notes and SEARCH CLASS notes below for the information handling subclasses relevant to memories acting on display data.
(8) Note. Means or steps for accessing and controlling plural memory configurations (e.g., data farms, "library" systems, etc.) including significant data processing are classified here. Details of control systems for medium delivery such as robotics or automated tape, cartridge, and platter selection and delivery, however, are properly classified elsewhere under automated control or another appropriate subclass in the respective device, robotics, and generic control classes. In instances where there is significant data processing and significant details of medium delivery systems, classification should be based on the hierarchy of classes and classified here.
(9) Note. This subclass is directed to generic memory accessing and control. Database accessing and retrieval is classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

161+,for reliability and availability combined with memory accessing and control provided for in this array. See the (6) Note for subclass 100 above.

SEE OR SEARCH CLASS:

340Communications: Electrical,   subclasses 1.1 through 16.1for controlling one or more devices to obtain a plurality of results by transmission of a designated one of plural distinctive control signals over a smaller number of communication lines or channels, particularly subclasses 2.1-2.8 for path selection, subclass 2.81 for tree or cascade selective communication, subclasses 3.1-3.9 for communication systems where status of a controlled device is communicated, subclasses 4.1-4.14 for synchronizing selective communication systems, subclasses 9.1-9.17 for selective communication addressing, subclasses 12.1-12.55 for pulse responsive actuation, and subclasses 14.1-14.69 for selective decoder matrix.
345Computer Graphics Processing and Selective Visual Display Systems,   subclasses 530 through 574for memory organization and structure for storing images to be displayed and subclasses 531-574 for interfacing between a graphics processor and a memory.
353Optics: Image Projectors,   subclasses 25+ for selective data retrieval of stored information viewed by a projection means.
358Facsimile and Static Presentation Processing,   subclasses 1.16 and 1.17 for static presentation processing combined with memory.
361Electricity: Electrical Systems and Devices,   subclasses 679.31 through 679.39for computer storage component combined with housing or mounting arrangement having no data processing or calculating procedures.
369Dynamic Information Storage or Retrieval,   subclasses 30.01 through 41.01,69, and 176-271, as appropriate, for subject matter related to designation or selection of storage medium to be used for storage and retrieval.
370Multiplex Communications,   for the simultaneous transmission of two or more signals over a common medium, particularly subclasses 351+ for time division multiplex (TDM) switching, subclasses 475+ for asynchronous TDM communications including addressing, and subclasses 498+ for time division bus transmission.
704Data Processing: Speech Signal Processing, Linguistics, Language Translation, and Audio Compression/Decompression,   subclasses 2+ for memory control scheme combined with linguistics.
707Data Processing: Database, Data Mining, and File Management or Data Structures,   subclasses 781 through 789for access control to a database or file in a computer environment, subclasses 790 through 812 for database design including data structures and data structure management, subclasses 813 through 820 for garbage collection in database environments, and subclasses 821 through 831 for file management, file systems and file directory structures.
710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclasses 1+ for combinations of data transfers performed by a peripheral (e.g., I/O processors, DMA, I/O controllers, I/O adapters, etc.) between digital data processing systems or computers and peripherals; subclasses 22+ for Direct Memory Access (DMA) or direct data transfers to or from memory or to or from other peripherals and for data transfers performed by a peripheral between external components such as disk drives, peripheral devices, etc., which involves I/O processing; and subclasses 100+ for connections within a single computer or digital data processing system arrangement such as interfacing, bus arbitration, bus expansion.
712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 220+ for processing control and instruction processing, per se, which often includes access to registers surrounding functional units of a processor.
714Error Detection/Correction and Fault Detection/Recovery,   subclasses 1+ for reliability and availability combined with memory accessing and control not provided for herein (see the ( 6 ) Note above).
717Data Processing: Software Development, Installation, and Management,   subclasses 151 through 161for software/program optimization of memory usage or other resource usage (e.g., optimization by removing redundancy, eliminating unnecessary memory accesses, etc.).
901Robots,   appropriate cross-reference art collections for reprogrammable, multifunction manipulators designed to move devices.
  
[List of Patents for class 711 subclass 101]    101Specific memory composition:
 This subclass is indented under subclass 100.  Subject matter wherein control of the memory or the accessing thereof is adapted to the type of memory being accessed.
(1) Note. Structures and particulars of the memory device itself are classified in the relevant device class.
(2) Note. Subject matter included herein is directed to the specifics of accessing technique employed to access and control the memory by computers, digital data processing systems, processors, or other users.
(3) Note. The nature of data stored in a memory (i.e., the information) does not make the memory "specific" within the context of this and its indented subclasses (e.g., video or image data, printer buffer, control datamemory, etc.).
(4) Note. Accessing and controlling of a multiport memory, per se, are classified elsewhere in this class. See the SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

131,for multiport cache.
149,for shared multiport memory.

SEE OR SEARCH CLASS:

235Registers,   subclasses 375+ for systems controlled by data bearing records.
313Electric Lamp and Discharge Devices,   subclasses 391+ for cathode ray tube storage devices.
326Electronic Digital Logic Circuitry,   subclasses 37+ for multifunctional or programmable logic (e.g., gate arrays) and subclasses 52+ and 104+ for generic logic functions such as EXOR, AND, OR, NOT, and decoding.
369Dynamic Information Storage or Retrieval,   subclasses 30.01 through 41.01,69, and 176-271, as appropriate, for subject matter related to designation or selection of storage medium to be used for storage and retrieval.
439Electrical Connectors,   subclasses 43+ for plug board connections and pins, and subclasses 55+ for preformed panel circuit arrangements (e.g., ICs, chips, wafers, etc.).
902Electronic Funds Transfer,   cross-reference art collections 25+ for smart card memories.
  
[List of Patents for class 711 subclass 102]    102Solid-state read only memory (ROM):
 This subclass is indented under subclass 101.  Subject matter including means or steps for accessing solid-state randomly accessible nonvolatile memory (e.g., ROM).

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   appropriate subclasses for storage having a particular internal cell structure (e.g., subclass 94 for read only (i.e., semipermanent) systems), subclasses 189.011 for memory read/write circuits, and subclasses 230.01+ for addressing circuits.
  
[List of Patents for class 711 subclass 103]    103Programmable read only memory (PROM, EEPROM, etc.):
 This subclass is indented under subclass 102.  Subject matter including means or steps for accessing and controlling programmable solid-state nonvolatile memory (e.g., PROM, EPROM, EEPROM, flash, etc.).
  
[List of Patents for class 711 subclass 104]    104Solid-state random access memory (RAM):
 This subclass is indented under subclass 101.  Subject matter including apparatus or method for accessing volatile randomly accessible memory.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclasses 129+ for various memory elements used in random access memory construction.
  
[List of Patents for class 711 subclass 105]    105Dynamic random access memory:
 This subclass is indented under subclass 104.  Subject matter including means or steps for accessing volatile memory requiring periodic refreshing (e.g., DRAM, Dynamic RAM, etc.).
  
[List of Patents for class 711 subclass 106]    106Refresh scheduling:
 This subclass is indented under subclass 105.  Subject matter including specifics of coordinating refreshing operations with other system operations.
(1) Note. This subclass is proper for subject matter directed to coordinating refresh scheduling with other system events, accesses, requirements, etc., external to the memory cells. However, coordinating the timing requirements within a memory cell or composite thereof is classified elsewhere. See the SEARCH CLASS notes below.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   appropriate subclasses for timing requirements at the cell level and for storage having a particular internal cell structure (e.g., subclass 222 for memory refreshing).
  
[List of Patents for class 711 subclass 107]    107Ferrite core:
 This subclass is indented under subclass 101.  Subject matter comprising arrays of magnetizable rings as the individual storage elements.
(1) Note. In the 1960"s the term "core memory" referred exclusively to memory with ferrite cores. Also at that time, the main memory of large systems were exclusively of this type. As the art progressed, the term core memory became a holdover to refer to the system"s main memory, regardless of the actual type of memory being used. Therefore, if core memory is claimed, the specification should be checked to see if the memory is indeed core memory (i.e., ferrite memory) for classification here; otherwise, it should be treated as solid-state memory and classified elsewhere.

SEE OR SEARCH THIS CLASS, SUBCLASS:

102+,for ROM accessing and control.
104+,for RAM accessing and control.
  
[List of Patents for class 711 subclass 108]    108Content addressable memory (CAM):
 This subclass is indented under subclass 101.  Subject matter including memory of the type where elements are addressed according to the stored contents (e.g., associative memory, etc.).

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclasses 49.1 through 50for associative memories or content addressable memories (CAM), per se.
  
[List of Patents for class 711 subclass 109]    109Shift register memory:
 This subclass is indented under subclass 101.  Subject matter including memory of the type where elements are arranged to serially pass the stored contents from one location to an adjacent location, or for use in data format conversion within a digital data processing system.
(1) Note. Employing shift registers as part of the system memory for transferring data within a digital data processing system is classified here; however, the specifics of the interconnections and control of shift register memories is classified elsewhere. See the SEARCH CLASS notes below.
(2) Note. Although data format conversion may form part of the overall combination in this subclass, data format conversion, per se, is classified elsewhere. See the SEARCH CLASS notes below.

SEE OR SEARCH CLASS:

235Registers,   subclasses 441+ , 492, and 493 for electrical records and record sensors (i.e., IC cards).
341Coded Data Generation or Conversion,   appropriate subclasses for digital to digital code converting.
377Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems,   subclasses 64+ for shift registers and subclasses 107+ and 118+ for counters.
  
[List of Patents for class 711 subclass 110]    110Circulating memory:
 This subclass is indented under subclass 109.  Subject matter wherein the contents of a register may be passed in a recirculating fashion among a group of adjacent registers (e.g., ring buffers, barrel shifters, etc.).
  
[List of Patents for class 711 subclass 111]    111Accessing dynamic storage device:
 This subclass is indented under subclass 101.  Subject matter including accessing memory of the type where a storage medium is moved relative to a transducer (e.g., magnetic or paper tape, punched cards, etc.).
(1) Note. This and indented subclasses provide for dynamic storage combined with significant digital data processing system elements and functions.

SEE OR SEARCH CLASS:

235Registers,   subclasses 375+ for various systems controlled by data bearing records, subclasses 419+ for record controlled calculators, and subclasses 435+ for coded record sensors.
360Dynamic Magnetic Information Storage or Retrieval,   subclasses 72.1+ for locating a specific area in storage.
369Dynamic Information Storage or Retrieval,   various subclasses for the arrangement of information within dynamic storage alone.
  
[List of Patents for class 711 subclass 112]    112Direct access storage device (DASD):
 This subclass is indented under subclass 111.  Subject matter wherein devices employing a medium capable of being accessed directly and by so doing skipping past portions of the medium.
(1) Note. For purposes of this definition, memory devices known typically as disks, drums, etc., are considered to be of the direct access type whereas tapes are not.
  
[List of Patents for class 711 subclass 113]    113Caching:
 This subclass is indented under subclass 112.  Subject matter wherein the DASD is used as a dedicated hierarchically intermediate store or with a dedicated hierarchically intermediate store.
(1) Note. Caching in this subclass is (a) being performed by a DASD device or (b) being supplied by another device in combination with a DASD. Caching, per se, is classified elsewhere.

SEE OR SEARCH THIS CLASS, SUBCLASS:

117+,for hierarchical memory accessing and control and caching, per se.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclasses 49.1 through 50for associative memories and caches under their class definition.
  
[List of Patents for class 711 subclass 114]    114Arrayed (e.g., RAIDs):
 This subclass is indented under subclass 112.  Subject matter where a plurality of direct access devices are arranged in an array and files or portions thereof are stored on more than one of the direct access storage devices.
(1) Note. This subclass is appropriate for redundant arrays of inexpensive disks (RAID).
(2) Note. See the (6) Note to subclass 100 for systems directed to reliability and availability of DASDs. See the SEARCH CLASS notes below.

SEE OR SEARCH CLASS:

326Electronic Digital Logic Circuitry,   subclasses 39+ for programmable gate arrays.
710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclasses 20+ for systems directed to parallel data transfer.
714Error Detection/Correction and Fault Detection/Recovery,   subclasses 5.1 through 6.32for systems directed to reliability and availability of DASDs.
  
[List of Patents for class 711 subclass 115]    115Detachable memory:
 This subclass is indented under subclass 101.  Subject matter wherein the memory is of the solid-state type and can be readily physically connected and disconnected manually, without the aid of any tools, for temporary or transient purposes (e.g., replaceable memory cartridges, smart cards, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:

2,for addressing extended/expanded memory.

SEE OR SEARCH CLASS:

235Registers,   subclasses 441+ , 492, and 493 for electrical records and record sensors (i.e., IC cards).
463Amusement Devices: Games,   subclass 44 for a cartridge for game memory storage.
710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclass 300 for bus expanding/extending and hot card inserting.
  
[List of Patents for class 711 subclass 116]    116Bubble memory:
 This subclass is indented under subclass 101.  Subject matter wherein the memory is of the solid-state type comprising one or more series of persistent microscopically small magnetized bubbles on a thin film substrate.
  
[List of Patents for class 711 subclass 117]    117Hierarchical memories:
 This subclass is indented under subclass 100.  Subject matter wherein the memory being accessed or controlled is in an arrangement consisting of more than one ordered level of memory.
  
[List of Patents for class 711 subclass 118]    118Caching:
 This subclass is indented under subclass 117.  Subject matter wherein portions of the data stored in slower main memory are transferred to faster memory between processor(s) and the main memory.

SEE OR SEARCH THIS CLASS, SUBCLASS:

113,for systems where a cache memory is created within a DASD or dedicated to a DASD device.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclasses 49.1 through 50for associative memories and caches at the cell level.
  
[List of Patents for class 711 subclass 119]    119Multiple caches:
 This subclass is indented under subclass 118.  Subject matter employing plural cache memories arranged between at least one processor and at least one main memory.
  
[List of Patents for class 711 subclass 120]    120Parallel caches:
 This subclass is indented under subclass 119.  Subject matter further comprising means or steps for employing plural cache memories arranged at the same ordinal level between at least one processor and at least one main memory.
  
[List of Patents for class 711 subclass 121]    121Private caches:
 This subclass is indented under subclass 119.  Subject matter further comprising means or steps for employing plural cache memories where at least one of the caches is exclusively associated with a respective one of a plurality of processors.
  
[List of Patents for class 711 subclass 122]    122Hierarchical caches:
 This subclass is indented under subclass 119.  Subject matter further comprising means or steps for caching at a plurality of different hierarchical levels (e.g., main cache coupled to an on-chip cache).
  
[List of Patents for class 711 subclass 123]    123User data cache and instruction data cache:
 This subclass is indented under subclass 119.  Subject matter further comprising means or steps for employing separate or partitioned cache(s) for separately storing portions of instruction data and user data, respectively.
(1) Note. This physical separation of instruction data and user data is often referred to as Harvard architecture in the art and associated literature.
  
[List of Patents for class 711 subclass 124]    124Cross-interrogating:
 This subclass is indented under subclass 119.  Subject matter wherein an individual cache system must announce to other cache systems or check with other cache systems which may possibly contain a copy of a given cached location prior to or upon modification or appropriation of data at a given cached location.
  
[List of Patents for class 711 subclass 125]    125Instruction data cache:
 This subclass is indented under subclass 118.  Subject matter further comprising means or steps using a single cache dedicated to caching instruction data.

SEE OR SEARCH CLASS:

712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 200 through 219,220+ and 300 for instructional data processing, particularly 216+ for instruction dependency checking and resolution.
  
[List of Patents for class 711 subclass 126]    126User data cache:
 This subclass is indented under subclass 118.  Subject further comprising means or steps for using a single cache dedicated to caching user data.
  
[List of Patents for class 711 subclass 127]    127Interleaved:
 This subclass is indented under subclass 118.  Subject matter wherein consecutive cache memory locations are located in different memory components.

SEE OR SEARCH THIS CLASS, SUBCLASS:

5,for interleaving in combination with multiple memory modules with significant addressing.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclasses 230.03 and 230.04 for subject matter including plural banks or blocks and alternating between them.
  
[List of Patents for class 711 subclass 128]    128Associative:
 This subclass is indented under subclass 118.  Subject matter further comprising organizing a cache system where any block in main memory can be mapped to any block in the cache (fully associative) or where the cache is divided into sets of blocks and individual blocks of main memory are mapped to any of the blocks of a particular corresponding set (that is, for example, set associative).

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclasses 49.1 through 50for associative memories or content addressable memories (CAM), per se.
  
[List of Patents for class 711 subclass 129]    129Partitioned cache:
 This subclass is indented under subclass 118.  Subject matter further comprising means or steps for dividing the cache into independent sections or domains.
  
[List of Patents for class 711 subclass 130]    130Shared cache:
 This subclass is indented under subclass 118.  Subject matter further comprising means or steps for providing caching functions to a plurality of processors from single cache.
  
[List of Patents for class 711 subclass 131]    131Multiport cache:
 This subclass is indented under subclass 118.  Subject matter further comprising caches composed of multiport memory thereby allowing simultaneous reads from the cache by plural processors.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclass 230.05 for multiple port access devices.
  
[List of Patents for class 711 subclass 132]    132Stack cache:
 This subclass is indented under subclass 118.  Subject matter further comprising means or steps for caching stack data.
  
[List of Patents for class 711 subclass 133]    133Entry replacement strategy:
 This subclass is indented under subclass 118.  Subject matter including provisions for determining when the contents of a cache location may be replaced with other data.

SEE OR SEARCH THIS CLASS, SUBCLASS:

203+,for various generalized virtual addressing teachings.
  
[List of Patents for class 711 subclass 134]    134Combined replacement modes:
 This subclass is indented under subclass 133.  Subject matter using a combination that includes more than one entry replacement determination mode.
  
[List of Patents for class 711 subclass 135]    135Cache flushing:
 This subclass is indented under subclass 133.  Subject matter including provisions to clear or reset the cache or associated flags.
  
[List of Patents for class 711 subclass 136]    136Least recently used:
 This subclass is indented under subclass 133.  Subject matter where the determination is made based upon the time since the last access to the contents of a given location.
  
[List of Patents for class 711 subclass 137]    137Look-ahead:
 This subclass is indented under subclass 118.  Subject matter where selected data from main memory are retrieved into the cache prior to any request from the processor for the selected data.

SEE OR SEARCH CLASS:

712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclass 205 for fetching, 207 for prefetching, and 233+ for branch prediction.
  
[List of Patents for class 711 subclass 138]    138Cache bypassing:
 This subclass is indented under subclass 118.  Subject matter wherein selected memory accesses are not placed into or retrieved from the cache.
  
[List of Patents for class 711 subclass 139]    139No-cache flags:
 This subclass is indented under subclass 138.  Subject matter including provisions for marking selected locations of main memory so that the contents are not cached.
  
[List of Patents for class 711 subclass 140]    140Cache pipelining:
 This subclass is indented under subclass 118.  Subject matter wherein one access sequence to the cache memory is started before a prior access sequence is completed.

SEE OR SEARCH CLASS:

712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 205+ .
  
[List of Patents for class 711 subclass 141]    141Coherency:
 This subclass is indented under subclass 118.  Subject matter further comprising means or steps not specifically covered above for assuring that the data stored in the cache memory and those of the main memory are either identical or controlled so that stale and current data are not confused with each other.
(1) Note. The subject matter in this subclass is also called cache consistency or cache currency in the art.

SEE OR SEARCH THIS CLASS, SUBCLASS:

161+,for various reliability methods under accessing and control allowed by the (6) Note for subclass 100 above, such as archiving and backup.

SEE OR SEARCH CLASS:

707Data Processing: Database, Data Mining, and File Management or Data Structures,   subclasses 609 through 686for database maintenance including synchronizing, archiving, backing up and recovering databases, subclasses 687 through 704 for database integrity in databases, and subclasses 790 through 812 for database design including data structures and data structure management.
714Error Detection/Correction and Fault Detection/Recovery,   subclass 1 for reliability and availability in digital data processing systems, per se, including subclasses 5.1 through 6.32 for memory or peripheral subsystem affected fault recovery.
715Data Processing: Presentation Processing of Document, Operator Interface Processing, and Screen Saver Display Processing,   subclasses 255 through 272for developing or changing a document wherein one or more elements of document are added, deleted, or modified, or including means or steps for storing the resultant altered document or the alterations.
  
[List of Patents for class 711 subclass 142]    142Write-through:
 This subclass is indented under subclass 141.  Subject matter where, as contents of the cache are changed, the changes are also posted to main memory substantially simultaneously.
  
[List of Patents for class 711 subclass 143]    143Write-back:
 This subclass is indented under subclass 141.  Subject matter where, as contents of the cache are changed, the changes are not posted to main memory immediately, but rather changes to a block are posted upon the occurrence of a predetermined event.
  
[List of Patents for class 711 subclass 144]    144Cache status data bit:
 This subclass is indented under subclass 141.  Subject matter wherein coherency for each unit or block of data includes associated identifier bit(s) to indicate the validity status of an associated cached location.
(1) Note. For this subclass, validity status bits can indicate whether data are modified, valid, dirty, etc.
  
[List of Patents for class 711 subclass 145]    145Access control bit:
 This subclass is indented under subclass 141.  Subject matter wherein each unit or block of memory or cache includes associated identifier bit(s) to indicate ownership of or restricted access to the unit or block.
(1) Note. For this subclass, access control bits can indicate whether the associated cached location is exclusive, shared, read only, locked, etc.
  
[List of Patents for class 711 subclass 146]    146Snooping:
 This subclass is indented under subclass 141.  Subject matter further comprising cache memory monitoring an associated address bus to determine if access to a cached location occurs by another cache memory or other user (e.g., DMA, peripherals, etc.).

SEE OR SEARCH CLASS:

710Electrical Computers And Digital Data Processing Systems: Input/Output,   subclasses 100+ for system intraconnecting, particularly subclasses 107+ for bus access regulating.
  
[List of Patents for class 711 subclass 147]    147Shared memory area:
 This subclass is indented under subclass 100.  Subject matter wherein at least a portion of the memory being accessed or controlled is solid-state memory that iscommon to a plurality of users (e.g., a CPU and a DMA controller, multiple CPUs, etc.) or a plurality of tasks (e.g., in a multitasking system) or both.

SEE OR SEARCH THIS CLASS, SUBCLASS:

169,for memory access pipelining.

SEE OR SEARCH CLASS:

707Data Processing: Database, Data Mining, and File Management or Data Structures,   subclasses 609 through 686for database maintenance including synchronizing, archiving, backing up and recovering databases, subclasses 687 through 704 for data integrity in databases, subclasses 781 through 789 for access control to a database or file in a computer environment, subclasses 790 through 812 for database design including data structures and data structure management, subclasses 813 through 820 for garbage collection in database environments, and subclasses 821 through 831 for file management, file systems and file directory structures.
709Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring or Plural Processor Synchronization,   subclasses 213 through 216for a plurality of computers transferring data through one or more memories accessible by the plurality of computers.
718Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   subclasses 102 through 108for process scheduling involving balancing the work load or resources, memory use, register use, resource availability, time constraints, semaphores, and mutual exclusion mechanisms used for programs or process synchronization.
  
[List of Patents for class 711 subclass 148]    148Plural shared memories:
 This subclass is indented under subclass 147.  Subject matter wherein plural independent memories are shared.
  
[List of Patents for class 711 subclass 149]    149Multiport memory:
 This subclass is indented under subclass 147.  Subject matter including means or steps for controlling shared memory capable of supporting a plurality of simultaneous read accesses.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclass 230.05 for multiple port access devices.
  
[List of Patents for class 711 subclass 150]    150Simultaneous access regulation:
 This subclass is indented under subclass 147.  Subject matter including provisions for controlling simultaneous memory access requests.

SEE OR SEARCH CLASS:

710Electrical Computers And Digital Data Processing Systems: Input/Output,   subclasses 36+ for I/O access regulating; subclasses 107+ for access regulating and arbitration within a digital data processing system; subclasses 200 through 244 for generalized locking, polling, access arbitrating; and subclasses 260+ for interrupt processing.
  
[List of Patents for class 711 subclass 151]    151Prioritized access regulation:
 This subclass is indented under subclass 147.  Subject matter including provisions for assigning priority for use in handling simultaneous memory access requests.

SEE OR SEARCH CLASS:

710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclasses 36+ for I/O access regulating; subclasses 107+ for access regulating and arbitration within a digital data processing system; and subclasses 200 through 269 for generalized locking, polling, access arbitrating, and interrupt processing.
718Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   subclass 103 for priority scheduling of process (e.g., deciding which resources to use, deciding which jobs to do first and what order to do them; scheduling constraints may include resource characteristics such as performance, availability, data coherency, etc.).
  
[List of Patents for class 711 subclass 152]    152Memory access blocking:
 This subclass is indented under subclass 147.  Subject matter including provisions for selectively restricting access to memory areas.

SEE OR SEARCH CLASS:

710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclasses 36+ for I/O access regulating; subclasses 107+ for access regulating and arbitration within a digital data processing system; and subclasses 200 through 244 for generic access locking, access regulating, or access arbitration in data processing system.
  
[List of Patents for class 711 subclass 153]    153Shared memory partitioning:
 This subclass is indented under subclass 147.  Subject matter further comprising means for dividing or segmenting a given logical shared memory area into independent sections or domains.

SEE OR SEARCH CLASS:

707Data Processing: Database, Data Mining, and File Management or Data Structures,   subclasses 609 through 686for database maintenance including synchronizing, archiving, backing up and recovering databases, subclasses 687 through 704 for data integrity in databases, subclasses 781 through 789 for access control to a database or file in a computer environment, subclasses 790 through 812 for database design including data structures and data structure management, subclasses 813 through 820 for garbage collection in database environments, and subclasses 821 through 831 for file management, file systems and file directory structure.
712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclass 228 for processing control and instruction processing for context preserving; subclass 229 for processing control and instruction processing for mode switch or change.
717Data Processing: Software Development, Installation, and Management,   appropriate subclasses for significant details of the construction, analysis, or modification of computer languages.
718Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclasses for processing task management, in particular subclass 107 and 108 for multi-tasking and context switching.
719Electrical Computers and Digital Processing Systems: Interprogram Communication or Interprocess Communication (IPC),   appropriate subclassesfor interprogram or interprocess communication.
726Information Security,   subclasses 1 through 36for information security in computers or digital processing system.
  
[List of Patents for class 711 subclass 154]    154Control technique:
 This subclass is indented under subclass 100.  Subject matter including particular means or steps for controlling memory accesses not specifically provided for above.

SEE OR SEARCH CLASS:

714Error Detection/Correction and Fault Detection/Recovery,   subclass 702 for memory access, subclasses 710+ for replacement with spare memory component or portion of memory component, subclasses 763+ for memory testing and memory accessing with error correction.
  
[List of Patents for class 711 subclass 155]    155Read-modify-write (RMW):
 This subclass is indented under subclass 154.  Subject matter including provisions for performing an access operation where the contents of a given memory location are read and then overwritten in a single access operation.
  
[List of Patents for class 711 subclass 156]    156Status storage:
 This subclass is indented under subclass 154.  Subject matter including provisions for storing data associated with memory accessing and control.
(1) Note. Examples of status data include control status words, program status words, etc.
  
[List of Patents for class 711 subclass 157]    157Interleaving:
 This subclass is indented under subclass 154.  Subject matter wherein consecutive memory addresses are in nonadjacent physical locations.

SEE OR SEARCH THIS CLASS, SUBCLASS:

5,for interleaving in combination with multiple memory modules with significant addressing.
127,for cache interleaving where consecutive cache memory locations are located in different memory components.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclasses 230.03 and 230.04 for subject matter including plural banks or blocks and alternating between them.
  
[List of Patents for class 711 subclass 158]    158Prioritizing:
 This subclass is indented under subclass 154.  Subject matter including banks or modules which are arranged so that a given physical memory element has access priority over another.
  
[List of Patents for class 711 subclass 159]    159Entry replacement strategy:
 This subclass is indented under subclass 154.  Subject matter including provisions for determining when the data stored in a particular memory location may be replaced.

SEE OR SEARCH THIS CLASS, SUBCLASS:

133+,for cache entry replacement strategies.
  
[List of Patents for class 711 subclass 160]    160Least recently used (LRU):
 This subclass is indented under subclass 159.  Subject matter wherein the determination is made based upon the time since the last access to the contents of a given location.
  
[List of Patents for class 711 subclass 161]    161Archiving:
 This subclass is indented under subclass 154.  Subject matter wherein the control technique prevents the corruption, loss, alteration, or disclosure of data by storing.

SEE OR SEARCH CLASS:

380Cryptography,   appropriate subclasses for cryptographic processing in general.
713Electrical Computers and Digital Processing Systems: Support,   subclasses 150 through 181for multiple computer communication using cryptography and subclasses 187 and 188 for software program protection or computer virus detection in combination with data encryption.
714Error Detection/Correction and Fault Detection/Recovery,   subclass 1 for diagnostic testing or monitoring of a digital data processing system for reliability purposes comprising power fail-safe functions, fault detection, or anticipation of a failure; more specifically, subclasses 5.1 through 6.32 for memory or peripheral subsystem affected recovery, subclass 42 for memory component fault, and subclass 54 for storage content error detection or notification, subclasses 718-723 for reliability and availability in memory accessing and control such as isolating failed memory and storing redundant data with recitation of the recovery, fault, or failure.
717Data Processing: Software Development, Installation, and Management,   subclasses 168 through 172for software upgrading or updating and subclasses 174-178 for software installation including local and remote software (e.g., operating system, application program, and other executable program) loading, copying, or installing onto a target storage medium such as a hard disk, tape drive, or other memory device.
726Information Security,   subclasses 1 through 36for information security in computers or digital processing system.
  
[List of Patents for class 711 subclass 162]    162Backup:
 This subclass is indented under subclass 161.  Subject matter wherein a verbatim redundant copy of the data is made.

SEE OR SEARCH THIS CLASS, SUBCLASS:

165,for movement or transfers of data amongst locations within a same memory level.

SEE OR SEARCH CLASS:

714Error Detection/Correction and Fault Detection/Recovery,   subclasses 5.1 through 6.32and subclasses 718-723 for reliability and availability in memory accessing and control such as isolating failed memory and storing redundant data with recitation of the recovery, fault, or failure.
  
[List of Patents for class 711 subclass 163]    163Access limiting:
 This subclass is indented under subclass 154.  Subject matter wherein memory entry is restricted.

SEE OR SEARCH CLASS:

455Telecommunications,   subclass 26.1 for subject matter which blocks access to a signal source or otherwise limits usage of modulated carrier equipment.
710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclasses 36+ for access regulating of peripheral to computer or vice versa; subclasses 107+ for regulating access of processors or memories to a bus; and subclasses 200 through 244 for generic access locking, access regulating, or access arbitration in data processing system.
713Electrical Computers and Digital Processing Systems: Support,   subclasses 182 through 186for system access control based on cryptographic identification, and subclasses 187 and 188 for software program protection or computer virus detection in combination with data encryption.
714Error Detection/Correction and Fault Detection/Recovery,   subclasses 763+ for memory access block coding and subclass 805 for storage accessing error/fault detection techniques.
726Information Security,   subclasses 1 through 36for information security in computers or digital processing system.
  
[List of Patents for class 711 subclass 164]    164With password or key:
 This subclass is indented under subclass 163.  Subject matter wherein authorization code information (e.g., password, key other than encryption key, etc.) is required for memory access.
(1) Note. This subclass does not provide for cryptographic keys. See below.

SEE OR SEARCH CLASS:

455Telecommunications,   subclass 26.1 for subject matter which blocks access to a signal source or otherwise limits usage of modulated carrier equipment.
705Data Processing: Financial, Business Practice, Management, or Cost/Price Determination,   subclass 18 for handling security or user identification provision to either prevent unauthorized use or access.
713Electrical Computers and Digital Processing Systems: Support,   subclass 187 and 188 for software program protection or computer virus detection in combination with data encryption.
714Error Detection/Correction and Fault Detection/Recovery,   subclasses 763+ for memory access block coding and subclass 805 for storage accessing error/fault detection techniques.
726Information Security,   subclasses 1 through 36for information security in computers or digital processing system.
  
[List of Patents for class 711 subclass 165]    165Internal relocation:
 This subclass is indented under subclass 154.  Subject matter including provisions for moving or copying data from one location in a given memory to another location in the given memory or another memory at the same hierarchical level.
(1) Note. This subclass does not provide for DMA. See below.

SEE OR SEARCH CLASS:

710Electrical Computers And Digital Data Processing Systems: Input/Output,   subclasses 22+ for transferring data via the I/O mechanism of DMA.
  
[List of Patents for class 711 subclass 166]    166Resetting:
 This subclass is indented under subclass 154.  Subject matter including provisions for clearing or initializing the contents of a given memory location.
(1) Note. This subclass provides for setting a portion of memory to an initial condition (e.g., filling all locations with zeros).

SEE OR SEARCH CLASS:

713Electrical Computers and Digital Processing Systems: Support,   subclass 1 for digital data processing system initialization or configuration (e.g., initializing, setup, configuration, or resetting) allocating extended or expanded memory, speci device drivers, paths, files, buffers, disk management, etc.; subclass 2 for loading initialization program (e.g., booting, BIOS, IPL, bootstrap, etc.); and subclass 100 for reconfiguring (e.g., changing system settings) of system settings, per se.
  
[List of Patents for class 711 subclass 167]    167Access timing:
 This subclass is indented under subclass 100.  Subject matter including provisions for controlling or coordinating the sequence of operations that make up a memory access.

SEE OR SEARCH CLASS:

326Electronic Digital Logic Circuitry,   subclasses 93 through 98for clocking or synchronizing of logic stages or gates.
370Multiplex Communications,   subclass 507 wherein the clock frequency adjustment of one station is based upon information about status of clock signals originating at other stations of the system.
375Pulse or Digital Communications,   subclasses 354+ for synchronizing the operation of pulse or digital receiving or transmitting mechanisms.
709Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring or Plural Processor Synchronization,   subclass 248 for multicomputer synchronization in a network.
710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclass 61 for synchronous data transfer in I/O process timing.
712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 245 through 248for processing sequence control.
713Electrical Computers and Digital Processing Systems: Support,   subclasses 400+ for details relating to the timing control or timing regulation of any one or combination of digital data processing system components according to a periodic sequence of clock/ timing pulses (e.g., synchronous time control, time delay, cycle control, cycle steal, etc.).
714Error Detection/Correction and Fault Detection/Recovery,   subclass 12 for fault recovery synchronization of redundantly operating processors.
718Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclassesfor task and process scheduling.
  
[List of Patents for class 711 subclass 168]    168Concurrent accessing:
 This subclass is indented under subclass 167.  Subject matter further including means or steps wherein multiple memory accesses are initiated substantially simultaneously.

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718Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   subclass 107 and 108 for multitasking and time sharing/slicing.
  
[List of Patents for class 711 subclass 169]    169Memory access pipelining:
 This subclass is indented under subclass 167.  Subject matter further including means or steps wherein a first access to memory is initiated before a second access is completed.
(1) Note. Pipelined instruction data processing is classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH CLASS:

712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 205+ for instruction fetching, subclasses 214+ for instruction issuing, subclasses 233+ for branching instruction processing.
713Electrical Computers and Digital Processing Systems: Support,   subclass 2 for loading initializing program.
718Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclassesfor task management and control related to process or job execution.
  
[List of Patents for class 711 subclass 170]    170Memory configuring:
 This subclass is indented under subclass 100.  Subject matter in which the allocation of memory space is specified or the layout is automatically determined.
(1) Note. Configuration at booting via software is classified elsewhere in this class. See the SEARCH THIS CLASS, SUBCLASS notes below.
(2) Note. Assigning operating characteristics to peripherals is classified elsewhere in this class. See the SEARCH THIS CLASS, SUBCLASS notes below.

SEE OR SEARCH CLASS:

707Data Processing: Database, Data Mining, and File Management or Data Structures,   subclasses 609 through 686for database maintenance including synchronizing, archiving, backing up and recovering databases; subclasses 687 through 704 for data integrity in databases; subclasses 781 through 789 for access control to a database or file in a computer environment; subclasses 790 through 812 for database design including data structures and data structure management; subclasses 813 through 820 for garbage collection in database environments, and subclasses 821 through 831 for file management, file systems and file directory structures.
709Electrical Computers and Digital Processing Systems: Multicomputer Data Transferring or Plural Processor Synchronization,   subclasses 220 through 222for network computer configuring.
710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclasses 8+ for assigning operating characteristics to peripherals or peripheral configuring and subclass 104 for utilizing a hardware structure for providing to a digital data processing system component the arrangement of the digital data processing system including characteristics of the digital data processing system"s components.
712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclass 228 for processing control and instruction processing for context preserving, subclass 229 for processing control and instruction processing for mode switch or change.
713Electrical Computers and Digital Processing Systems: Support,   subclasses 1+ for digital data processing system initialization or configuration (e.g., initializing, set up, configuration, or resetting) allocating extended or expanded memory, specifying device driver, path, file, buffer, disk management, etc.; subclass 100 for reconfiguring of system setting, per se.
714Error Detection/Correction and Fault Detection/Recovery,   subclasses 3+ for reconfiguring in the event of a fault under fault recovery, reliability, and availability.
718Electrical Computers and Digital Processing Systems: Virtual Machine Task or Process Management or Task Management/Control,   appropriate subclasses for task management, in particular subclass 104 for resource allocation (e.g., deciding how best to use the available resources to get the job done) and also subclasses 107 and 108 for multitasking and context switching.
  
[List of Patents for class 711 subclass 171]    171Based on data size:
 This subclass is indented under subclass 170.  Subject matter comprising means or steps for allocating memory space based on the amount of storage space required.
  
[List of Patents for class 711 subclass 172]    172Based on component size:
 This subclass is indented under subclass 170.  Subject matter comprising means or steps for allocating memory based on the size of each physical solid-state memory.
  
[List of Patents for class 711 subclass 173]    173Memory partitioning:
 This subclass is indented under subclass 170.  Subject matter further comprising means for dividing or segmenting a given logical memory into independent sections or domains.
  
[List of Patents for class 711 subclass 200]    200ADDRESS FORMATION:
 This subclass is indented under the class definition.  Subject matter comprising means or steps for determining or modifying a value which specifies a location in at least one memory.
(1) Note. The subject matter of this subclass and the subclasses thereunder includes, for example, virtual memory addressing, address translation, translation look-aside buffers (TLBs), boundary checking, and page-mode addressing.
(2) Note. The subject matter also includes deriving new address data from existing address data.
(3) Note. The location in memory may include data for forming further an address (e.g., address mapping is classified herein).
(4) Note. Means or steps for addressing or for storing data in one or more memory cells of a storage medium having one or more specific, internal cell elements is classified elsewhere. See the SEARCH CLASS notes below.

SEE OR SEARCH THIS CLASS, SUBCLASS:

1,for addressing combined with specific memory configurations (e.g., extended/expanded memory, cache memory, dynamic memory, etc.).
3,for cache memory addressing.
101,through 116, for storage accessing and control for various memory compositions (e.g., ROM, RAM, CAM, dynamic, detachable, bubble, etc.) with more than nominal data processing.

SEE OR SEARCH CLASS:

326Electronic Digital Logic Circuitry,   subclasses 104 through 108for digital logic decoding circuits in general.
340Communications: Electrical,   subclasses 9.1 through 9.17for selective communication addressing and subclasses 14.1-14.69 for selective decoder matrix which may be used for control or as a switching means.
345Computer Graphics Processing and Selective Visual Display Systems,   subclasses 530 through 574for processing indices to locations (or addresses) of stored data elements in a computer graphic processing system.
360Dynamic Magnetic Information Storage or Retrieval,   subclass 72.2 for addressing and control of recording mechanism to locate the selected area.
365Static Information Storage and Retrieval,   subclass 189.011 for read/write circuits and subclasses 230.01+ for addressing of addressable, static single storage elements or plural elements of the same type.
369Dynamic Information Storage or Retrieval,   various subclasses for record carriers and systems wherein information is stored and retrieved by interaction with a medium and there is relative motion between a medium and a transducer. Particularly, see subclasses 30.01 through 41.01for selective addressing of dynamic storage medium.
370Multiplex Communications,   appropriate subclasses for multiplex switching techniques similar to addressing and the handling of memoryinformation signals (e.g., subclasses 351+ for packetized multiplexed communications).
704Data Processing: Speech Signal Processing, Linguistics, Language Translation, and Audio Compression/Decompression,   subclasses 2+ for memory control scheme combined with linguistics.
707Data Processing: Database, Data Mining, and File Management or Data Structures,   subclasses 609 through 686for database maintenance including synchronizing, archiving, backing up and recovering databases, subclasses 687 through 704 for data integrity in databases, subclasses 781 through 789 for access control to a database or file in a computer environment, subclasses 790 through 812 for database design including data structures and data structure management, subclasses 813 through 820 for garbage collection in database environments, and subclasses 821 through 831 for file management, file systems and file directory structures.
710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclasses 3 through 4for Input/Output addressing; subclass 9 for address assignment for configuring peripherals, subclasses 22-28 for direct memory accessing including addressing techniques; and subclass 316 for system intra-connecting switching.
712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 208+ for instruction decoding involving start or initial address generation; subclass 230 for generating the address of the next micro-instruction.
  
[List of Patents for class 711 subclass 201]    201Slip control, misaligning, boundary alignment:
 This subclass is indented under subclass 200.  Subject matter wherein the value determination takes into account a memory size constraint.
(1) Note. This subclass will accept range or limit checking, boundary crossing, and related memory boundary issues (e.g., (a) handling a boundary fixed length field to accommodate data size or position and boundary checking and (b) incrementing addresses within a page).
  
[List of Patents for class 711 subclass 202]    202Address mapping (e.g., conversion, translation):
 This subclass is indented under subclass 200.  Subject matter including translating (i.e., converting) processormemoryaddress data to physical memoryaddress data through a mechanism which defines a correspondence between the addresses.
(1) Note. The subject matter in this and the indented subclasses is aimed at determining a physical address using a mapping technique.
(2) Note. Classification here is proper for direct mapping for a segmented memory not being used in a virtual memory system.
  
[List of Patents for class 711 subclass 203]    203Virtual addressing:
 This subclass is indented under subclass 202.  Subject matter wherein the mapping allows an application to view available memory resources as a uniform primary memory.

SEE OR SEARCH THIS CLASS, SUBCLASS:

6,for address mapping for virtual machines.
  
[List of Patents for class 711 subclass 204]    204Predicting, look-ahead:
 This subclass is indented under subclass 203.  Subject matter wherein means or steps are utilized for optimizing address determination by, for example, anticipating a next address or prefetching addresses.

SEE OR SEARCH CLASS:

712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 205+ for instruction fetching, subclass 207 for profetching of instructions and 233+ for branch prediction.
  
[List of Patents for class 711 subclass 205]    205Directories and tables (e.g., DLAT, TLB):
 This subclass is indented under subclass 204.  Subject matter wherein a memory space is employed for registering indexes and the like to real or physical address spaces in a predicting or look-ahead arrangement.
(1) Note. A directory table is a mechanism for storing virtual (i.e., logical) to physical (i.e., real, absolute) address translation entries that are used in combination with methods of predicting or prefetching.
(2) Note. DLAT is a term of art referring to Directory Look-Aside Table; TLB is a term of art referring to Translation Look-Aside Buffer.
  
[List of Patents for class 711 subclass 206]    206Translation tables (e.g., segment and page table or map):
 This subclass is indented under subclass 203.  Subject matter wherein directories (e.g., maps) are employed for converting address data in a first form (e.g., virtual, logical) to address data in a second form (e.g., physical, absolute).
(1) Note. This subclass and its indented subclasses are intended for generalized applications of tables not classifiable in the combinations above.
(2) Note. This area also provides for mechanisms for storing virtual (i.e., logical) to physical (i.e., real, absolute) address translation entries that are of general use in virtual memory.
(3) Note. This subclass will accept table walking which generally requires accesses to main memory.
  
[List of Patents for class 711 subclass 207]    207Directory tables (e.g., DLAT, TLB):
 This subclass is indented under subclass 206.  Subject matter wherein a memory space is employed for registering indexes and the like to real or physical address spaces.
(1) Note. These mechanisms convert address data from a virtual address to a physical address without the need for accessing translation tables in main memory (e.g., utilizing cache for virtual to physical translation).
(2) Note. DLAT is a term of art referring to Directory Look-Aside Table; TLB is a term of art referring to Translation Look-Aside Buffer.

SEE OR SEARCH THIS CLASS, SUBCLASS:

3,for cache memory addressing.
  
[List of Patents for class 711 subclass 208]    208Segment or page table descriptor:
 This subclass is indented under subclass 206.  Subject matter wherein an entry, word, or other data is maintained and is utilized in the translation.
  
[List of Patents for class 711 subclass 209]    209Including plural logical address spaces, pages, segments, blocks:
 This subclass is indented under subclass 203.  Subject matter wherein portions of memory are organized or managed in accordance with a predetermined mapping scheme.
(1) Note. This subclass includes art directed to addressing variable-sized pages, segments, and blocks.
  
[List of Patents for class 711 subclass 210]    210Resolving conflict, coherency, or synonym problem:
 This subclass is indented under subclass 202.  Subject matter including compensating for situations when addresses map to the same location (e.g., synonym problems or alias addresses).

SEE OR SEARCH CLASS:

714Error Detection/Correction and Fault Detection/Recovery,   subclass 180 for reliability and availability in general in digital data processing systems.
  
[List of Patents for class 711 subclass 211]    211Address multiplexing or address bus manipulation:
 This subclass is indented under subclass 200.  Subject matter including address bus modifying, multiplexing addresses, or adapting to various bus widths.

SEE OR SEARCH CLASS:

710Electrical Computers and Digital Data Processing Systems: Input/Output,   subclass 300 for bus extending or expanding and subclasses 305-317 for bus architectures.
  
[List of Patents for class 711 subclass 212]    212Varying address bit-length or size:
 This subclass is indented under subclass 200.  Subject matter wherein bits are added or subtracted from existing address data to generate other address data.
  
[List of Patents for class 711 subclass 213]    213Generating prefetch, look-ahead, jump, or predictive address:
 This subclass is indented under subclass 200.  Subject matter wherein look-ahead, predictive, or jump address data are formed.
(1) Note. Prefetching, look-ahead, etc., for virtual memory addressing are classified elsewhere.

SEE OR SEARCH THIS CLASS, SUBCLASS:

203+,for virtual memory addressing.

SEE OR SEARCH CLASS:

712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 205+ and 207 and 233+ respectively.
  
[List of Patents for class 711 subclass 214]    214Operand address generation:
 This subclass is indented under subclass 200.  Subject matter wherein data relevant to an instruction and used by an instruction are used to form the address.

SEE OR SEARCH CLASS:

712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   subclasses 200 through 219,220+ and 300 for instruction processing, particularly subclasses 233 through 244 for branching instruction processing.
  
[List of Patents for class 711 subclass 215]    215In response to microinstruction:
 This subclass is indented under subclass 200.  Subject matter wherein microcode is stored in memory and particular addressing mechanisms at the microinstruction level are employed.

SEE OR SEARCH CLASS:

712Electrical Computers and Digital Processing Systems: Processing Architectures and Instruction Processing (e.g., Processors),   particularly subclasses 200 through 219,220+ and 300 for instruction processing, particularly 245+ for microsequencing processing; and subclasses 1+ for digital data processing system architecture.
  
[List of Patents for class 711 subclass 216]    216Hashing:
 This subclass is indented under subclass 200.  Subject matter wherein an address value (i.e., key other than an encryption key) is manipulated to form an index value.
(1) Note. This subclass does not provide for cryptographic keys. See below.

SEE OR SEARCH CLASS:

707Data Processing: Database, Data Mining, and File Management or Data Structures,   subclass 698 for database integrity using hash, subclasses 705 through 721 for database searching, per se, and subclass 747 for hash in index generation.
713Electrical Computers and Digital Processing Systems: Support,   subclass 187 and 188 for software program protection or computer virus detection in combination with data encryption.
726Information Security,   subclasses 1 through 36for information security in computers or digital processing system.
  
[List of Patents for class 711 subclass 217]    217Generating a particular pattern/sequence of addresses:
 This subclass is indented under subclass 200.  Subject matter wherein values specifying memory locations are determined according to a predetermined algorithm.

SEE OR SEARCH CLASS:

365Static Information Storage and Retrieval,   subclasses 230.03 and 230.04 for subject matter including plural banks or blocks and alternating between them.
714Error Detection/Correction and Fault Detection/Recovery,   subclasses 718 through 720for testing memories utilizing patterns of addresses and data.
  
[List of Patents for class 711 subclass 218]    218Sequential addresses generation:
 This subclass is indented under subclass 217.  Subject matter wherein the pattern created is seriatim.

SEE OR SEARCH CLASS:

377Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems,   appropriate subclasses for generic pulse counting circuits and systems.
  
[List of Patents for class 711 subclass 219]    219Incrementing, decrementing, or shiftingcircuitry:
 This subclass is indented under subclass 200.  Subject matter utilizing particular hardware that adds by 1, subtracts by 1, and multiplies or divides by 2n (where n is an integer).

SEE OR SEARCH CLASS:

377Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems,   appropriate subclasses for generic pulse counting circuits and systems.
  
[List of Patents for class 711 subclass 220]    220Combining two or more values to create address:
 This subclass is indented under subclass 200.  Subject matter wherein results from the interaction of two or more other data provide the address (e.g., generalized indirect addressing, indexing, prefixing, base + sag/tag + set, bit insertion).
  
[List of Patents for class 711 subclass 221]    221Using table:
 This subclass is indented under subclass 200.  Subject matter having a memory space of general utility for registering indexes and like data related to address generation (e.g., fixed offsets, conditions, or status).

SEE OR SEARCH THIS CLASS, SUBCLASS:

202+,for tables used in mapping or translating.
  

E-SUBCLASSES

NOTE—E-subclasses in USPC Class 711/E12.001-E12.103 were created as duplicates of EPO groups in G06F 12/00 and its indents. With the implementation of CPC, these E-subclasses should no longer be used. Instead, use CPC groups in G06F 12/00 and its indents.

The E-subclasses in U.S. Class 711 provide for methods and apparatus for addressing or allocating computer memory space including space management and address translation. They also provide for methods and means for protecting against unauthorized use of memory and protection against loss of memory contents.

[List of Patents for class 711 subclass E12.001]    E12.001ACCESSING, ADDRESSING, OR ALLOCATING WITHIN MEMORY SYSTEMS OR ARCHITECTURES:
 This main group provides for methods and apparatus for addressing or allocating computer memory space including space management and address translation. It also provides for methods and means for protecting against unauthorized use of memory and protection against loss of memory contents. This subclass is substantially the same in scope as ECLA classification G06F12/00.
  
[List of Patents for class 711 subclass E12.002]    E12.002Addressing or allocation; relocation:
 This subclass is indented under subclass E12.001. This subclass is substantially the same in scope as ECLA classification G06F12/02.
  
[List of Patents for class 711 subclass E12.003]    E12.003With multidimensional access, e.g., row/column, matrix, etc.:
 This subclass is indented under subclass E12.002. This subclass is substantially the same in scope as ECLA classification G06F12/02B.
  
[List of Patents for class 711 subclass E12.004]    E12.004With look-ahead addressing means:
 This subclass is indented under subclass E12.002. This subclass is substantially the same in scope as ECLA classification G06F12/02C.
  
[List of Patents for class 711 subclass E12.005]    E12.005User addresses space allocation, e.g., contiguous or noncontiguous base addressing, etc.:
 This subclass is indented under subclass E12.002. This subclass is substantially the same in scope as ECLA classification G06F12/02D.
  
[List of Patents for class 711 subclass E12.006]    E12.006Free address space management:
 This subclass is indented under subclass E12.005. This subclass is substantially the same in scope as ECLA classification G06F12/02D2.
  
[List of Patents for class 711 subclass E12.007]    E12.007In block-addressed memory:
 This subclass is indented under subclass E12.006. This subclass is substantially the same in scope as ECLA classification G06F12/02D2E.
  
[List of Patents for class 711 subclass E12.008]    E12.008In block-erasable memory, e.g., flash memory etc.:
 This subclass is indented under subclass E12.007. This subclass is substantially the same in scope as ECLA classification G06F12/02D2E2.
  
[List of Patents for class 711 subclass E12.009]    E12.009Garbage collection, i.e., reclamation of unreferenced memory:
 This subclass is indented under subclass E12.006. This subclass is substantially the same in scope as ECLA classification G06F12/02D2G.
  
[List of Patents for class 711 subclass E12.01]    E12.01Using reference counting:
 This subclass is indented under subclass E12.009. This subclass is substantially the same in scope as ECLA classification G06F12/02D2G2.
  
[List of Patents for class 711 subclass E12.011]    E12.011Incremental or concurrent garbage collection, e.g., in real-time systems, etc.:
 This subclass is indented under subclass E12.009. This subclass is substantially the same in scope as ECLA classification G06F12/02D2G4.
  
[List of Patents for class 711 subclass E12.012]    E12.012Generational garbage collection:
 This subclass is indented under subclass E12.011. This subclass is substantially the same in scope as ECLA classification G06F12/02D2G4G.
  
[List of Patents for class 711 subclass E12.013]    E12.013Multiple users address space allocation, e.g., using different base addresses, etc.:
 This subclass is indented under subclass E12.005. This subclass is substantially the same in scope as ECLA classification G06F12/02D4.
  
[List of Patents for class 711 subclass E12.014]    E12.014Using tables or multilevel address translation means:
 This subclass is indented under subclass E12.005. This subclass is substantially the same in scope as ECLA classification G06F12/02D6.
  
[List of Patents for class 711 subclass E12.015]    E12.015Addressing variable-length words or parts of words:
 This subclass is indented under subclass E12.002. This subclass is substantially the same in scope as ECLA classification G06F12/04.
  
[List of Patents for class 711 subclass E12.016]    E12.016In hierarchically structured memory systems, e.g., virtual memory systems, etc.:
 This subclass is indented under subclass E12.002. This subclass is substantially the same in scope as ECLA classification G06F12/08.
  
[List of Patents for class 711 subclass E12.017]    E12.017Addressing of memory level in which access to desired data or data block requires associative addressing means, e.g. cache, etc.:
 This subclass is indented under subclass E12.016. This subclass is substantially the same in scope as ECLA classification G06F12/08B.
  
[List of Patents for class 711 subclass E12.018]    E12.018Using pseudo-associative means, e.g., set-associative, hashing, etc.:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B10.
  
[List of Patents for class 711 subclass E12.019]    E12.019For peripheral storage systems, e.g., disc cache, etc.:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B12.
  
[List of Patents for class 711 subclass E12.02]    E12.02With dedicated cache, e.g., instruction or stack, etc.:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B14.
  
[List of Patents for class 711 subclass E12.021]    E12.021Using selective caching, e.g., bypass, partial write, etc.:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B18.
  
[List of Patents for class 711 subclass E12.022]    E12.022Using clearing, invalidating, or resetting means:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B20.
  
[List of Patents for class 711 subclass E12.023]    E12.023Multi-user, multiprocessor, multiprocessing cache systems:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B4.
  
[List of Patents for class 711 subclass E12.024]    E12.024With multilevel cache hierarchies:
 This subclass is indented under subclass E12.023. This subclass is substantially the same in scope as ECLA classification G06F12/08B4L.
  
[List of Patents for class 711 subclass E12.025]    E12.025With network or matrix configuration:
 This subclass is indented under subclass E12.023. This subclass is substantially the same in scope as ECLA classification G06F12/08B4N.
  
[List of Patents for class 711 subclass E12.026]    E12.026Cache consistency protocols:
 This subclass is indented under subclass E12.023. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P.
  
[List of Patents for class 711 subclass E12.027]    E12.027Using directory methods:
 This subclass is indented under subclass E12.026. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P2.
  
[List of Patents for class 711 subclass E12.028]    E12.028Copy directories:
 This subclass is indented under subclass E12.027. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P2C.

SEE OR SEARCH THIS CLASS, SUBCLASS:

E12.033,for local copy tags for implementing a bus snooping protocol.
  
[List of Patents for class 711 subclass E12.029]    E12.029Associative directories:
 This subclass is indented under subclass E12.027. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P2A.
  
[List of Patents for class 711 subclass E12.03]    E12.03Distributed directories, e.g., linked lists of caches, etc.:
 This subclass is indented under subclass E12.027. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P2D.
  
[List of Patents for class 711 subclass E12.031]    E12.031Limited pointers directories; state-only directories without pointers:
 This subclass is indented under subclass E12.027. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P2E.
  
[List of Patents for class 711 subclass E12.032]    E12.032With concurrent directory accessing, i.e., handling multiple concurrent coherency transactions:
 This subclass is indented under subclass E12.027. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P2R.
  
[List of Patents for class 711 subclass E12.033]    E12.033Using a bus scheme, e.g., with bus monitoring or watching means, etc.:
 This subclass is indented under subclass E12.026. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P4.
  
[List of Patents for class 711 subclass E12.034]    E12.034In combination with broadcast means, e.g., for invalidation or updating, etc.:
 This subclass is indented under subclass E12.033. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P4B.
  
[List of Patents for class 711 subclass E12.035]    E12.035For main memory peripheral accesses, e.g., I/O or DMA, etc.:
 This subclass is indented under subclass E12.033. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P4P.
  
[List of Patents for class 711 subclass E12.036]    E12.036With software control, e.g., noncacheable data, etc.:
 This subclass is indented under subclass E12.026. This subclass is substantially the same in scope as ECLA classification G06F12/08B4P6.
  
[List of Patents for class 711 subclass E12.037]    E12.037With cache invalidating means:
 This subclass is indented under subclass E12.023. This subclass is substantially the same in scope as ECLA classification G06F12/08B4J.
  
[List of Patents for class 711 subclass E12.038]    E12.038With shared cache:
 This subclass is indented under subclass E12.023. This subclass is substantially the same in scope as ECLA classification G06F12/08B4S.
  
[List of Patents for class 711 subclass E12.039]    E12.039For multiprocessing or multitasking:
 This subclass is indented under subclass E12.023. This subclass is substantially the same in scope as ECLA classification G06F12/08B4T.
  
[List of Patents for class 711 subclass E12.04]    E12.04With main memory updating:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B2.
  
[List of Patents for class 711 subclass E12.041]    E12.041Organization and technology of caches:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B22.
  
[List of Patents for class 711 subclass E12.042]    E12.042Of parts of caches, e.g., directory or tag array, etc.:
 This subclass is indented under subclass E12.041. This subclass is substantially the same in scope as ECLA classification G06F12/08B22D.
  
[List of Patents for class 711 subclass E12.043]    E12.043With plurality of cache hierarchy levels:
 This subclass is indented under subclass E12.041. This subclass is substantially the same in scope as ECLA classification G06F12/08B22L.
  
[List of Patents for class 711 subclass E12.044]    E12.044Multiple simultaneous or quasi-simultaneous cache accessing:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B6.
  
[List of Patents for class 711 subclass E12.045]    E12.045Cache with multiple tag or data arrays being simultaneously accessible:
 This subclass is indented under subclass E12.044. This subclass is substantially the same in scope as ECLA classification G06F12/08B6M.
  
[List of Patents for class 711 subclass E12.046]    E12.046Partitioned cache, e.g., separate instruction and operand caches, etc.:
 This subclass is indented under subclass E12.045. This subclass is substantially the same in scope as ECLA classification G06F12/08B6M2.
  
[List of Patents for class 711 subclass E12.047]    E12.047Cache with interleaved addressing:
 This subclass is indented under subclass E12.045. This subclass is substantially the same in scope as ECLA classification G06F12/08B6M4.
  
[List of Patents for class 711 subclass E12.048]    E12.048Cache with multi-port tag or data arrays:
 This subclass is indented under subclass E12.044. This subclass is substantially the same in scope as ECLA classification G06F12/08B6N.
  
[List of Patents for class 711 subclass E12.049]    E12.049Overlapped cache accessing, e.g., pipeline, etc.:
 This subclass is indented under subclass E12.044. This subclass is substantially the same in scope as ECLA classification G06F12/08B6P.
  
[List of Patents for class 711 subclass E12.05]    E12.05By multiple requestors:
 This subclass is indented under subclass E12.049. This subclass is substantially the same in scope as ECLA classification G06F12/08B6P2.
  
[List of Patents for class 711 subclass E12.051]    E12.051With reload from main memory:
 This subclass is indented under subclass E12.049. This subclass is substantially the same in scope as ECLA classification G06F12/08B6P4.
  
[List of Patents for class 711 subclass E12.052]    E12.052Cache access modes:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B16.
  
[List of Patents for class 711 subclass E12.053]    E12.053Burst mode:
 This subclass is indented under subclass E12.052. This subclass is substantially the same in scope as ECLA classification G06F12/08B16B.
  
[List of Patents for class 711 subclass E12.054]    E12.054Page mode:
 This subclass is indented under subclass E12.052. This subclass is substantially the same in scope as ECLA classification G06F12/08B16D.
  
[List of Patents for class 711 subclass E12.055]    E12.055Parallel mode, e.g., in parallel with main memory or CPU, etc.:
 This subclass is indented under subclass E12.052. This subclass is substantially the same in scope as ECLA classification G06F12/08B16F.
  
[List of Patents for class 711 subclass E12.056]    E12.056Variable-length word access:
 This subclass is indented under subclass E12.052. This subclass is substantially the same in scope as ECLA classification G06F12/08B16V.
  
[List of Patents for class 711 subclass E12.057]    E12.057With pre-fetch:
 This subclass is indented under subclass E12.017. This subclass is substantially the same in scope as ECLA classification G06F12/08B8.
  
[List of Patents for class 711 subclass E12.058]    E12.058Address translation:
 This subclass is indented under subclass E12.016. This subclass is substantially the same in scope as ECLA classification G06F12/10.
  
[List of Patents for class 711 subclass E12.059]    E12.059Using page tables, e.g., page table structures, etc.:
 This subclass is indented under subclass E12.058. This subclass is substantially the same in scope as ECLA classification G06F12/10D.
  
[List of Patents for class 711 subclass E12.06]    E12.06Involving hashing techniques, e.g., inverted page tables, etc.:
 This subclass is indented under subclass E12.059. This subclass is substantially the same in scope as ECLA classification G06F12/10D2.
  
[List of Patents for class 711 subclass E12.061]    E12.061Using associative or pseudo-associative address translation means, e.g., translation look-aside buffer (TLB), address translation buffer (ATB), address cache, etc.:
 This subclass is indented under subclass E12.058. This subclass is substantially the same in scope as ECLA classification G06F12/10L.
  
[List of Patents for class 711 subclass E12.062]    E12.062Associated with data cache:
 This subclass is indented under subclass E12.061. This subclass is substantially the same in scope as ECLA classification G06F12/10L4.
  
[List of Patents for class 711 subclass E12.063]    E12.063Data cache being concurrently physically addressed:
 This subclass is indented under subclass E12.062. This subclass is substantially the same in scope as ECLA classification G06F12/10L4P.
  
[List of Patents for class 711 subclass E12.064]    E12.064Data cache being concurrently virtually addressed:
 This subclass is indented under subclass E12.062. This subclass is substantially the same in scope as ECLA classification G06F12/10L4V.
  
[List of Patents for class 711 subclass E12.065]    E12.065For multiple virtual address spaces, e.g., segmentation, etc.:
 This subclass is indented under subclass E12.061. This subclass is substantially the same in scope as ECLA classification G06F12/10L2.
  
[List of Patents for class 711 subclass E12.066]    E12.066Decentralized address translation, e.g., in distributed shared memory systems, etc.:
 This subclass is indented under subclass E12.058. This subclass is substantially the same in scope as ECLA classification G06F12/10M.
  
[List of Patents for class 711 subclass E12.067]    E12.067For peripheral accesses to main memory, e.g., DMA, etc.:
 This subclass is indented under subclass E12.058. This subclass is substantially the same in scope as ECLA classification G06F12/10P.
  
[List of Patents for class 711 subclass E12.068]    E12.068For multiple virtual address spaces, e.g., segmentation, etc.:
 This subclass is indented under subclass E12.058. This subclass is substantially the same in scope as ECLA classification G06F12/10S.
  
[List of Patents for class 711 subclass E12.069]    E12.069Replacement control:
 This subclass is indented under subclass E12.016. This subclass is substantially the same in scope as ECLA classification G06F12/12.
  
[List of Patents for class 711 subclass E12.07]    E12.07Using replacement algorithm:
 This subclass is indented under subclass E12.069. This subclass is substantially the same in scope as ECLA classification G06F12/12B.
  
[List of Patents for class 711 subclass E12.071]    E12.071Of the least frequently used type, e.g., with individual count value, etc.:
 This subclass is indented under subclass E12.07. This subclass is substantially the same in scope as ECLA classification G06F12/12B2.
  
[List of Patents for class 711 subclass E12.072]    E12.072With age list, e.g., queue, MRU-LRU list, etc.:
 This subclass is indented under subclass E12.07. This subclass is substantially the same in scope as ECLA classification G06F12/12B4.
  
[List of Patents for class 711 subclass E12.073]    E12.073Being minimized, e.g., nonMRU, etc.:
 This subclass is indented under subclass E12.072. This subclass is substantially the same in scope as ECLA classification G06F12/12B4B.
  
[List of Patents for class 711 subclass E12.074]    E12.074Being generated by decoding array or storage:
 This subclass is indented under subclass E12.072. This subclass is substantially the same in scope as ECLA classification G06F12/12B4C.
  
[List of Patents for class 711 subclass E12.075]    E12.075With special data handling, e.g., priority of data or instructions, pinning, errors, etc.:
 This subclass is indented under subclass E12.07. This subclass is substantially the same in scope as ECLA classification G06F12/12B6.
  
[List of Patents for class 711 subclass E12.076]    E12.076Using additional replacement algorithm:
 This subclass is indented under subclass E12.075. This subclass is substantially the same in scope as ECLA classification G06F12/12B6B.
  
[List of Patents for class 711 subclass E12.077]    E12.077Adapted to multidimensional cache systems, e.g., set-associative, multi-cache, multi-set, or multilevel, etc.:
 This subclass is indented under subclass E12.07. This subclass is substantially the same in scope as ECLA classification G06F12/12B8.
  
[List of Patents for class 711 subclass E12.078]    E12.078Addressing physical block of locations, e.g., base addressing, module addressing, memory dedication, etc.:
 This subclass is indented under subclass E12.002. This subclass is substantially the same in scope as ECLA classification G06F12/06.
(1) Note. This group is limited to module addressing or allocation.

SEE OR SEARCH THIS CLASS, SUBCLASS:

E12.005,for base addressing.
  
[List of Patents for class 711 subclass E12.079]    E12.079Interleaved addressing:
 This subclass is indented under subclass E12.078. This subclass is substantially the same in scope as ECLA classification G06F12/06A.
  
[List of Patents for class 711 subclass E12.08]    E12.08Address space extension:
 This subclass is indented under subclass E12.078. This subclass is substantially the same in scope as ECLA classification G06F12/06C.
  
[List of Patents for class 711 subclass E12.081]    E12.081For memory modules:
 This subclass is indented under subclass E12.08. This subclass is substantially the same in scope as ECLA classification G06F12/06C2.
  
[List of Patents for class 711 subclass E12.082]    E12.082For I/O modules, e.g., memory mapped I/O, etc.:
 This subclass is indented under subclass E12.08. This subclass is substantially the same in scope as ECLA classification G06F12/06C4.
  
[List of Patents for class 711 subclass E12.083]    E12.083Combination of memories, e.g., ROM and RAM, etc., to permit replacement or supplementing of words in one module by words in another module:
 This subclass is indented under subclass E12.078. This subclass is substantially the same in scope as ECLA classification G06F12/06D.
  
[List of Patents for class 711 subclass E12.084]    E12.084Configuration or reconfiguration:
 This subclass is indented under subclass E12.078. This subclass is substantially the same in scope as ECLA classification G06F12/06K.
  
[List of Patents for class 711 subclass E12.085]    E12.085With centralized address assignment:
 This subclass is indented under subclass E12.084. This subclass is substantially the same in scope as ECLA classification G06F12/06K2.
  
[List of Patents for class 711 subclass E12.086]    E12.086And decentralized selection:
 This subclass is indented under subclass E12.085. This subclass is substantially the same in scope as ECLA classification G06F12/06K2D.
  
[List of Patents for class 711 subclass E12.087]    E12.087With decentralized address assignment:
 This subclass is indented under subclass E12.084. This subclass is substantially the same in scope as ECLA classification G06F12/06K4.
  
[List of Patents for class 711 subclass E12.088]    E12.088Address being position dependent:
 This subclass is indented under subclass E12.087. This subclass is substantially the same in scope as ECLA classification G06F12/06K4P.
  
[List of Patents for class 711 subclass E12.089]    E12.089With feedback, e.g., presence or absence of unit detected by addressing, overflow detection, etc.:
 This subclass is indented under subclass E12.084. This subclass is substantially the same in scope as ECLA classification G06F12/06K6.
  
[List of Patents for class 711 subclass E12.09]    E12.09Multi-configuration, e.g., local and global addressing, etc.:
 This subclass is indented under subclass E12.084. This subclass is substantially the same in scope as ECLA classification G06F12/06K8.
  
[List of Patents for class 711 subclass E12.091]    E12.091Protection against unauthorized use of memory:
 This subclass is indented under subclass E12.001. This subclass is substantially the same in scope as ECLA classification G06F12/14.
(1) Note. This subclass covers protection against unauthorized access to memory
  
[List of Patents for class 711 subclass E12.092]    E12.092By using cryptography:
 This subclass is indented under subclass E12.091. This subclass is substantially the same in scope as ECLA classification G06F12/14B.
  
[List of Patents for class 711 subclass E12.093]    E12.093By checking subject access rights:
 This subclass is indented under subclass E12.091. This subclass is substantially the same in scope as ECLA classification G06F12/14D.
  
[List of Patents for class 711 subclass E12.094]    E12.094Key-lock mechanism:
 This subclass is indented under subclass E12.093. This subclass is substantially the same in scope as ECLA classification G06F12/14D1.
  
[List of Patents for class 711 subclass E12.095]    E12.095In virtual system, e.g., with translation means, etc.:
 This subclass is indented under subclass E12.094. This subclass is substantially the same in scope as ECLA classification G06F12/14D1A.
  
[List of Patents for class 711 subclass E12.096]    E12.096Using access table, e.g., matrix or list, etc.:
 This subclass is indented under subclass E12.093. This subclass is substantially the same in scope as ECLA classification G06F12/14D2.
  
[List of Patents for class 711 subclass E12.097]    E12.097In hierarchical protection system, e.g., privilege levels, memory rings, etc.:
 This subclass is indented under subclass E12.093. This subclass is substantially the same in scope as ECLA classification G06F12/14D3.
  
[List of Patents for class 711 subclass E12.098]    E12.098By checking object accessibility, e.g., type of access defined by the memory independently of subject rights, etc.:
 This subclass is indented under subclass E12.091. This subclass is substantially the same in scope as ECLA classification G06F12/14C.
  
[List of Patents for class 711 subclass E12.099]    E12.099Protection being physical, e.g., cell, word, block, etc.:
 This subclass is indented under subclass E12.098. This subclass is substantially the same in scope as ECLA classification G06F12/14C1.
  
[List of Patents for class 711 subclass E12.1]    E12.1For module or part of module:
 This subclass is indented under subclass E12.099. This subclass is substantially the same in scope as ECLA classification G06F12/14C1A.
  
[List of Patents for class 711 subclass E12.101]    E12.101For range:
 This subclass is indented under subclass E12.099. This subclass is substantially the same in scope as ECLA classification G06F12/14C1B.
  
[List of Patents for class 711 subclass E12.102]    E12.102Protection being virtual, e.g., for virtual blocks or segments before translation mechanism, etc.:
 This subclass is indented under subclass E12.098. This subclass is substantially the same in scope as ECLA classification G06F12/14C2.
  
[List of Patents for class 711 subclass E12.103]    E12.103Protection against loss of memory contents:
 This subclass is indented under subclass E12.001. This subclass is substantially the same in scope as ECLA classification G06F12/16.
  

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