CPC Definition - Subclass H10W
This place covers:
(a) packages of devices and parts of such packages;
(b) interconnections of devices in chips, wafers, substrates or packages;
(c) connectors of devices in packages;
(d) other constructional details of devices in chips, wafers, substrates or packages, e.g. isolation regions between components of integrated devices; or
(e) detachable holders for supporting packaged chips in operation;
(f) the manufacture or treatment of aspects (a) - (e);
when aspects (a) - (e) are:
(1) applicable to devices covered by subclass H10B;
(2) applicable to devices covered by subclass H10D, except for semiconductor bodies or electrodes thereof, which are covered by groups H10D 62/00 and H10D 64/00; or
Attention is drawn to the following places, which may be of interest for search:
Printed circuits; Casings or constructional details of electrical apparatus; Manufacture of assemblages of electrical components | |
Constructional details of inorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation | |
Constructional details of individual inorganic light-emitting semiconductor devices having potential barriers | |
Constructional details of integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H 20/00 | |
Constructional details, e.g. interconnections, of organic electric solid-state devices | |
Interconnections of integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K 10/00 | |
Constructional details of organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation | |
Interconnections of devices controlled by radiation | |
Constructional details of organic light-emitting devices | |
Constructional details of integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K 50/00 | |
Constructional details of devices covered by H10K and not covered by groups H10K 10/80, H10K 30/80, H10K 50/80 or H10K 59/80 | |
Constructional details of thermoelectric devices comprising a junction of dissimilar materials | |
Constructional details of piezoelectric or electrostrictive devices | |
Constructional details of magnetostrictive devices | |
Constructional details of galvanomagnetic devices | |
Constructional details of Hall-effect devices | |
Constructional details of superconducting devices | |
Generic processes or apparatus for the manufacture or treatment of devices covered by class H10 |
In this place, the following terms or expressions are used with the meaning indicated:
bipolar | refers to semiconductor technology that involves multi-carrier-type operation, i.e. which simultaneously uses both electrons and holes as charge carriers |
body | the region of semiconductor (resp. solid-state) material(s) within which, or at the surface of which, the physical effects that are characteristic of the device occur, and any bordering semiconductor (resp. solid-state) material(s) that are contiguous with this region. Examples: in a field-effect transistor [FET], the physical effects occur in the channel region between the source and the drain. The semiconductor body includes the channel region, the source and drain regions, and any contiguous semiconductor material; in a light-emitting diode [LED], the physical effects occur at a junction of active semiconductor layers. The semiconductor body includes these active semiconductor layers and any contiguous semiconductor layers, such as buffer layers, possibly a growth substrate, that are between the cathode and anode electrodes; in a thermoelectric device, the solid-state body includes all solid-state materials in the path of current between the electrodes. |
chip | a piece of a wafer or a substrate that has been processed to contain devices therein or thereon. The expression "diced chip" refers to the result of dicing a wafer or a substrate into a plurality of chips, whereas "undiced chip" refers to a chip before dicing or with no dicing. |
component | an electric circuit element (e.g. diode, transistor, LED) that is one of a plurality of elements formed in or on a common substrate, e.g. in an integrated device |
container | a solid construction in which (one or more) devices are placed, or which is formed around the devices, for forming packaged devices. A container requires a partial or total enclosure and it may also comprise a filling. |
device | an electric circuit element (e.g. diode, transistor, LED);(depending on the context) can also refer to an integrated device (e.g. CMOS-IC, DRAM device). A device may be in the form of a bare or packaged chip. |
dopant | the atoms or compounds added to a material during doping |
doping | the intentional addition of a small quantity of atoms or compounds into a material to achieve a desired characteristic, e.g. to produce an n-type or p-type material. |
electrode | a conductive region in or on the semiconductor body or solid-state body of a device (and other than the body itself) which exerts an electrical influence on the body, irrespective of whether or not an external electrical connection is made thereto. The term covers metallic regions which exert electrical influence on the body through an insulating region (e.g. in intentional non-parasitic capacitive coupling), or inductive coupling arrangements. In a capacitive coupling arrangement, the dielectric region is regarded as part of the electrode. The overall conductive wiring may comprise multiple portions. In such a case, only the wiring portions that exert an electrical influence on the body are considered portions of the electrode. Examples: conductive layer(s) in direct physical contact with the body; conductive region(s) exerting an inductive coupling onto the body; a multilayer structure which exerts influence on the body through an insulating region, e.g. in intentional non-parasitic capacitive coupling. |
encapsulation | an enclosure consisting of (one or more) layers, e.g. comprising organic polymers, which at least partially enclose the (one or more) devices, thereby protecting them. An encapsulation is often used to hermetically seal devices. |
FET | field-effect transistor |
field-effect | refers to semiconductor technology wherein a voltage applied to a gate electrode creates an electric field that allows for control of current near the interface of the gate and the body, e.g. to create an inversion channel between the source and drain of a MOSFET |
individual | refers to: an electric circuit element not being an integrated device; or a component of an integrated device. Examples of individual devices include: diodes, transistors, photovoltaic cells, Josephson-junction devices, light-emitting diodes [LED], organic LEDs, or a single LED component within an integrated device. |
integrated circuit | an integrated device where all the electric circuit elements (e.g. diodes, transistors, LEDs) are formed in or on a common substrate, including interconnections between the elements |
integrated device | a device consisting of a plurality of semiconductor or other solid-state electric circuit elements formed in or on a common substrate |
interconnection | a conductive arrangement for conducting electric current from an electrode of a circuit element to another part of the circuit. Examples include metal wirings. |
MIS | metal-insulator-semiconductor |
MISFET | metal-insulator-semiconductor field-effect transistor |
MOS | metal-oxide-semiconductor |
package | the collection of all elements, which are external to the chip, that protect the chip or connect it to another object. Package therefore covers encapsulations, containers, package substrates, interposers, heatsinks or the like. Package does not include objects at a higher system level, like circuit boards and beyond, e.g. a housing in which the circuit board is enclosed. |
TFT | thin-film transistor |
unipolar | refers to semiconductor technology that primarily involves one type only of charge carrier, i.e. it involves either holes or electrons but not both |
via | an electrically or thermally conductive connection that passes vertically through a layer. Examples include through-hole vias, blind vias, buried vias, and vias connecting between traces of the back-end-of-line [BEOL] metallisations. |
wafer | can be one of the following: (a) a slice of semiconductor or electric solid-state active material. For example: a slice of silicon; a slice of a semiconducting compound, e.g. gallium nitride [GaN]; a slice of lithium tantalate [LiTaO3] for superconductor applications. (b) a multilayered laminate, having at least one layer of semiconductor or electric solid-state active material, the layer being meant to be processed into devices. For example: silicon-on-insulator [SOI]; silicon-on-glass [SOG]; silicon-on-sapphire [SOS]; a composite wafer comprising silicon carbide [SiC] on polycrystalline silicon [Si] support; a layer of semiconducting nanowires on glass. A wafer is typically processed by (e.g.) deposition, etching, doping or diffusion, and is then typically diced into chips. |
This place covers:
Isolation regions that are in wafers or semiconductor bodies and that are:
- directly between components of integrated devices (e.g. in the same plane as the components); or
- in the electrical path between components of integrated devices (e.g. below the plane of the components).
Attention is drawn to the following places, which may be of interest for search:
Insulating parts of interconnections within wafers or substrates, e.g. through-silicon vias [TSV] | |
Insulating parts of interconnections external to, wafers or substrates | |
Semiconductor bodies of inorganic semiconductor devices having potential barriers | |
Integrated devices comprising inorganic semiconductor devices |
Buried insulating layers, e.g. buried oxide layers, of semiconductor-on-insulator substrates are covered in group H10W 10/00.
Attention is drawn to the following places, which may be of interest for search:
Air gaps in insulating parts of interconnections external to wafers or substrates |
Attention is drawn to the following places, which may be of interest for search:
Highly-doped isolation regions in semiconductor bodies between components of integrated devices | |
Highly-doped interconnections within wafers or substrates | |
Semiconductor bodies, or regions thereof, of inorganic semiconductor devices having potential barriers | |
Integrated devices comprising inorganic semiconductor devices | |
Ion implantation into semiconductor materials of wafers, substrates or parts of devices | |
Diffusion of dopants within, into or out of semiconductor bodies or layers |
Groups H10W 70/00, H10W 72/00 and H10W 20/00 each cover interconnections, depending on the location of the interconnections.
Group H10W 20/00 covers interconnections that are not in the package. These interconnections are in chips, wafers or substrates other than package substrates. The interconnections may be at least partially surrounded by the semiconductor material of the wafers or by the material of the substrates (in group H10W 20/20), or may be on the wafers or substrates (e.g. in front-end-of-line [FEOL] or back-end-of-line [BEOL] metallisation layers within a chip).
Group H10W 70/00 covers interconnections in packages that are within package substrates, interposers or redistribution layers [RDL].
Group H10W 72/00 covers interconnections in packages that are in parts of the package other than in package substrates, interposers or redistribution layers. For example, bond wires between a chip and a package substrate.
Attention is drawn to the following places, which may be of interest for search:
Package substrates; Interposers; Redistribution layers [RDL] | |
Interconnections or connectors in packages other than in package substrates, interposers or redistribution layers | |
Electrically-conductive connections, in general | |
Printed circuits | |
Interconnections, e.g. lead-frames, bond wires or solder balls | |
Interconnections of active-matrix LED displays | |
Interconnections of integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K 10/00 | |
Interconnections of devices controlled by radiation | |
Constructional details of interconnections, e.g. terminals | |
Interconnections in thermoelectric devices comprising a junction of dissimilar materials | |
Interconnections in piezoelectric or electrostrictive devices | |
Formation of conductive or resistive materials | |
Etching of wafers, substrates or parts of devices |
This place covers:
Interconnections that provide a current path internal to wafers or substrates.
Attention is drawn to the following places, which may be of interest for search:
Interconnections in insulating or insulated package substrates, interposers or redistribution layers | |
Vias in insulating or insulated package substrates |
Attention is drawn to the following places, which may be of interest for search:
Redistribution layers outside of chips |
Contact plugs that directly contact the semiconductor body, and hence are electrodes, may be classified in this group.
Attention is drawn to the following places, which may be of interest for search:
Interconnections within wafers or substrates, e.g. through-silicon vias | |
Vias in insulating or insulated package substrates |
Attention is drawn to the following places, which may be of interest for search:
Air gaps as isolation regions in semiconductor bodies between components of integrated devices |
In this place, the following terms or expressions are used with the meaning indicated:
antifuse | a part of an interconnection that is capable of having its state changed from non-conductive to conductive |
fuse | a part of an interconnection that is capable of having its state changed from conductive to non-conductive |
This place does not cover:
Integrated devices comprising arrangements for thermal protection |
Attention is drawn to the following places, which may be of interest for search:
Arrangements for protection of devices other than thermal protection | |
Arrangements for thermal protection or thermal control of stacked chips | |
Modifications common to different types of electric apparatus to facilitate cooling, ventilating or heating | |
Arrangements for cooling, heating, ventilating or compensating for temperature fluctuations for inorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation | |
Arrangements for heat extraction or cooling for inorganic light-emitting devices | |
Arrangements for heating or cooling of organic light-emitting devices |
This place does not cover:
Arrangements for thermal protection |
Attention is drawn to the following places, which may be of interest for search:
Encapsulations | |
Containers | |
Arrangements for preventing damage to photovoltaic cells caused by corpuscular radiation |
This place covers:
Marks in or on the chips, wafers, substrates or packages of devices.
Groups H10W 70/00, H10W 72/00 and H10W 20/00 each cover interconnections, depending on the location of the interconnections.
Group H10W 20/00 covers interconnections that are not in the package. These interconnections are in chips, wafers or substrates other than package substrates. The interconnections may be at least partially surrounded by the semiconductor material of the wafers or by the material of the substrates (in group H10W 20/20), or may be on the wafers or substrates (e.g. in front-end-of-line [FEOL] or back-end-of-line [BEOL] metallisation layers within a chip).
Group H10W 70/00 covers interconnections in packages that are within package substrates, interposers or redistribution layers [RDL].
Group H10W 72/00 covers interconnections in packages that are in parts of the package other than in package substrates, interposers or redistribution layers. For example, bond wires between a chip and a package substrate.
Attention is drawn to the following places, which may be of interest for search:
Interconnections in chips, wafers or substrates | |
Interconnections in packages other than in package substrates, interposers or redistribution layers | |
Printed circuits | |
Apparatus or processes for manufacturing printed circuits |
In this place, the following terms or expressions are used with the meaning indicated:
redistribution layer | interconnections in the package, such as metal traces or vias, that laterally reroute ("redistribute") the chip's input/output [I/O] layout into a different, desired I/O pad layout for external connections. Examples include: fan-in RDLs [FI-RDL], i.e. for redistributing I/O signals from a larger chip to a smaller package substrate or interposer; and fan-out RDLs [FO-RDLs], i.e. for redistributing I/O signals from a smaller chip to a larger package substrate or interposer. |
In patent documents, the following abbreviations are often used:
RDL | Redistribution layer |
This place does not cover:
Leadframes |
Attention is drawn to the following places, which may be of interest for search:
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes | |
Insulating or insulated package substrates, interposers or redistribution layers between stacked chips | |
Printed circuits |
Attention is drawn to the following places, which may be of interest for search:
Conductive parts of interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes | |
Interconnections in printed circuit board |
Attention is drawn to the following places, which may be of interest for search:
Interconnections within wafers or substrates, e.g. through-silicon vias | |
Vias external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes |
This place covers:
Interconnections or connectors in parts of packages other than in package substrates, interposers or redistribution layers. For example, between a chip and a package substrate, or in an encapsulation.
Groups H10W 70/00, H10W 72/00 and H10W 20/00 each cover interconnections, depending on the location of the interconnections.
Group H10W 20/00 covers interconnections that are not in the package. These interconnections are in chips, wafers or substrates other than package substrates. The interconnections may be at least partially surrounded by the semiconductor material of the wafers or by the material of the substrates (in group H10W 20/20), or may be on the wafers or substrates (e.g. in front-end-of-line [FEOL] or back-end-of-line [BEOL] metallisation layers within a chip).
Group H10W 70/00 covers interconnections in packages that are within package substrates, interposers or redistribution layers [RDL].
Group H10W 72/00 covers interconnections in packages that are in parts of the package other than in package substrates, interposers or redistribution layers. For example, bond wires between a chip and a package substrate.
Attention is drawn to the following places, which may be of interest for search:
Interconnections in chips, wafers or substrates | |
Interconnections in insulated package substrates, interposers or redistribution layers [RDL] | |
Electrically-conductive connections, in general |
If a connector is directly on an electrode or interconnection, without an intervening bond pad, so that the electrode or interconnection acts as a bond pad, the electrode or interconnection may be classified in groups for bond pads.
In this place, the following terms or expressions are used with the meaning indicated:
connector | an element within a package for electrically or physically connecting chips or package parts to other chips, package parts or a circuit board (e.g. to a printed circuit board [PCB]) |
This place covers:
Bump connectors, dummy bumps or thermal bumps in packages. For example, a bump between a chip and a package substrate; or a bump on the surface of a package substrate opposite to a mounted chip.
Attention is drawn to the following places, which may be of interest for search:
Manufacture or treatment of bump connectors | |
Connecting or disconnecting of bump connectors | |
Underfills | |
Positions of bump connectors relative to package parts |
In this place, the following terms or expressions are used with the meaning indicated:
bump connector | a bump that provides electrical connection. Examples include solder balls or copper pillars. An electrically-conductive connector on the electrodes or bond pads of a chip or package part, for electrical connection between objects. Examples include solder balls or copper pillars. |
dummy bump | a bump having similar properties to a bump connector (such as shape or material), for purposes other than electrical connection, such as mechanical connection |
thermal bump | a bump having similar properties to a bump connector (such as shape or material), for purposes other than electrical connection, such as for thermal connection between objects |
In patent documents, the following words/expressions are often used as synonyms:
- "solder bump", "bump" and "solder ball"
This place covers:
Pads or under-bump metallurgy [UBM] for bump connectors.
Attention is drawn to the following places, which may be of interest for search:
Manufacture or treatment of die-attach connectors | |
Connecting or disconnecting of die-attach connectors | |
Underfills | |
Positions of die-attach connectors relative to package parts |
In this place, the following terms or expressions are used with the meaning indicated:
die-attach connector | a connector for bonding or mounting of a chip, primarily intended for mechanical connection. Examples include: (a) an insulating adhesive to connect the inactive surface of a chip to a package substrate; (b) a conductive solder or sintered layer to connect the inactive side of a chip to a leadframe. |
Attention is drawn to the following places, which may be of interest for search:
Manufacture or treatment of bond wires | |
Connecting or disconnecting of bond wires | |
Positions of bond wires relative to package parts |
In this place, the following terms or expressions are used with the meaning indicated:
bond wire | a conducting connector in the form of typically a flexible thread that is intended to be connected to an object by wirebonding methods, e.g. by thermocompression, ultrasonic or thermosonic methods |
Attention is drawn to the following places, which may be of interest for search:
Manufacture or treatment of strap connectors | |
Connecting or disconnecting of strap connectors | |
Positions of strap connectors relative to package parts |
In this place, the following terms or expressions are used with the meaning indicated:
strap connector | a conductive connector, often having a width that is of the scale of a chip's width, that is typically used for high-power applications |
This place covers:
Bond pads in general, i.e. where the nature of a related connector is unspecified or generic to multiple types of connectors.
Bond pads specially adapted for a specific type of connector are classified in a group covering the connector type. For example, bond pads specially adapted for wire connectors are classified in group H10W 72/59 and bond pads specially adapted for strap connectors are classified in group H10W 72/60.
Examples of places where the subject matter of this place is covered when specially adapted, used for a particular purpose, or incorporated in a larger system:
Bond pads specially adapted for bump connectors | |
Bond pads specially adapted for conductive adhesives | |
Bond pads specially adapted for bond wires | |
Bond pads specially adapted for strap connectors |
Attention is drawn to the following places, which may be of interest for search:
Manufacture or treatment of bond pads | |
Direct bonding of bond pads | |
Positions of direct-bonded bond pads relative to package parts |
Attention is drawn to the following places, which may be of interest for search:
Die-attach connectors | |
Encapsulations or containers for stacked chips | |
Encapsulations or containers for integrated devices, or assemblies of multiple devices, having inorganic photovoltaic cells | |
Coatings for inorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation | |
Encapsulations or containers for inorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation | |
Coatings for inorganic light-emitting devices | |
Encapsulations for inorganic light-emitting devices | |
Encapsulations for integrated devices, or assemblies of multiple devices, comprising at least one inorganic light-emitting device | |
Passivation, containers or encapsulations for organic devices specially adapted for rectifying, amplifying, oscillating or switching | |
Passivation, containers or encapsulations for organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation | |
Passivation, containers or encapsulations for organic light-emitting devices |
Attention is drawn to the following places, which may be of interest for search:
Detachable holders for supporting packaged chips in operation | |
Encapsulations or containers for stacked chips | |
Casings, cabinets or drawers for electric apparatus | |
Encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells | |
Containers or encapsulations of image sensors | |
Encapsulations or containers light-receiving devices | |
Packages for light-emitting devices | |
Containers for light-emitting devices |
This place covers:
Materials formed in containers before or after mounting chips in the container.
In this group, the phase of the fillings is determined at the operating temperature of the device.
This place covers:
Gettering materials formed in containers or matrix materials having gettering materials as components therein, which are formed in containers.
In this group, the phase of the fillings is determined at the operating temperature of the device.
Group H10W 78/00 covers the aspect of a holder being detachable, while other groups cover the holders.
For example, package substrates, containers or heat sinks that are detachable may be classified both in group H10W 78/00 and in the groups covering package substrates, containers or heat sinks.
Attention is drawn to the following places, which may be of interest for search:
Securing means for detachable heating or cooling arrangements, e.g. clamps | |
Package substrates; Interposers; Redistribution layers [RDL] | |
Printed circuits |
This place covers:
Direct bonding of:
- chips, e.g. chip-to-chip;
- wafers having devices and interconnections therein or thereon, e.g. wafer-to-wafer;
- substrates having devices and interconnections therein or thereon; or
- combinations thereof, e.g. chip-to-wafer.
Bonding of wafers or substrates either (i) before the step of making of any interconnections or (ii) before the step of packaging of devices, whichever step comes first, is covered in H10P 10/00. Aspects of bonding involving chips, wafers or substrates, which already have interconnections therein/thereon, are covered in group H10W 80/00.
Attention is drawn to the following places, which may be of interest for search:
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations | |
Bond pads, in general | |
Positions of direct-bonded bond pads relative to package parts |
In this place, the following terms or expressions are used with the meaning indicated:
direct bonding | bonding of two objects without the use of intervening bonding material (e.g. without solder or adhesive). Examples include: (a) direct pad-to-pad bonding; (b) direct insulator-to-insulator bonding; and (c) hybrid bonding, namely the combination of (a) and (b) above. |
This place covers:
The relative positions of multiple chips within a single package, e.g. adjacent chips in a single encapsulation.
The relative positions of multiple chips within multiple packages, e.g. one encapsulated chip on another encapsulated chip in a "package-on-package" configuration.
1. Package parts per se are covered by other groups of this subclass, e.g. encapsulations are covered by H10W 74/00.
Attention is drawn to the following places, which may be of interest for search:
Assemblies of multiple devices comprising at least one memory device covered by subclass H10B | |
Assemblies of multiple devices comprising at least one device covered by subclass H10D | |
Assemblies of multiple devices comprising at least one photovoltaic cell covered by group H10F 10/00 | |
Assemblies of multiple devices comprising at least one element covered by group H10F 30/00, e.g. comprising a photodiode | |
Assemblies of multiple devices comprising at least one light-emitting device covered by group H10H 20/00 | |
Assemblies of multiple devices comprising at least one organic radiation-sensitive element covered by group H10K 30/00 | |
Assemblies of multiple devices comprising at least one organic light-emitting element covered by group H10K 50/00 | |
Assemblies of multiple devices comprising at least one thermoelectric or thermomagnetic element covered by groups H10N 10/00 - H10N 15/00 | |
Assemblies of multiple devices comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N 30/00 - H10N 35/00 | |
Assemblies of multiple devices comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N 50/00 - H10N 52/00 | |
Assemblies of multiple devices comprising at least one superconducting element covered by group H10N 60/00 | |
Assemblies of multiple devices comprising at least one solid-state element covered by group H10N 70/00 | |
Assemblies of multiple devices comprising at least one bulk negative-resistance effect element covered by group H10N 80/00 |
The manufacture or treatment of elements covered by subclass of H10W where provision for the process exists in this subclass are covered by the groups that provide for it. For example, the manufacture or treatment of an encapsulation is covered by group H10W 74/01.
The manufacture or treatment of elements covered by this subclass that would be classified together with the part because no provision for the process exists in this subclass are covered by the group related to the part. For example, the manufacture or treatment of a bump connector should be classified in group H10W 72/20.
In this place, the following terms or expressions are used with the meaning indicated:
packaging | manufacture or treatment of a package or its parts |