Devices or arrangements for storage of digital or analogue information in which no relative movement takes place between an information storage element and a transducer; which incorporate a selecting-device for writing-in or reading-out the information into or from the store.

In this sub-class there exist three general main groups, G11C 5/00, G11C 7/00 and G11C 8/00, which cover aspects such as power supply, reading and writing arrangements and addressing arrangements that are common to many if not all types of memories. There are further main groups which are dedicated to one or more specific types of memory cell technologies. Within these, there may be specific sub-groups for aspects such as power supply or addressing which parallel the general groups. The convention is that, where a document describes a specific aspect for a specific cell technology without indicating its use with other cell types, it should only be classified under the technology group. If it is described as applicable to two cell types then it should be classified under each cell type and in the general group. Thus, for example, a sense amplifier for a resistive RAM would be classified under G11C 13/004, while a document applying the same sense amplifier to both ReRAM and flash memory would be further classified in G11C 16/26 and G11C 7/06.

G11C 29/00 is a further general group covering the aspects of testing and repair of memory devices. There are no cell-type specific sub-groups for these aspects and thus they are only classified in this place. However other aspects also covered in testing documents will be classified according to the rules of the previous paragraph.

Details of arrangements providing supporting functions for semiconductor memory devices, concerning protection against loss of information, memory layout and stacking, signal line and power line interconnection, memory modules and their electrical interconnections, and power supplies including backup supplies, as well as charge pumps, voltage and current reference generators as well as circuits for stabilization of voltages and currents, which are common to all semiconductor memories types covered by subclass G11C, as detailed in main groups G11C 13/00, G11C 14/00, G11C 16/00, G11C 17/00, G11C 19/00, G11C 21/00, G11C 23/00, G11C 25/00, G11C 27/00 as well as G11C 11/00.

This group covers the above mentioned aspects only when they are concerned with a semiconductor memory.

Furthermore, in the case where any of the above mentioned aspects are adapted to be used with a semiconductor memory of a specific type, such aspects should be classified in the relevant group covering that specific type of semiconductor device, as long as such a specific group is present.

If documents are clearly restricted to one specific cell type or memory technology they should not be classified here but in the group of said cell technology, unless there is no group for that cell technology. If documents mention applications to different types of cells then they can be classified here.

Geometrical layout considerations of the internal components of a memory device.

Layout considerations on a printed circuit board are covered by H05K 1/18.

Electrical aspects of memory modules such as e.g. SIMM, DIMM or flash memories.

Covering the detection of change in supply voltage, on the voltage or the ground side, in general.

Voluntary power down or standby arrangements.

Covering the characteristics of the power up and power down circuits, the standby circuits and recovery circuits.

All aspects of reading and writing of data to an address memory cell in general except the addressing of the cell. The addressing and row circuitry is covered in G11C 8/00. G11C 7/00 is more about column and input/output circuitry "In general" means that technology or cell specific documents are not covered here but in their respective groups.

If documents are clearly restricted to one specific cell type or memory technology they should not be classified here but in the group of said cell technology, unless there is no group for that cell technology. If documents mention applications to different types of cells then they can be classified here.

If refresh is concerned G11C 11/406 takes precedence.

Most of the current sense amplifiers (current mirrors based) and most of the multi stage sense amplifiers.

This is a recent group and most of the material about the control of sense amplifiers in general and about sense amplifier drivers is in G11C 7/06.

Input/output (I/0) data interface arrangements.

Covers all the synchronous memory data interfaces (Synclink, SDR, DDR, Rambus).

Serial interfaces (IC2, SPI, single wire) when applied to memories are mainly classified in G11C 5/066. Buses with Ring topologies (daisy chain or peer-to-peer buses) for memories are also covered in G11C 7/10, G11C 7/1051 and G11C 7/1078. Documents where the memory controller is the main aspect are in the G06F 13/16 groups. Data buses and bus protocols in general are in G06F 13/00.

In particular:

It also contains sometimes memories with ECC circuits. However these should be searched and classified in G06F 11/1044 .

The pipelining in clock synchronous and wave pipelining in clockless (asynchronous) memories.

"Interleaving" when referring to a bit line layout is classified in G11C 7/18.

Mode setting registers and bonding pads.

Also some on die termination (ODT) documents which are unfortunately spread over three groups G11C 7/1048, G11C 7/1051 and G11C 5/06, where they are now classified.

Together with G11C 7/1078, most of the synchronous interfaces documents.

Many early SDRAMs but became rapidly obsolete as most dynamic memories are now synchronous.

Together with G11C 7/1051, most of the synchronous interfaces documents.

Also many early solid state music players and early solid state memory cards (e.g. Compact Flash, SDcard).These should not be classified here but in G11B, G06F and G06K.

Circuitry used for decoding a memory address selecting a row line, a bank , a block or a range of memory cells in a semiconductor memory device.

If documents are clearly restricted to one specific cell type or memory technology they should not be classified here but in the group of said cell technology, unless there is no group for that cell technology. If documents mention applications to different types of cells then they can be classified here.

Circuitries that have an electrical effect on the rows or word lines. e.g. applying a voltage or a potential to the word line or row.

Decoders, circuitry which processes the address information to make a single or plural selection of word line or row line possible. However, these decoder circuits are usually not used for the electrical activation of the row or word line. This is the task of the word line control circuits.

In particular, global and local word line structure.

Only documents describing memories where each storage cell on its own has two or more ports.

G11C 11/56 takes precedence over sub-groups G11C 11/02 - G11C 11/54.

The sub-group classification G11C 11/34 is not to be assigned as there exist more specific places for different cell types.

Memories having two distinct arrays of memory elements, one with volatile memory elements and another one with non-volatile memory elements, the latter functioning as a backup memory for the volatile part of the memory.

Also the (now obsolete) magnetic-core memories.

Memories using a single magnetic layer.

Memories using domain wall displacement in a shift register like manner, see also G11C 19/0833.

Memories using multiple magnetic layers not using any spin effect.

Memories using magnetic spin effect, i.e. where the memory elements have magnetic tunnel junctions.

Auxiliary circuitry for MRAM elements.

MRAM specific details of selecting a memory element, e.g. select transistors, diodes or mere word line or bit line selection voltages.

Details of checking written data in MRAM elements.

Memories using ferroelectric elements. This covers memories with capacitive elements where the insulating dielectric material between the capacitor plates is a ferroelectric material.

Details of FRAM memory elements comprising a ferroelectric capacitor.

Details of FRAM memory elements comprising a transistor with ferroelectric material, e.g. a FEFET.

Auxiliary circuitry for FRAM elements.

FRAM specific details of selecting a memory element, e.g. select transistors, diodes or mere word line or bit line selection voltages.

Details of checking written data in MRAM elements.

Documents should not be classified in this group unless there is no more specific place available below or in G11C 14/00 - G11C 21/00 (see precedence rule at beginning of this main group). e.g., for:

DRAM (Dynamic RAM), see G11C 11/401 - G11C 11/4099

FRAM, FeRAM (Ferro-electric RAM) see G11C 11/22

MRAM (Magnetic RAM) see G11C 11/14 - G11C 11/16

NVRAM (Nonvolatile RAM) see G11C 5/141 (battery backed RAM) or G11C 16/00 (EAROM/EEPROM/Flash memory)

PCRAM, PRAM (Phase-change RAM) see G11C 13/0004

RRAM, ReRAM (Resistive RAM) see G11C 13/0002 - G11C 13/0097

SRAM (Static RAM) see G11C 11/41 - G11C 11/419

ROM (Read-only Memory) see G11C 17/02 - G11C 17/126

PROM (Programmable ROM) see G11C 17/14 - G11C 17/18

EPROM (Erasable PROM) see G11C 16/00 - G11C 16/349

EEPROM, E2PROM (Electrically-erasable PROM) see G11C 16/00 - G11C 16/349

EAROM (Electrically-alterable ROM) see G11C 16/00 - G11C 16/349

Basically this group covers DRAMs - and some further types of cells needing to be periodically and frequently refreshed such gain cells.

This group and its sub groups concerns mainly DRAM cells of any type from classic one transistor-one capacitor cell types to more exotic types such single transistor cells or gain cells. All cells have in common that they require to be updated or rewritten or refreshed frequently in order to retain their data.

This is a technology or cell type specific group and only DRAMs and memories needing frequent refreshes should be classified here. FeRAM with a dynamic mode should be classified in G11C 11/22.

Mostly 1T1C cells but single transistor cells are also found here (see also G11C 2211/4016 for SOI and isolated well single transistor cells).

Cells with three charge-transfer gates, but it also contains gain cells and other cells with access transistors combined with another charge storage transistor. Finally, it covers also partially capacitor based cells with two access transistors and those with more than 3 access transistors (multiport DRAM cells see also G11C 8/16).

All the power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits specific to DRAM - see also G11C 5/14-G11C 5/147 for memory power circuits in general; see also G11C 11/4076 and G11C 7/22 for some power management aspects (changing memory state or mode and DPD e.g. deep power down wake-ups ) and G11C 11/406 for the refresh aspects in low power mode (self-refresh).

The group contains also most of the documents concerning cells with a controlled back plate and back plate voltage circuits.

Precharging, equalising or isolating circuits for DRAMs are in G11C 11/4094 and in general also in G11C 7/12.

Memories having memory cells with positive feedback or a latch, i.e. a Static RAM or SRAM. This group only covers the aspects of the memory device itself. Manufacturing is covered by H10B 99/00 and array structures by H10B 10/00.

This group contains SRAM memory cells per se.

Circuitry providing for power, address decoding, signal control etc. required for the functioning of the SRAM. This group and its dependents cover SRAMs having bipolar as well as FET transistor memory cells.

Memories using superconductive elements like squids

This sub-group contains no documents; see G11C 17/00 and subgroups.

As used in neural networks.

Additional aspects relating to the cell type rather than multi-state storage per se should be classified under the relevant cell technology. For counting arrangements comprising multi-stable elements of this type see H03K 25/00, H03K 29/00.

Digital stores or memories:

H01L: Semiconductor fabrication means and methods.

G03H: Holographic processes and apparatus.

RRAM storage elements; for MRAM storage elements see G11C 11/15 and G11C 11/16.

RRAM elements in which the electrical resistance change is based on an amorphous to crystalline or crystalline to amorphous transition in a phase change material.

RRAM elements in which the electrical resistance change is based on a switching mechanism in metal oxides e.g. TiO, NiO, HfO2, CuO.

RRAM elements in which the electrical resistance change is based on the formation and breaking of chemical bonds.

RRAM elements in which the electrical resistance change is based on ion movement in a solid electrolyte between metal electrodes.

Auxiliary circuitry for RRAM elements.

Storage elements in which the electrical resistance change is based on the formation and breaking of chemical bonds (for RRAM G11C 13/0009 takes precedence).

Memories with arrangements to save information from a volatile to a nonvolatile memory when power supply is lost and to restore the information from the nonvolatile to the volatile memory when power is restored.

Sub-groups cover details of cells adapted for this purpose, classified first by volatile and then by nonvolatile storage type.

For memories where volatile and non-volatile elements co-exist but are operated independently, see G11C 11/005. For volatile memories which are designed to power up in a known state (latent image memory), see G11C 7/20.

Where a document only describes the presence of a nonvolatile memory to backup a volatile memory, without cell details, it should be placed in the main group. In principle, a search for such a document would need to encompass all the sub-groups as well as the main group. More detail about the type of storage elements can be added by using Indexing Codes relating to specific cell types.

In case the nonvolatile element is not covered below, classify here with an Indexing Code to specify its type.

Can further distinguish between FG (Indexing Code G11C 16/0408) and MNOS (Indexing Code: G11C 16/0466).

Can be further characterised using codes from Indexing Code G11C 11/14 to Indexing Code G11C 11/16.

Can be further characterised using codes from Indexing Code G11C 13/0002 to Indexing Code G11C 13/0019.

In case the nonvolatile element is not covered below, classify here with an Indexing Code to specify its type. For SRAM cells in general see G11C 11/41.

Can further distinguish between FG (Indexing Code G11C 16/0408) and MNOS (Indexing Code G11C 16/0466).

Can be further characterised using codes from Indexing Code G11C 11/14 to Indexing Code G11C 11/16.

Can be further characterised using codes from Indexing Code G11C 13/0002 to Indexing Code G11C 13/0019.

Memories wherein a sought data word for a given field (characteristic part) is supplied as input to the memory, which is able to search its stored data contents to determine if the supplied data word is present among said data contents. If a match or 'hit' is established, the address(es) in the memory where the supplied data word was found is/are returned. Optionally the contents of all fields of the matching word are returned.

Memories of the type in which charge is stored in a non-volatile manner, either in a "floating gate" capacitor (see G11C 16/0408) or trapped in the gate insulator of a transistor (see G11C 16/0466).

In both cases, the effect of charge storage is to modify the threshold voltage of the transistor, e.g. from depletion to enhancement mode (stored state discriminated by conduction or not at zero gate voltage) or from 'normal' to 'deep' enhancement (stored state discriminated by conduction or not at small positive gate voltage).

Also cells in which the floating gate is composed of "nanocrystals".

May also comprise cells with additional control gates, e.g. an erase gate.

The also known as "split-gate" or "1½ transistor" cells.

The classical EEPROM cells.

Aso complementary-pair type cells, in which two floating gate transistors store opposite states. This type is often used to store redundancy information, see also G11C 29/789.

i.e. NAND type cells.

i.e. arrays in which the individual cell transistors are formed between parallel bitlines, one of which is selected by decoder circuitry to be ground and the other as a normal bitline.

This group is only used if no lower sub-group is suitable - assign multiple sub-groups rather than placing here.

Erase preprogramming, also called preconditioning.

Especially high-voltage switches (see e.g. EP862183, figures 1-3), ramp generators (see e.g. EP903750, figure 4).

e.g. ultraviolet erase.

What is also known as "overerase/overprogram correction" or "threshold convergence".

May lead to repeated erase, verify steps until correctly erased or retry limit reached (= failure).

Circuits that make no attempt at recovery; the device is therefore regarded as faulty.

Circuits that may lead to repeated program, verify steps until correctly programmed or retry limit reached (= failure).

Circuits that make no attempt at recovery; the device is therefore regarded as faulty.

Memories in which the stored data are permanently defined at the time of manufacturing (mask ROM) or which are adapted to be programmed with data one time only after manufacture (PROM).

i.e. NAND-type cells.

i.e. arrays in which the individual cell transistors are formed between parallel bitlines, one of which is selected by decoder circuitry to be ground and the other as a normal bitline.

So-called OTPROM (one-time programmable read only memories), i.e. EPROMs or flash memory arrays which are wholly or partly adapted to not be erasable (e.g. UV EPROM with no erasing window in the package, flash arrays not selectable to receive erasing voltages) are classified in G11C 16/00, with code G11C 2216/26.

e.g. fuses, antifuses.

Digital stores or memories in which information is cascaded between neighbouring data storage locations in a chain under the control of at least one common clock signal.

Digital stores or memories in which information bits circulate stepwise in a closed loop or ring arrangement.

Micromechanical and nanomechanical systems for data storage.

Digital stores or memories whose operation is based on fluid or liquid media.

Static stores or memories comprising:

H03K 17/00: Electronic switching or gating i.e. not by contact-making or -braking.

H03K 5/13: Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals.

The two main fields Test and Repair of semiconductor memories.

Concerning Test: This group covers test in particular

Repair of memories is found below at G11C 29/70

H01L: Semiconductor fabrication means and methods.

G06F 11/00: Error detection and correction, monitoring of normal operation.

G06F 12/00: Accessing, addressing or allocation within memory systems.

G01R 31/28: Test of electronic circuits.

Invention related features(concerning testing):

e.g. short circuit and cross talking on signal lines, intercell defects, stuck at fault (line permanently to GND or Vcc), refresh counter, fuses, charge pumps

G11C 29/021: in voltage or current generators

G11C 29/022: in I/O circuitry

G11C 29/023 : in clock generator or timing circuitry

G11C 29/024: in decoders

G11C 29/025: in signal lines

G11C 29/026: in sense amplifiers

G11C 29/027: in fuses

G11C 29/028: with adaption or trimming of parameters

e.g. only when stress (high temperature/voltage/clock frequency) is essential feature - EC documents only classified therein from 2007 onwards (IPC class for mostly Korean and Japanese documents relating to accelerated test)

e.g. when test is performed by writing/reading/comparing data, includes stress test (high temperature/voltage/clock frequency) when stress is not essential feature; test when something else is measured, i.e. not by write/read/compare in G11C 29/50

e.g. checkerboard pattern

e.g. all for which no particular sub-class exists like error catch memory, word/bit line control, identification means, self refresh logic, interconnection details

G11C 29/12005: comprising voltage or current generators

G11C 29/1201: comprising IO circuitry

G11C 29/12015: comprising clock generation or timing circuitry

e.g. test configuration, internal clock generation, provisions for high speed test with low speed tester

e.g. state machines, sequencers

e.g. address circuits, scrambling

e.g. linear address generation

e.g. test of redundant cells (replacement of defective cells in G11C 29/70 )

e.g. memories with multiple arrays serially accessed

e.g. bit line/word line spans over multiple arrays and is in normal mode accessed at once

e.g. test on single array / block

e.g. cells connected in series only for test (overlap with G01R 31/318536 scan chain for logic test)

e.g. bit line/word line testing, more than one bit a time tested in single array, word line and bit line driver, controller, decoder therefor

e.g. data storage in DUT, inverters, row copy circuits

e.g. built-in comparators, means to read out test data from memory

e.g. by use of LFSR (Linear Feedback Shift Register), EXOR logic circuit

e.g. test performed with use of ECC (overlap with G06F 11/10)

e.g. for repair, keep track on found errors, failure capture (overlap with G06F 11/20)

e.g. initiation of test mode, how to avoid entering test mode

e.g. inside or outside memory, overlap with 12 and 56, test interfaces, test connectors, probes, I/O lines, reducing number of used pads/terminals to tester, external monitoring of test results, access paths, interface to scan chains, JTAG, DMA, external provided clock for test

e.g. marginal test including current, race, refresh, temperature, timing/delay, signal margin, imprint and fatigue, floating gate transistor test by dielectric layer test, e.g. gate oxide stress test; EEPROM erase/program verify when focus on threshold voltage or current measurement, i.e. at multilevel EEPROM; charge gain/leakage, DRAM data retention time test, trimming circuits

G11C 29/50004: of threshold voltage

G11C 29/50008: of impedance

G11C 29/50012: of timing

G11C 29/50016: of retention

e.g. data retention in DRAM or EEPROM cells

e.g. soft errors (i.e. radiation) or when memory content can not be read from outside (content protected), transparent test (modifies contents and restores back to original) EEPROM erase/program verify when 0/1 read (during normal operation G11C 16/34) when EEPROM cell is not defective but overerased / overprogrammed

e.g. design of test techniques, simulation, test coverage, error latency (probability)

e.g. external test machines, external pattern and address generation/scrambling, here only when specific for memories, overlap with G01R 31/319

G11C 29/56004: pattern generation

G11C 29/56008: error analysis

G11C 29/56012: timing aspects, clock generation, synchronisation

G11C 29/56: tester apparatus features

Additional (not directly invention) related features:

e.g. when test result is feedback into manufacturing process

e.g. document discloses all essential elements off test loop from data generation via DUT to data comparison

e.g. test is performed when memory operates in user application, either in idle state or by monitoring, leading to repair in case of failure

Document relates to error correction (only) in normal operation:

e.g. translation of logical address to physical address

e.g. parallel / simultaneous test of multiple word lines / blocks / arrays / devices / modules

e.g. comparison of test results of identical chips or with golden chip; or looping test result through a plurality of chips / modules

e.g. repair information, chip identification, quality data

e.g. physical values not covered elsewhere

e.g. for timing, voltage, multiplexing of test channels

e.g. as failure bit map

e.g. raw data collection and management

Repairing defective memory devices by using redundant (spare) elements; repairing defective memory devices by reconfiguring the address space (this implies a reduced memory capacity compared with a non-defective device); algorithms for effecting such repairs.

Illustrative example of subject matter classified in this group: EP1141834, figure 1.

Replacement algorithms (failure map to redundancy implementation ).

Both with and without dedicated spares - typically address translations via pointers.

Techniques used for redundancy in this kind of applications are always very similar and almost all of them involve sector mapping, counting of read/erase operations, wear-out detection, etc. Many of these documents include lower level features related to flash memories (flash).

See also G11C 16/349 for wear-out detection; G11C 29/88 for 'hard wired' reconfiguration.

Could include disconnecting faulty elements.

In DRAMS, how to refresh the redundant lines which are substituting faulty lines.

Fuse related issues; most of these documents have descriptions at transistor level, explaining how the fuse circuits are built or how they are included in the redundancy decoding elements.

In this case, a master fuse can be used to decide whether a redundant line or decoder is in use. This allows to save time when programming the fuses. See EP646866, fig.3 (reference 50).

In these documents, the "fuse" is not a fuse as such, but rather a non-volatile memory cell or a combination of a fuse with a latch to retain its status (i.e. the fuse is only read at power up to reduce stress thereon). See US5619469, fig2.

Under this group, techniques which tend to reduce real estate by several means. When the document is a pure layout description - i.e. without a clear functionality other than a "new layout" - it is included in this 'head group'. It should be clear that there is a clear "layout" approach in the description and figures.

Transmission of faulty/redundant addresses between the fuse boxes and the final decoders is done by encoding: For 2n redundant lines only n lines have to be routed. See EP496282, fig.2.

Faults which involve several (adjacent) lines can be solved in a simplified way, 'simplified' implying using a reduced amount of coding or storage for the defect. These kind of faults are very frequent due to impurities of a big size. See US5281868, fig. 3,4.

Solutions that might have a lower redundancy efficiency (e.g. lines can only be replaced in sets of four, regardless of the fault) but allows to have fewer and/or smaller comparators. See EP239196, fig 3.

All kinds of solutions in which different combinations of faulty/redundant replacement are possible to allow for a higher level of repair with a lower number of spares. For instance, when redundant lines in a block can be used to substitute faulty lines in any other block, or when the same redundant line can be used for row or column repair, etc. See US5469388 fig 4A.

Faults are solved in a hierarchical way. For instance: lines are replaced with redundant lines in a given block or, if not possible, then the complete block is repaired with a redundant block as a whole unit, etc. See US5295101, fig. 7.

The amount of real estate occupied by fuses is lower.

The layout is done in such a way that a certain cost function associated with the yield is optimized. A lot of NPL and thesis-like stuff. See XP237814.

Certain applications (ROMs, synchronous memories, cache memories) demand redundancy solutions which are very related to the nature of the application itself and therefore more likely to be relevant in an application-oriented context.

For the case of Dual port RAMs, video memories and the like.

These redundancy solutions are usually taking into account the block erase operations as well as the aging of EEPROM cells due to program/erase. Many of these documents are also classified with the solid state disks solutions (G11C 29/765). Normally documents put in this group work at a lower level (i.e. row/columns in a block, rather than sector mapping level.

Redundancy solutions for Mask ROMs which have specific layouts.

Same as above for the case of synchronous memories. Timing (synchronicity) requirements as well as the specific (i.e. sequential) nature of read/write operations are linked to some redundancy requirements.

Most of the solutions for this problem are related to the avoidance of DC faults.

A common way to reduce power consumption in these cases.

Roll call circuits to identify redundancy substitutions.

Solving the problem of a faulty spare element which must be disabled for redundant substitution.

In this group, solutions which propose to eliminate or reduce the difference in speed between a non-faulty and a faulty line selection. Many of these documents are actually addressing stability problems (e.g. obtain a reliable voltage level before sampling fuse values) employing similar solutions such as ATDs.

The trick here usually is to insert a delay element in the faster path to make sure both paths (normal and redundant) are equally slow. This delay element usually consists of slower transistors in the path or a chain of inverters. See US5777931, fig.5.

A normal/redundant selection signal is already obtained at a predecoding stage which allows to start some kind of preselection. See US5550776, fig.4.

Usually the case with column redundancy: Addresses are input simultaneously to faulty and normal column decoders and only at the output (usually by means of a multiplexer) it is decided whether a redundant replacement is pertinent. See US4473895, fig.1.

Columns are shifted one or more position skipping the faulty one(s). There are redundant columns at the end of the chain. See EP434200, fig. 4.

Partially good memories, degraded memories.

See US2006190762 (figure 1 - shown), US2009067276.

See US2008307251 (fig.1), US2009072886 (fig.1 - shown).

See US2006221729, figure 2.

See US2008180983 (figure 2), US2006221729 (figure 3).