Memory devices consisting of multiple semiconductor or solid-state components. This includes the multiple memory cells constituting the memory core region and logic components within the immediate peripheral region surrounding the memory core region. The memory cells have storage components therein, which may be accessed by selection components.

This includes the following kind of devices:

Volatile Memory Devices:

Non-Volatile Memory Devices:

Assemblies of multiple devices comprising at least one memory device of this subclass.

Processes and apparatus specially adapted for the manufacture or treatment of such devices.

When the focus of the invention is on the structure of the device, classification is made in H10B. When the focus of the invention is on the structures used for accessing the device, such as structures or circuits for reading, writing, or erasing data in the device, classification is made in G11C.

Memory devices having multiple volatile memory cells, wherein, in each cell, the logic state is stored in one of two stable states of a cross-coupled inverter. SRAM cells commonly have four or more transistors.

Dynamic memory devices having multiple volatile memory cells, wherein, each cell has:

Memory devices wherein data is stored even when power is removed (non-volatile), wherein the cells have components (e.g. fuses or anti-fuses) that are irreversibly changed during programming.

The group H10B 20/00 itself covers memory devices wherein, after manufacturing, the operations are limited to read-only (e.g. mask ROM), because the programming thereof was performed during manufacturing. The groups H10B 20/20 - H10B 20/25 cover programmable ROM [PROM] wherein the memory may be programmed after manufacturing by a user.

ROM and PROM devices are typically programmable only once (though in some situations, a cell may have more than one element that may be irreversibly changed, so a very limited amount of "corrective" programming may occur). This is contrasted with EPROM and EEPROM devices, which can be writable or erasable many (e.g. millions of) times.

Non-volatile ROM devices comprising multiple memory cells that can be programmed after their manufacture ("programmable ROM" or "PROM"), wherein the memory cell comprises field-effect components as either the access component or the storage component.

The group H10B 20/20 itself covers PROM wherein individual memory cells may each be programmed more than once, e.g. a "corrective programming" may occur because the cells have more than one element that may be irreversibly-changeable element. The groups indented under H10B 20/20 cover PROM wherein each cell may only be programmed once.

Illustrative example for this group: a cell is constructed from an anti-fuse programming transistor M0, an electronic fuse EF, and a control transistor MN1, such that the normal programming of M0 by breaking down its gate-source insulation layer (which decreases its initial large resistance) can be followed by "correction programming" by fusing the effuse (increasing the resistance).

Non-volatile programmable ROM (PROM) devices comprising multiple memory cells wherein, after their manufacture, each cell can only be programmed once (e.g. by permanently connecting or disconnecting a fuse or an anti-fuse).

Non-volatile memory devices having multiple memory cells, wherein in each cell, the logic state is stored as charge on a floating gate of a transistor. The memory cell can be electrically erased and reprogrammed.

Non-volatile memory devices having multiple memory cells, wherein in each cell, the logic state is stored as charge on a charge-trapping gate dielectric. The memory cell can be electrically erased and reprogrammed.

Non-volatile memory devices having multiple memory cells, wherein in each cell, the logic state is stored as a polarisation state of a ferroelectric material within a transistor, e.g. in a ferroelectric gate dielectric. The memory cell can be electrically erased and reprogrammed.

Non-volatile memory devices having multiple memory cells, wherein in each cell, the logic state is stored as a polarisation state of a ferroelectric material within a capacitor, e.g. in a ferroelectric capacitor dielectric. The cell is accessed by a selection component and can be electrically erased and reprogrammed.

Non-volatile memory devices having multiple memory cells, wherein in each cell, the logic state is stored in magnetic domains of magnetic layers in a storage component. The memory cell can be electrically erased and reprogrammed. Examples include MTJ-based memory and STT-MRAM.

Aspects of the individual galvanomagnetic devices (e.g. structure, materials or manufacturing) are covered by group H10N 50/00.

Non-volatile memory devices having multiple memory cells, wherein in each cell, the logic state is stored as a high or low resistance state. The memory cell can be electrically erased and reprogrammed. Examples include:

Aspects of the individual resistance switching devices (e.g. structure, materials or manufacturing) are covered by group H10N 70/00.

Non-volatile memory devices having multiple memory cells, wherein in each cell, the logic state is erasable and reprogrammable, other than those covered by H10B 41/00- H10B 63/00. Examples include:

Class H10 contains many groups for assemblies. If an assembly has multiple element devices therein, multiple classification should be used to classify the assembly in each appropriate group.

For example, if an assembly of multiple devices has the elements of, e.g. a memory chip, an integrated processor chip and a superconducting integrated chip, multiple classification should be made in H10B 80/00 for the memory chip, in H01L 25/00 for the integrated processor chip and in H10N 69/00 for the superconducting chip.

Furthermore, classification of generic aspects of the assembly (e.g. the chips are stacked, or have interposers therebetween) should be made in H01L 25/00 and H01L 2225/00.