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Indent Level
Color Curly Brackets (indicating CPC extensions to IPC)

CPC
COOPERATIVE PATENT CLASSIFICATION
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AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (of dynamo-electric generators H02P)
NOTE
-
This subclass covers:

- automatic control circuits for generators of electronic
oscillations or pulses;
- starting, synchronisation, or stabilisation circuits for
generators where the type of generator is irrelevant or
unspecified.

This subclass does not cover stabilisation or starting circuits specially adapted to only one specific type of generator, which are covered by subclasses H03B, H03K.

In this subclass, the following expression is used with the meaning indicated:

- "automatic control" covers only closed loop systems.

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Stabilisation of generator output against variations of physical values, e.g. power supply (automatic control H03L 5/00, H03L 7/00)
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H03L 1/02
.
against variations of temperature only
. .
{
of generators comprising distributed capacitance and inductance
}
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H03L 1/022
. .
{
by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature (H03L 1/021 takes precedence)
}
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. . .
{
by using voltage variable capacitance diodes
}
H03L 1/025
. . . .
{
and a memory for digitally storing correction values
}
H03L 1/026
. . .
{
by using a memory for digitally storing correction values (H03L 1/025 takes precedence)
}
H03L 1/027
. . .
{
by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/substract logic circuit (H03L 1/023, H03L 1/026 take precedence)
}
H03L 1/028
. .
{
of generators comprising piezo-electric resonators (H03L 1/021 and H03L 1/022 take precedence; oscillation generators with a piezo-electric resonator per se H03B 5/32)
}
. .
Constructional details for maintaining temperature constant
H03L 3/00
Starting of generators
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Automatic control of voltage, current, or power
.
of power
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Automatic control of frequency or phase; Synchronisation (tuning of resonant circuits in general H03J; synchronising in digital communication systems, see the relevant groups in class H04)
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.
using a frequency discriminator comprising a passive frequency-determining element
. .
wherein the frequency-determining element comprises distributed inductance and capacitance
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.
using a reference signal applied to a frequency- or phase-locked loop
. .
using several loops, e.g. for redundant clock signal generation (for indirect frequency synthesis H03L 7/22)
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H03L 7/08
. .
Details of the phase-locked loop
. . .
{
the loop being adapted for reducing power consumption (H03L 7/14 takes precedence)
}
H03L 7/0805
. . .
{
the loop being adapted to provide an additional control signal for use outside the loop
}
. . .
{
concerning mainly a recovery circuit for the reference signal
}
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. . .
provided with an additional controlled phase shifter
{
(H03L 7/0998 takes precedence)
}
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. . . .
{
and where no voltage or current controlled oscillator is used
}
. . . . .
{
the phase shifting device being digitally controlled
}
H03L 7/0816
. . . . .
{
the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
}
H03L 7/0818
. . . . .
{
the controlled phase shifter comprising coarse and fine delay or phase-shifting means
}
. . .
the reference signal being additionally directly applied to the generator (direct frequency synchronisation without loop H03L 7/24)
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. . .
concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L 7/10 takes precedence; frequency or phase detection comparison in general H03D 3/00, H03D 13/00)
H03L 7/087
. . . .
using at least two phase detectors or a frequency and phase detector in the loop
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. . . .
the phase or frequency detector generating up-down pulses (H03L 7/087 takes precedence)
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H03L 7/0891
. . . . .
{
the up-down pulses controlling source and sink current generators, e.g. a charge pump
}
. . . . . .
{
the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
}
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H03L 7/0895
. . . . . .
{
Details of the current generators (H03L 7/0893 takes precedence)
}
H03L 7/0896
. . . . . . .
{
the current generators being controlled by differential up-down pulses
}
. . . . . . .
{
the source or sink current values being variable (H03L 7/0896 takes precedence)
}
. . . .
the phase or frequency detector using a sampling device (H03L 7/087 takes precedence)
. . . .
using special filtering or amplification characteristics in the loop (H03L 7/087 to H03L 7/091 take precedence)
. . . .
using a lock detector (H03L 7/087 takes precedence)
. . . .
using a comparator for comparing the voltages obtained from two frequency to voltage converters
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H03L 7/099
. . .
concerning mainly the controlled oscillator of the loop
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. . . .
{
the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L 7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L 7/0814)
}
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. . . . .
{
comprising a counter or a frequency divider
}
H03L 7/0993
. . . . . .
{
and a circuit for adding and deleting pulses
}
. . . . .
{
comprising an accumulator
}
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H03L 7/0995
. . . .
{
the oscillator comprising a ring oscillator
}
H03L 7/0996
. . . . .
{
Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
}
H03L 7/0997
. . . . .
{
Controlling the number of delay elements connected in series in the ring oscillator
}
H03L 7/0998
. . . . .
{
using phase interpolation
}
WARNING
-
Not complete, see also H03L 7/0995

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. . .
for assuring initial synchronisation or for broadening the capture range
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H03L 7/101
. . . .
{
using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop (H03L 7/113, H03L 7/187 take precedence)
}
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H03L 7/102
. . . . .
{
the additional signal being directly applied to the controlled loop oscillator
}
H03L 7/103
. . . . . .
{
the additional signal being a digital signal
}
H03L 7/104
. . . .
{
using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L 7/107, H03L 7/12 take precedence)
}
H03L 7/105
. . . .
{
Resetting the controlled oscillator when its frequency is outside a predetermined limit
}
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. . . .
using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
H03L 7/1072
. . . . .
{
by changing characteristics of the charge pump, e.g. changing the gain
}
H03L 7/1075
. . . . .
{
by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L 7/1072 takes precedence)
}
H03L 7/1077
. . . . .
{
by changing characteristics of the phase or frequency detection means (H03L 7/1072 takes precedence)
}
H03L 7/113
. . . .
using frequency discriminator
H03L 7/12
. . . .
using a scanning signal (tuning circuits with automatic scanning over a band of frequencies H03J 7/18)
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. . .
for assuring constant frequency when supply or correction voltages fail
{
or are interrupted
}
H03L 7/141
. . . .
{
the phase-locked loop controlling several oscillators in turn
}
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H03L 7/143
. . . .
{
by switching the reference signal of the phase-locked loop
}
H03L 7/145
. . . . .
{
the switched reference signal being derived from the controlled oscillator output signal
}
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H03L 7/146
. . . .
{
by using digital means for generating the oscillator control signal (H03L 7/141, H03L 7/143 take precedence)
}
H03L 7/148
. . . . .
{
said digital means comprising a counter or a divider
}
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H03L 7/16
. .
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
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H03L 7/18
. . .
using a frequency divider or counter in the loop (H03L 7/20, H03L 7/22 take precedence)
H03L 7/1803
. . . .
{
the counter or frequency divider being connected to a cycle or pulse swallowing circuit
}
H03L 7/1806
. . . .
{
the frequency divider comprising a phase accumulator generating the frequency divided signal
}
H03L 7/181
. . . .
a numerical count result being used for locking the loop, the counter counting during fixed time intervals
{
(H03L 7/1806 takes precedence)
}
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H03L 7/183
. . . .
a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
{
(H03L 7/1806 takes precedence)
}
. . . . .
using a mixer in the loop (H03L 7/187 to H03L 7/195 take precedence)
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. . . . .
using means for coarse tuning the voltage controlled oscillator of the loop (H03L 7/191 to H03L 7/195 take precedence)
H03L 7/189
. . . . . .
comprising a D/A converter for generating a coarse tuning voltage
. . . . .
using at least two different signals from the frequency divider or the counter for determining the time difference (H03L 7/193, H03L 7/195 take precedence)
. . . . .
the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider (pulse counters/frequency dividers H03K 21/00 to H03K 29/00)
H03L 7/195
. . . . .
in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency (H03L 7/193 takes precedence; pulse counters for predetermined counting H03K 21/00 to H03K 29/00)
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H03L 7/197
. . . .
a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
{
(H03L 7/1806 takes precedence)
}
H03L 7/1972
. . . . .
{
for reducing the locking time interval (H03L 7/1974, H03L 7/199 take precedence)
}
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H03L 7/1974
. . . . .
{
for fractional frequency division
}
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. . . . . .
{
using a phase accumulator for controlling the counter or frequency divider
}
H03L 7/1978
. . . . . . .
{
using a cycle or pulse removing circuit
}
H03L 7/199
. . . . .
with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
H03L 7/20
. . .
using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it (H03L 7/22 takes precedence)
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. . .
using more than one loop
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H03L 7/23
. . . .
with pulse counters or frequency dividers
H03L 7/235
. . . . .
{
Nested phase locked loops
}
.
using a reference signal directly applied to the generator
.
using energy levels of molecules, atoms, or subatomic particles as a frequency reference
H03L 9/00
Automatic control not provided for in other groups of this subclass
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H03L 2207/00
Indexing scheme relating to automatic control of frequency or phase and to synchronisation
H03L 2207/04
.
Modifications for maintaining constant the phase-locked loop damping factor when other loop parameters change
H03L 2207/05
.
Compensating for non-linear characteristics of the controlled oscillator
H03L 2207/06
.
Phase locked loops with a controlled oscillator having at least two frequency control terminals
H03L 2207/08
.
Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
H03L 2207/10
.
Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
H03L 2207/12
.
Indirect frequency synthesis using a mixer in the phase-locked loop
H03L 2207/14
.
Preventing false-lock or pseudo-lock of the PLL
H03L 2207/18
.
Temporarily disabling, deactivating or stopping the frequency counter or divider
H03L 2207/50
.
All digital phase-locked loop
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Last Modified: 10/10/2013