Manual of U.S. Patent Classification
as of June 30, 2000

Class
438
SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS

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Subclass		Title
ClassTitle		===> SEMICONDUCTOR DEVICE MANUFACTURING: PROCESS
1		HAVING BIOMATERIAL COMPONENT OR INTEGRATED WITH LIVING ORGANISM
2		HAVING SUPERCONDUCTIVE COMPONENT
3		HAVING MAGNETIC OR FERROELECTRIC COMPONENT
4		REPAIR OR RESTORATION
5		INCLUDING CONTROL RESPONSIVE TO SENSED CONDITION
6		. Interconnecting plural devices on semiconductor substrate
7		. Optical characteristic sensed
8		. . Chemical etching
9		. . . Plasma etching
10		. Electrical characteristic sensed
11		. . Utilizing integral test element
12		. . And removal of defect
13		. . Altering electrical property by material removal
14		WITH MEASURING OR TESTING
15		. Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
16		. Optical characteristic sensed
17		. Electrical characteristic sensed
18		. . Utilizing integral test element
19		HAVING INTEGRAL POWER SOURCE (E.G., BATTERY, ETC.)
20		ELECTRON EMITTER MANUFACTURE
21		MANUFACTURE OF ELECTRICAL DEVICE CONTROLLED PRINTHEAD
22		MAKING DEVICE OR CIRCUIT EMISSIVE OF NONELECTRICAL SIGNAL
23		. Having diverse electrical device
24		. . Including device responsive to nonelectrical signal
25		. . . Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
26		. Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
27		. . Having additional optical element (e.g., optical fiber, etc.)
28		. . Plural emissive devices
29		. Including integrally formed optical element (e.g., reflective layer, luminescent material, contoured surface, etc.)
30		. . Liquid crystal component
31		. . Optical waveguide structure
32		. . Optical grating structure
33		. Substrate dicing
34		. Making emissive array
35		. . Multiple wavelength emissive
36		. Ordered or disordered
37		. Graded composition
38		. Passivating of surface
39		. Mesa formation
40		. . Tapered etching
41		. . With epitaxial deposition of semiconductor adjacent mesa
42		. Groove formation
43		. . Tapered etching
44		. . With epitaxial deposition of semiconductor in groove
45		. Dopant introduction into semiconductor region
46		. Compound semiconductor
47		. . Heterojunction
48		MAKING DEVICE OR CIRCUIT RESPONSIVE TO NONELECTRICAL SIGNAL
49		. Chemically responsive
50		. Physical stress responsive
51		. . Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
52		. . Having cantilever element
53		. . Having diaphragm element
54		. Thermally responsive
55		. . Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
56		. Responsive to corpuscular radiation (e.g., nuclear particle detector, etc.)
57		. Responsive to electromagnetic radiation
58		. . Gettering of substrate
59		. . Having diverse electrical device
60		. . . Charge transfer device (e.g., CCD, etc.)
61		. . Continuous processing
62		. . . Using running length substrate
63		. . Particulate semiconductor component
64		. . Packaging (e.g., with mounting, encapsulating, etc.) or treatment of packaged semiconductor
65		. . . Having additional optical element (e.g., optical fiber, etc.)
66		. . . Plural responsive devices (e.g., array, etc.)
67		. . . . Assembly of plural semiconductor substrates
68		. . Substrate dicing
69		. . Including integrally formed optical element (e.g., reflective layer, luminescent layer, etc.)
70		. . . Color filter
71		. . . Specific surface topography (e.g., textured surface, etc.)
72		. . . Having reflective or antireflective component
73		. . Making electromagnetic responsive array
74		. . . Vertically arranged (e.g., tandem, stacked, etc.)
75		. . . Charge transfer device (e.g., CCD, etc.)
76		. . . . Majority signal carrier (e.g., buried or bulk channel, peristaltic, etc.)
77		. . . . Compound semiconductor
78		. . . . Having structure to improve output signal (e.g., exposure control structure, etc.)
79		. . . . . Having blooming suppression structure (e.g., antiblooming drain, etc.)
80		. . . Lateral series connected array
81		. . . . Specified shape junction barrier (e.g., V-grooved junction, etc.)
82		. . Having organic semiconductor component
83		. . Forming point contact
84		. . Having selenium or tellurium elemental semiconductor component
85		. . Having metal oxide or copper sulfide compound semiconductive component
86		. . . And cadmium sulfide compound semiconductive component
87		. . Graded composition
88		. . Direct application of electric current
89		. . Fusion or solidification of semiconductor region
90		. . Including storage of electrical charge in substrate
91		. . Avalanche diode
92		. . Schottky barrier junction
93		. . Compound semiconductor
94		. . . Heterojunction
95		. . . Chalcogen (i.e., oxygen (O), sulfur (S), selenium (Se), tellurium (Te)) containing
96		. . Amorphous semiconductor
97		. . Polycrystalline semiconductor
98		. . Contact formation (i.e., metallization)
99		HAVING ORGANIC SEMICONDUCTIVE COMPONENT
100		MAKING POINT CONTACT DEVICE
101		. Direct application of electrical current
102		HAVING SELENIUM OR TELLURIUM ELEMENTAL SEMICONDUCTOR COMPONENT
103		. Direct application of electrical current
104		HAVING METAL OXIDE OR COPPER SULFIDE COMPOUND SEMICONDUCTOR COMPONENT
105		HAVING DIAMOND SEMICONDUCTOR COMPONENT
106		PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR
107		. Assembly of plural semiconductive substrates each possessing electrical device
108		. . Flip-chip-type assembly
109		. . Stacked array (e.g., rectifier, etc.)
110		. Making plural separate devices
111		. . Using strip lead frame
112		. . . And encapsulating
113		. . Substrate dicing
114		. . . Utilizing a coating to perfect the dicing
115		. Including contaminant removal or mitigation
116		. Having light transmissive window
117		. Incorporating resilient component (e.g., spring, etc.)
118		. Including adhesive bonding step
119		. . Electrically conductive adhesive
120		. With vibration step
121		. Metallic housing or support
122		. . Possessing thermal dissipation structure (i.e., heat sink)
123		. . Lead frame
124		. . And encapsulating
125		. Insulative housing or support
126		. . And encapsulating
127		. Encapsulating
128		MAKING DEVICE ARRAY AND SELECTIVELY INTERCONNECTING
129		. With electrical circuit layout
130		. Rendering selected devices operable or inoperable
131		. Using structure alterable to conductive state (i.e., antifuse)
132		. Using structure alterable to nonconductive state (i.e., fuse)
133		MAKING REGENERATIVE-TYPE SWITCHING DEVICE (E.G., SCR, IGBT, THYRISTOR, ETC.)
134		. Bidirectional rectifier with control electrode (e.g., triac, diac, etc.)
135		. Having field effect structure
136		. . Junction gate
137		. . . Vertical channel
138		. . Vertical channel
139		. Altering electrical characteristic
140		. Having structure increasing breakdown voltage (e.g., guard ring, field plate, etc.)
141		MAKING CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR, ETC.)
142		MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS
143		. Gettering of semiconductor substrate
144		. Charge transfer device (e.g., CCD, etc.)
145		. . Having additional electrical device
146		. . Majority signal carrier (e.g., buried or bulk channel, peristaltic, etc.)
147		. . Changing width or direction of channel (e.g., meandering channel, etc.)
148		. . Substantially incomplete signal charge transfer (e.g., bucket brigade, etc.)
149		. On insulating substrate or layer (e.g., TFT, etc.)
150		. . Specified crystallographic orientation
151		. . Having insulated gate
152		. . . Combined with electrical device not on insulating substrate or layer
153		. . . . Complementary field effect transistors
154		. . . Complementary field effect transistors
155		. . . And additional electrical device on insulating substrate or layer
156		. . . Vertical channel
157		. . . Plural gate electrodes (e.g., dual gate, etc.)
158		. . . Inverted transistor structure
159		. . . . Source-to-gate or drain-to-gate overlap
160		. . . . Utilizing backside irradiation
161		. . . Including source or drain electrode formation prior to semiconductor layer formation (i.e., staggered electrodes)
162		. . . Introduction of nondopant into semiconductor layer
163		. . . Adjusting channel dimension (e.g., providing lightly doped source or drain region, etc.)
164		. . . Semiconductor islands formed upon insulating substrate or layer (e.g., mesa formation, etc.)
165		. . . . Including differential oxidation
166		. . . Including recrystallization step
167		. Having Schottky gate (e.g., MESFET, HEMT, etc.)
168		. . Specified crystallographic orientation
169		. . Complementary Schottky gate field effect transistors
170		. . And bipolar device
171		. . And passive electrical device (e.g., resistor, capacitor, etc.)
172		. . Having heterojunction (e.g., HEMT, MODFET, etc.)
173		. . Vertical channel
174		. . Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.)
175		. . Buried channel
176		. . Plural gate electrodes (e.g., dual gate, etc.)
177		. . Closed or loop gate
178		. . Elemental semiconductor
179		. . Asymmetric
180		. . Self-aligned
181		. . . Doping of semiconductive region
182		. . . . T-gate
183		. . . . Dummy gate
184		. . . . Utilizing gate sidewall structure
185		. . . . . Multiple doping steps
186		. Having junction gate (e.g., JFET, SIT, etc.)
187		. . Specified crystallographic orientation
188		. . Complementary junction gate field effect transistors
189		. . And bipolar transistor
190		. . And passive device (e.g., resistor, capacitor, etc.)
191		. . Having heterojunction
192		. . Vertical channel
193		. . . Multiple parallel current paths (e.g., grid gate, etc.)
194		. . Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.)
195		. . Plural gate electrodes
196		. . Including isolation structure
197		. Having insulated gate (e.g., IGFET, MISFET, MOSFET, etc.)
198		. . Specified crystallographic orientation
199		. . Complementary insulated gate field effect transistors (i.e., CMOS)
200		. . . And additional electrical device
201		. . . . Including insulated gate field effect transistor having gate surrounded by dielectric (i.e., floating gate)
202		. . . . Including bipolar transistor (i.e., BiCMOS)
203		. . . . . Complementary bipolar transistors
204		. . . . . Lateral bipolar transistor
205		. . . . . Plural bipolar transistors of differing electrical characteristics
206		. . . . . Vertical channel insulated gate field effect transistor
207		. . . . . Including isolation structure
208		. . . . . . Isolation by PN junction only
209		. . . . Including additional vertical channel insulated gate field effect transistor
210		. . . . Including passive device (e.g., resistor, capacitor, etc.)
211		. . . Having gate surrounded by dielectric (i.e., floating gate)
212		. . . Vertical channel
213		. . . Common active region
214		. . . Having underpass or crossunder
215		. . . Having fuse or integral short
216		. . . Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound
217		. . . Doping of semiconductor channel region beneath gate insulator (e.g., threshold voltage adjustment, etc.)
218		. . . Including isolation structure
219		. . . . Total dielectric isolation
220		. . . . Isolation by PN junction only
221		. . . . Dielectric isolation formed by grooving and refilling with dielectric material
222		. . . . . With epitaxial semiconductor layer formation
223		. . . . . Having well structure of opposite conductivity type
224		. . . . . . Plural wells
225		. . . . Recessed oxide formed by localized oxidation (i.e., LOCOS)
226		. . . . . With epitaxial semiconductor layer formation
227		. . . . . Having well structure of opposite conductivity type
228		. . . . . . Plural wells
229		. . . Self-aligned
230		. . . . Utilizing gate sidewall structure
231		. . . . . Plural doping steps
232		. . . . Plural doping steps
233		. . . And contact formation
234		. . Including bipolar transistor (i.e., BiMOS)
235		. . . Heterojunction bipolar transistor
236		. . . Lateral bipolar transistor
237		. . Including diode
238		. . Including passive device (e.g., resistor, capacitor, etc.)
239		. . . Capacitor
240		. . . . Having high dielectric constant insulator (e.g., Ta2O5, etc.)
241		. . . . And additional field effect transistor (e.g., sense or access transistor, etc.)
242		. . . . . Including transistor formed on trench sidewalls
243		. . . . Trench capacitor
244		. . . . . Utilizing stacked capacitor structure (e.g., stacked trench, buried stacked capacitor, etc.)
245		. . . . . With epitaxial layer formed over the trench
246		. . . . . Including doping of trench surfaces
247		. . . . . . Multiple doping steps
248		. . . . . . Including isolation means formed in trench
249		. . . . . . Doping by outdiffusion from a dopant source layer (e.g., doped oxide, etc.)
250		. . . . Planar capacitor
251		. . . . . Including doping of semiconductive region
252		. . . . . . Multiple doping steps
253		. . . . Stacked capacitor
254		. . . . . Including selectively removing material to undercut and expose storage node layer
255		. . . . . Including texturizing storage node layer
256		. . . . . Contacts formed by selective growth or deposition
257		. . Having additional gate electrode surrounded by dielectric (i.e., floating gate)
258		. . . Including additional field effect transistor (e.g., sense or access transistor, etc.)
259		. . . Including forming gate electrode in trench or recess in substrate
260		. . . Textured surface of gate insulator or gate electrode
261		. . . Multiple interelectrode dielectrics or nonsilicon compound gate insulator
262		. . . Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.)
263		. . . . Tunneling insulator
264		. . . Tunneling insulator
265		. . . Oxidizing sidewall of gate electrode
266		. . . Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)
267		. . . . Including forming gate electrode as conductive sidewall spacer to another electrode
268		. . Vertical channel
269		. . . Utilizing epitaxial semiconductor layer grown through an opening in an insulating layer
270		. . . Gate electrode in trench or recess in semiconductor substrate
271		. . . . V-gate
272		. . . . Totally embedded in semiconductive layers
273		. . . Having integral short of source and base regions
274		. . . . Short formed in recess in substrate
275		. . Making plural insulated gate field effect transistors of differing electrical characteristics
276		. . . Introducing a dopant into the channel region of selected transistors
277		. . . . Including forming overlapping gate electrodes
278		. . . . After formation of source or drain regions and gate electrode (e.g., late programming, encoding, etc.)
279		. . Making plural insulated gate field effect transistors having common active region
280		. . Having underpass or crossunder
281		. . Having fuse or integral short
282		. . Buried channel
283		. . Plural gate electrodes (e.g., dual gate, etc.)
284		. . Closed or loop gate
285		. . Utilizing compound semiconductor
286		. . Asymmetric
287		. . Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compound
288		. . Having step of storing electrical charge in gate dielectric
289		. . Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)
290		. . . After formation of source or drain regions and gate electrode
291		. . . Using channel conductivity dopant of opposite type as that of source and drain
292		. . Direct application of electrical current
293		. . Fusion or solidification of semiconductor region
294		. . Including isolation structure
295		. . . Total dielectric isolation
296		. . . Dielectric isolation formed by grooving and refilling with dielectric material
297		. . . Recessed oxide formed by localized oxidation (i.e., LOCOS)
298		. . . . Doping region beneath recessed oxide (e.g., to form chanstop, etc.)
299		. . Self-aligned
300		. . . Having elevated source or drain (e.g., epitaxially formed source or drain, etc.)
301		. . . Source or drain doping
302		. . . . Oblique implantation
303		. . . . Utilizing gate sidewall structure
304		. . . . . Conductive sidewall component
305		. . . . . Plural doping steps
306		. . . . Plural doping steps
307		. . . . . Using same conductivity-type dopant
308		. . Radiation or energy treatment modifying properties of semiconductor regions of substrate (e.g., thermal, corpuscular, electromagnetic, etc.)
309		FORMING BIPOLAR TRANSISTOR BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS
310		. Gettering of semiconductor substrate
311		. On insulating substrate or layer (i.e., SOI type)
312		. Having heterojunction
313		. . Complementary bipolar transistors
314		. . And additional electrical device
315		. . Forming inverted transistor structure
316		. . Forming lateral transistor structure
317		. . Wide bandgap emitter
318		. . Including isolation structure
319		. . . Air isolation (e.g., mesa, etc.)
320		. . Self-aligned
321		. . . Utilizing dummy emitter
322		. Complementary bipolar transistors
323		. . Having common active region (i.e., integrated injection logic (I2L), etc.)
324		. . . Including additional electrical device
325		. . . Having lateral bipolar transistor
326		. . Including additional electrical device
327		. . Having lateral bipolar transistor