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ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES)
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| 1 | ![[Patents]](../gifs/ps.gif) | BULK EFFECT DEVICE |
| 2 | ![[Patents]](../gifs/ps.gif) | . Bulk effect switching in amorphous material |
| 3 | ![[Patents]](../gifs/ps.gif) | . . With means to localize region of conduction (e.g., "pore" structure) |
| 4 | ![[Patents]](../gifs/ps.gif) | . . With specified electrode composition or configuration |
| 5 | ![[Patents]](../gifs/ps.gif) | . . In array |
| 6 | ![[Patents]](../gifs/ps.gif) | . Intervalley transfer (e.g., Gunn effect) |
| 7 | ![[Patents]](../gifs/ps.gif) | . . In monolithic integrated circuit |
| 8 | ![[Patents]](../gifs/ps.gif) | . . Three or more terminal device |
| 9 | ![[Patents]](../gifs/ps.gif) | THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE, QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE) |
| 10 | ![[Patents]](../gifs/ps.gif) | . Low workfunction layer for electron emission, e.g., photocathode electron emissive layer |
| 11 | ![[Patents]](../gifs/ps.gif) | . . Combined with a heterojunction involving a III-V compound |
| 12 | ![[Patents]](../gifs/ps.gif) | . Heterojunction |
| 13 | ![[Patents]](../gifs/ps.gif) | . . Incoherent light emitter |
| 14 | ![[Patents]](../gifs/ps.gif) | . . Quantum well |
| 15 | ![[Patents]](../gifs/ps.gif) | . . . Superlattice |
| 16 | ![[Patents]](../gifs/ps.gif) | . . . . Of amorphous semiconductor material |
| 17 | ![[Patents]](../gifs/ps.gif) | . . . . With particular barrier dimension |
| 18 | ![[Patents]](../gifs/ps.gif) | . . . . Strained layer superlattice |
| 19 | ![[Patents]](../gifs/ps.gif) | . . . . . Si Ge |
| 20 | ![[Patents]](../gifs/ps.gif) | . . . . Field effect device |
| 21 | ![[Patents]](../gifs/ps.gif) | . . . . Light responsive structure |
| 22 | ![[Patents]](../gifs/ps.gif) | . . . . With specified semiconductor materials |
| 23 | ![[Patents]](../gifs/ps.gif) | . . . Current flow across well |
| 24 | ![[Patents]](../gifs/ps.gif) | . . . Field effect device |
| 25 | ![[Patents]](../gifs/ps.gif) | . . . Employing resonant tunneling |
| 26 | ![[Patents]](../gifs/ps.gif) | . . Ballistic transport device |
| 27 | ![[Patents]](../gifs/ps.gif) | . . . Field effect transistor |
| 28 | ![[Patents]](../gifs/ps.gif) | . Non-heterojunction superlattice (e.g., doping superlattice or alternating metal and insulator layers) |
| 29 | ![[Patents]](../gifs/ps.gif) | . Ballistic transport device (e.g., hot electron transistor) |
| 30 | ![[Patents]](../gifs/ps.gif) | . Tunneling through region of reduced conductivity |
| 31 | ![[Patents]](../gifs/ps.gif) | . . Josephson |
| 32 | ![[Patents]](../gifs/ps.gif) | . . . Particular electrode material |
| 33 | ![[Patents]](../gifs/ps.gif) | . . . . High temperature (i.e., >30 Kelvin) |
| 34 | ![[Patents]](../gifs/ps.gif) | . . . Weak link (e.g., narrowed portion of superconductive line) |
| 35 | ![[Patents]](../gifs/ps.gif) | . . . Particular barrier material |
| 36 | ![[Patents]](../gifs/ps.gif) | . . . With additional electrode to control conductive state of Josephson junction |
| 37 | ![[Patents]](../gifs/ps.gif) | . . At least one electrode layer of semiconductor material |
| 38 | ![[Patents]](../gifs/ps.gif) | . . . Three or more electrode device |
| 39 | ![[Patents]](../gifs/ps.gif) | . . Three or more electrode device |
| 40 | ![[Patents]](../gifs/ps.gif) | ORGANIC SEMICONDUCTOR MATERIAL |
| 41 | ![[Patents]](../gifs/ps.gif) | POINT CONTACT DEVICE |
| 42 | ![[Patents]](../gifs/ps.gif) | SEMICONDUCTOR IS SELENIUM OR TELLURIUM IN ELEMENTAL FORM |
| 43 | ![[Patents]](../gifs/ps.gif) | SEMICONDUCTOR IS AN OXIDE OF A METAL (E.G., CuO, ZnO) OR COPPER SULFIDE |
| 44 | ![[Patents]](../gifs/ps.gif) | WITH METAL CONTACT ALLOYED TO ELEMENTAL SEMICONDUCTOR TYPE PN JUNCTION IN NONREGENERATIVE STRUCTURE |
| 45 | ![[Patents]](../gifs/ps.gif) | . Elongated alloyed region (e.g., thermal gradient zone melting, TGZM) |
| 46 | ![[Patents]](../gifs/ps.gif) | . In pn junction tunnel diode (Esaki diode) |
| 47 | ![[Patents]](../gifs/ps.gif) | . In bipolar transistor structure |
| 48 | ![[Patents]](../gifs/ps.gif) | TEST OR CALIBRATION STRUCTURE |
| 49 | ![[Patents]](../gifs/ps.gif) | NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION) |
| 50 | ![[Patents]](../gifs/ps.gif) | . Non-single crystal, or recrystallized, active junction adapted to be electrically shorted (e.g., "anti-fuse" element) |
| 51 | ![[Patents]](../gifs/ps.gif) | . Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction) |
| 52 | ![[Patents]](../gifs/ps.gif) | . Amorphous semiconductor material |
| 53 | ![[Patents]](../gifs/ps.gif) | . . Responsive to nonelectrical external signals (e.g., light) |
| 54 | ![[Patents]](../gifs/ps.gif) | . . . With Schottky barrier to amorphous material |
| 55 | ![[Patents]](../gifs/ps.gif) | . . . Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si Ge , SiN ) |
| 56 | ![[Patents]](../gifs/ps.gif) | . . . With impurity other than hydrogen to passivate dangling bonds (e.g., halide) |
| 57 | ![[Patents]](../gifs/ps.gif) | . . Field effect device in amorphous semiconductor material |
| 58 | ![[Patents]](../gifs/ps.gif) | . . . With impurity other than hydrogen to passivate dangling bonds (e.g., halide) |
| 59 | ![[Patents]](../gifs/ps.gif) | . . . In array having structure for use as imager or display, or with transparent electrode |
| 60 | ![[Patents]](../gifs/ps.gif) | . . . With field electrode under or on a side edge of amorphous semiconductor material (e.g., vertical current path) |
| 61 | ![[Patents]](../gifs/ps.gif) | . . . With heavily doped regions contacting amorphous semiconductor material (e.g., heavily doped source and drain) |
| 62 | ![[Patents]](../gifs/ps.gif) | . . With impurity other than hydrogen to passivate dangling bonds (e.g., halide) |
| 63 | ![[Patents]](../gifs/ps.gif) | . . Amorphous semiconductor is alloy or contains material to change band gap (e.g., SixGe1-x, SiNy) |
| 64 | ![[Patents]](../gifs/ps.gif) | . Non-single crystal, or recrystallized, material with specified crystal structure (e.g., specified crystal size or orientation) |
| 65 | ![[Patents]](../gifs/ps.gif) | . Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., GexSi1-x, polycrystalline silicon with dangling bond modifier) |
| 66 | ![[Patents]](../gifs/ps.gif) | . Field effect device in non-single crystal, or recrystallized, semiconductor material |
| 67 | ![[Patents]](../gifs/ps.gif) | . . In combination with device formed in single crystal semiconductor material (e.g., stacked FETs) |
| 68 | ![[Patents]](../gifs/ps.gif) | . . . Capacitor element in single crystal semiconductor (e.g., DRAM) |
| 69 | ![[Patents]](../gifs/ps.gif) | . . . Field effect transistor in single crystal material, complememtary to that in non-single crystal, or recrystallized, material (e.g., CMOS) |
| 70 | ![[Patents]](../gifs/ps.gif) | . . . Recrystallized semiconductor material |
| 71 | ![[Patents]](../gifs/ps.gif) | . . In combination with capacitor element (e.g., DRAM) |
| 72 | ![[Patents]](../gifs/ps.gif) | . . In array having structure for use as imager or display, or with transparent electrode |
| 73 | ![[Patents]](../gifs/ps.gif) | . Schottky barrier to polycrystalline semiconductor material |
| 74 | ![[Patents]](../gifs/ps.gif) | . Plural recrystallized semiconductor layers (e.g., "3-dimensional integrated circuit") |
| 75 | ![[Patents]](../gifs/ps.gif) | . Recrystallized semiconductor material |
| 76 | ![[Patents]](../gifs/ps.gif) | SPECIFIED WIDE BAND GAP (> 1.5eV) SEMICONDUCTOR MATERIAL OTHER THAN GaAsP OR GaAlAs |
| 77 | ![[Patents]](../gifs/ps.gif) | . Diamond or Silicon Carbide |
| 78 | ![[Patents]](../gifs/ps.gif) | . II-IV compound |
| 79 | ![[Patents]](../gifs/ps.gif) | INCOHERENT LIGHT EMITTER STRUCTURE |
| 80 | ![[Patents]](../gifs/ps.gif) | . In combination with or also constituting light responsive device |
| 81 | ![[Patents]](../gifs/ps.gif) | . . With specific housing or contact structure |
| 82 | ![[Patents]](../gifs/ps.gif) | . . . Discrete light emitting and light responsive devices |
| 83 | ![[Patents]](../gifs/ps.gif) | . . Light coupled transistor structure |
| 84 | ![[Patents]](../gifs/ps.gif) | . . Combined in integrated structure |
| 85 | ![[Patents]](../gifs/ps.gif) | . . . With heterojunction |
| 86 | ![[Patents]](../gifs/ps.gif) | . Active layer of indirect band gap semiconductor |
| 87 | ![[Patents]](../gifs/ps.gif) | . . With means to facilitate electron-hole recombination (e.g., isoelectronic traps such as nitrogen in GaP) |
| 88 | ![[Patents]](../gifs/ps.gif) | . Plural light emitting devices (e.g., matrix, 7-segment array) |
| 89 | ![[Patents]](../gifs/ps.gif) | . . Multi-color emission |
| 90 | ![[Patents]](../gifs/ps.gif) | . . . With heterojunction |
| 91 | ![[Patents]](../gifs/ps.gif) | . . With shaped contacts or opaque masking |
| 92 | ![[Patents]](../gifs/ps.gif) | . . Alphanumeric segmented array |
| 93 | ![[Patents]](../gifs/ps.gif) | . . With electrical isolation means in integrated circuit structure |
| 94 | ![[Patents]](../gifs/ps.gif) | . With heterojunction |
| 95 | ![[Patents]](../gifs/ps.gif) | . . With contoured external surface (e.g., dome shape to facilitate light emission) |
| 96 | ![[Patents]](../gifs/ps.gif) | . . Plural heterojunctions in same device |
| 97 | ![[Patents]](../gifs/ps.gif) | . . . More than two heterojunctions in same device |
| 98 | ![[Patents]](../gifs/ps.gif) | . With reflector, opaque mask, or optical element (e.g., lens, optical fiber, index of refraction matching layer, luminescent material layer, filter) integral with device or device enclosure or package |
| 99 | ![[Patents]](../gifs/ps.gif) | . With housing or contact structure |
| 100 | ![[Patents]](../gifs/ps.gif) | . Encapsulated |
| 101 | ![[Patents]](../gifs/ps.gif) | . With particular dopant concentration or concentration profile (e.g., graded junction) |
| 102 | ![[Patents]](../gifs/ps.gif) | . With particular dopant material (e.g., Zinc as dopant in GaAs) |
| 103 | ![[Patents]](../gifs/ps.gif) | . With particular semiconductor material |
| 104 | ![[Patents]](../gifs/ps.gif) | TUNNELING PN JUNCTION (E.G., ESAKI DIODE) DEVICE |
| 105 | ![[Patents]](../gifs/ps.gif) | . In three or more terminal device |
| 106 | ![[Patents]](../gifs/ps.gif) | . Reverse bias tunneling structure (e.g., "backward" diode, true Zener diode) |
| 107 | ![[Patents]](../gifs/ps.gif) | REGENERATIVE TYPE SWITCHING DEVICE (E.G., SCR, COMFET, THYRISTOR) |
| 108 | ![[Patents]](../gifs/ps.gif) | . Controlled by nonelectrical, nonoptical external signal (e.g., magnetic field, pressure, thermal) |
| 109 | ![[Patents]](../gifs/ps.gif) | . Having only two terminals and no control electrode (gate) (e.g., Shockley diode) |
| 110 | ![[Patents]](../gifs/ps.gif) | . . More than four semiconductor layers of alternating conductivity types (e.g., pnpnpn structure, 5 layer bidirectional diacs, etc.) |
| 111 | ![[Patents]](../gifs/ps.gif) | . . Triggered by VBO overvoltage means |
| 112 | ![[Patents]](../gifs/ps.gif) | . . With highly-doped breakdown diode trigger |
| 113 | ![[Patents]](../gifs/ps.gif) | . With light activation |
| 114 | ![[Patents]](../gifs/ps.gif) | . . With separate light dector integrated on chip with regenerative switching device |
| 115 | ![[Patents]](../gifs/ps.gif) | . . With electrical trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.) |
| 116 | ![[Patents]](../gifs/ps.gif) | . . With light conductor means (e.g., light fiber or light pipe) integral with device or device enclosure or package |
| 117 | ![[Patents]](../gifs/ps.gif) | . . . In groove or with thinned semiconductor portion |
| 118 | ![[Patents]](../gifs/ps.gif) | . . With groove or thinned light sensitive portion |
| 119 | ![[Patents]](../gifs/ps.gif) | . Bidirectional rectifier with control electrode (gate) (e.g., Triac) |
| 120 | ![[Patents]](../gifs/ps.gif) | . . Six or more semiconductor layers of alternating conductivity types (e.g., npnpnpn structure) |
| 121 | ![[Patents]](../gifs/ps.gif) | . . With diode or transistor in reverse path |
| 122 | ![[Patents]](../gifs/ps.gif) | . . Lateral |
| 123 | ![[Patents]](../gifs/ps.gif) | . . With trigger signal amplification (e.g., amplified gate) |
| 124 | ![[Patents]](../gifs/ps.gif) | . . Combined with field effect transistor structure |
| 125 | ![[Patents]](../gifs/ps.gif) | . . . Controllable emitter shunting |
| 126 | ![[Patents]](../gifs/ps.gif) | . . With means to separate a device into sections having different conductive polarity |
| 127 | ![[Patents]](../gifs/ps.gif) | . . . Guard ring or groove |
| 128 | ![[Patents]](../gifs/ps.gif) | . . Having overlapping sections of different conductive polarity |
| 129 | ![[Patents]](../gifs/ps.gif) | . . With means to increase reverse breakdown voltage |
| 130 | ![[Patents]](../gifs/ps.gif) | . . Switching speed enhancement means |
| 131 | ![[Patents]](../gifs/ps.gif) | . . . Recombination centers or deep level dopants |
| 132 | ![[Patents]](../gifs/ps.gif) | . Five or more layer unidirectional structure |
| 133 | ![[Patents]](../gifs/ps.gif) | . Combined with field effect transistor |
| 134 | ![[Patents]](../gifs/ps.gif) | . . J-FET (junction field effect transistor) |
| 135 | ![[Patents]](../gifs/ps.gif) | . . . Vertical (i.e., where the source is located above the drain or vice versa) |
| 136 | ![[Patents]](../gifs/ps.gif) | . . . . Enhancement mode (e.g., so-called SITs) |
| 137 | ![[Patents]](../gifs/ps.gif) | . . Having controllable emitter shunt |
| 138 | ![[Patents]](../gifs/ps.gif) | . . . Having gate turn off (GTO) feature |
| 139 | ![[Patents]](../gifs/ps.gif) | . . With extended latchup current level (e.g., COMFET device) |
| 140 | ![[Patents]](../gifs/ps.gif) | . . . Combined with other solid state active device in integrated structure |
| 141 | ![[Patents]](../gifs/ps.gif) | . . . Lateral structure, i.e., current flow parallel to main device surface |
| 142 | ![[Patents]](../gifs/ps.gif) | . . . Having impurity doping for gain reduction |
| 143 | ![[Patents]](../gifs/ps.gif) | . . . Having anode shunt means |
| 144 | ![[Patents]](../gifs/ps.gif) | . . . Cathode emitter or cathode electrode feature |
| 145 | ![[Patents]](../gifs/ps.gif) | . . . Low impedance channel contact extends below surface |
| 146 | ![[Patents]](../gifs/ps.gif) | . Combined with other solid state active device in integrated structure |
| 147 | ![[Patents]](../gifs/ps.gif) | . With extended latchup current level (e.g., gate turn off "GTO" device) |
| 148 | ![[Patents]](../gifs/ps.gif) | . . Having impurity doping for gain reduction |
| 149 | ![[Patents]](../gifs/ps.gif) | . . Having anode shunt means |
| 150 | ![[Patents]](../gifs/ps.gif) | . . With specified housing or external terminal |
| 151 | ![[Patents]](../gifs/ps.gif) | . . . External gate terminal structure or composition |
| 152 | ![[Patents]](../gifs/ps.gif) | . . Cathode emitter or cathode electrode feature |
| 153 | ![[Patents]](../gifs/ps.gif) | . . Gate region or electrode feature |
| 154 | ![[Patents]](../gifs/ps.gif) | . With resistive region connecting separate sections of device |
| 155 | ![[Patents]](../gifs/ps.gif) | . With switching speed enhancement means (e.g., Schottky contact) |
| 156 | ![[Patents]](../gifs/ps.gif) | . . Having deep level dopants or recombination centers |
| 157 | ![[Patents]](../gifs/ps.gif) | . With integrated trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.) |
| 158 | ![[Patents]](../gifs/ps.gif) | . . Three or more amplification stages |
| 159 | ![[Patents]](../gifs/ps.gif) | . . Transistor as amplifier |
| 160 | ![[Patents]](../gifs/ps.gif) | . . With distributed amplified current |
| 161 | ![[Patents]](../gifs/ps.gif) | . . With a turn-off diode |
| 162 | ![[Patents]](../gifs/ps.gif) | . Lateral structure |
| 163 | ![[Patents]](../gifs/ps.gif) | . Emitter region feature |
| 164 | ![[Patents]](../gifs/ps.gif) | . . Multi-emitter region (e.g., emitter geometry or emitter ballast resistor) |
| 165 | ![[Patents]](../gifs/ps.gif) | . . . Laterally symmetric regions |
| 166 | ![[Patents]](../gifs/ps.gif) | . . . Radially symmetric regions |
| 167 | ![[Patents]](../gifs/ps.gif) | . Having at least four external electrodes |
| 168 | ![[Patents]](../gifs/ps.gif) | . With means to increase breakdown voltage |
| 169 | ![[Patents]](../gifs/ps.gif) | . . High resistivity base layer |
| 170 | ![[Patents]](../gifs/ps.gif) | . . Surface feature (e.g., guard ring, groove, mesa) |
| 171 | ![[Patents]](../gifs/ps.gif) | . . . Edge feature (e.g., beveled edge) |
| 172 | ![[Patents]](../gifs/ps.gif) | . With means to lower "ON" voltage drop |
| 173 | ![[Patents]](../gifs/ps.gif) | . Device protection (e.g., from overvoltage) |
| 174 | ![[Patents]](../gifs/ps.gif) | . . Rate of rise of current (e.g., dI/dt) |
| 175 | ![[Patents]](../gifs/ps.gif) | . With means to control triggering (e.g., gate electrode configuration, zener diode firing, dV/dt control, transient control by ferrite bead, etc.) |
| 176 | ![[Patents]](../gifs/ps.gif) | . . Located in an emitter-gate region |
| 177 | ![[Patents]](../gifs/ps.gif) | . With housing or external electrode |
| 178 | ![[Patents]](../gifs/ps.gif) | . . With means to avoid stress between electrode and active device (e.g., thermal expansion matching of electrode to semiconductor) |
| 179 | ![[Patents]](../gifs/ps.gif) | . . . With malleable electrode (e.g., silver electrode layer) |
| 180 | ![[Patents]](../gifs/ps.gif) | . . Stud mount |
| 181 | ![[Patents]](../gifs/ps.gif) | . . With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element (e.g., ring) |
| 182 | ![[Patents]](../gifs/ps.gif) | . . . With lead feedthrough means on side of housing |
| 183 | ![[Patents]](../gifs/ps.gif) | HETEROJUNCTION DEVICE |
| 183.1 | ![[Patents]](../gifs/ps.gif) | . Charge transfer device |
| 184 | ![[Patents]](../gifs/ps.gif) | . Light responsive structure |
| 185 | ![[Patents]](../gifs/ps.gif) | . . Staircase (including graded composition) device |
| 186 | ![[Patents]](../gifs/ps.gif) | . . Avalanche photodetection structure |
| 187 | ![[Patents]](../gifs/ps.gif) | . . Having transistor structure |
| 188 | ![[Patents]](../gifs/ps.gif) | . . Having narrow energy band gap (<<1eV) layer (e.g., PbSnTe, HgCdTe, etc.) |
| 189 | ![[Patents]](../gifs/ps.gif) | . . . Layer is a group III-V semiconductor compound |
| 190 | ![[Patents]](../gifs/ps.gif) | . With lattice constant mismatch (e.g., with buffer layer to accomodate mismatch) |
| 191 | ![[Patents]](../gifs/ps.gif) | . Having graded composition |
| 192 | ![[Patents]](../gifs/ps.gif) | . Field effect transistor |
| 194 | ![[Patents]](../gifs/ps.gif) | . . Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT) |
| 195 | ![[Patents]](../gifs/ps.gif) | . . . Combined with diverse type device |
| 196 | ![[Patents]](../gifs/ps.gif) | . Both semiconductors of the heterojunction are the same conductivity type (i.e., either N or P) |
| 197 | ![[Patents]](../gifs/ps.gif) | . Bipolar transistor |
| 198 | ![[Patents]](../gifs/ps.gif) | . . Wide band gap emitter |
| 199 | ![[Patents]](../gifs/ps.gif) | . Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts, including heterojunction IMPATT type microwave diodes) |
| 200 | ![[Patents]](../gifs/ps.gif) | . Heterojunction formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., Ge (group IV) - GaAs (group III-V) or InP (group III-V) - CdTe (group II-VI)) |
| 201 | ![[Patents]](../gifs/ps.gif) | . Between different group IV-VI or II-VI or III-V compounds other than GaAs/GaAlAs |
| 202 | ![[Patents]](../gifs/ps.gif) | GATE ARRAYS |
| 203 | ![[Patents]](../gifs/ps.gif) | . With particular chip input/output means |
| 204 | ![[Patents]](../gifs/ps.gif) | . Having specific type of active device (e.g., CMOS) |
| 205 | ![[Patents]](../gifs/ps.gif) | . . With bipolar transistors or with FETs of only one channel conductivity type (e.g., enhancement-depletion FETs) |
| 206 | ![[Patents]](../gifs/ps.gif) | . . Particular layout of complementary FETs with regard to each other |
| 207 | ![[Patents]](../gifs/ps.gif) | . With particular power supply distribution means |
| 208 | ![[Patents]](../gifs/ps.gif) | . With particular signal path connections |
| 209 | ![[Patents]](../gifs/ps.gif) | . . Programmable signal paths (e.g., with fuse elements, laser programmable, etc.) |
| 210 | ![[Patents]](../gifs/ps.gif) | . . With wiring channel area |
| 211 | ![[Patents]](../gifs/ps.gif) | . . Multi-level metallization |
| 212 | ![[Patents]](../gifs/ps.gif) | CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE-BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR) |
| 213 | ![[Patents]](../gifs/ps.gif) | FIELD EFFECT DEVICE |
| 214 | ![[Patents]](../gifs/ps.gif) | . Charge injection device |
| 215 | ![[Patents]](../gifs/ps.gif) | . Charge transfer device |
| 216 | ![[Patents]](../gifs/ps.gif) | . . Majority signal carrier (e.g., buried or bulk channel, or peristaltic) |
| 217 | ![[Patents]](../gifs/ps.gif) | . . . Having a conductive means in direct contact with channel (e.g., non- insulated gate) |
| 218 | ![[Patents]](../gifs/ps.gif) | . . . High resistivity channel (e.g., accumulation mode) or surface channel (e.g., transfer of signal charge occurs at the surface of the semi-conductor) or minority carriers at input (e.g., surface channel input) |
| 219 | ![[Patents]](../gifs/ps.gif) | . . . Impurity concentration variation |
| 220 | ![[Patents]](../gifs/ps.gif) | . . . . Vertically within channel (e.g., profiled) |
| 221 | ![[Patents]](../gifs/ps.gif) | . . . . Along the length of the channel (e.g., doping variations for transfer directionality) |
| 222 | ![[Patents]](../gifs/ps.gif) | . . . Responsive to non-electrical external signal (e.g., imager) |
| 223 | ![[Patents]](../gifs/ps.gif) | . . . . Having structure to improve output signal (e.g., antiblooming drain) |
| 224 | ![[Patents]](../gifs/ps.gif) | . . . Channel confinement |
| 225 | ![[Patents]](../gifs/ps.gif) | . . Non-electrical input responsive (e.g., light responsive imager, input programmed by size of storage sites for use as a read-only memory, etc.) |
| 226 | ![[Patents]](../gifs/ps.gif) | . . . Sensor element and charge transfer device are of different materials or on different substrates (e.g., "hybrid") |
| 227 | ![[Patents]](../gifs/ps.gif) | . . . With specified dopant (e.g., photoionizable, "extrinsic" detectors for infrared) |
| 228 | ![[Patents]](../gifs/ps.gif) | . . . Light responsive, back illuminated |
| 229 | ![[Patents]](../gifs/ps.gif) | . . . Having structure to improve output signal (e.g., exposure control structure) |
| 230 | ![[Patents]](../gifs/ps.gif) | . . . . With blooming suppression structure |
| 231 | ![[Patents]](../gifs/ps.gif) | . . . 2-dimensional area architecture |
| 232 | ![[Patents]](../gifs/ps.gif) | . . . . Having alternating strips of sensor structures and register structures (e.g., interline imager) |
| 233 | ![[Patents]](../gifs/ps.gif) | . . . . Sensors not overlaid by electrode (e.g., photodiodes) |
| 234 | ![[Patents]](../gifs/ps.gif) | . . . Single strip of sensors (e.g., linear imager) |
| 235 | ![[Patents]](../gifs/ps.gif) | . . Electrical input |
| 236 | ![[Patents]](../gifs/ps.gif) | . . . Signal applied to field effect electrode |
| 237 | ![[Patents]](../gifs/ps.gif) | . . . . Charge-presetting/linear input type (e.g., fill and spill) |
| 238 | ![[Patents]](../gifs/ps.gif) | . . . Input signal responsive to signal charge in charge transfer device (e.g., regeneration or feedback) |
| 239 | ![[Patents]](../gifs/ps.gif) | . . Signal charge detection type (e.g., floating diffusion or floating gate non-destructive output) |
| 240 | ![[Patents]](../gifs/ps.gif) | . . Changing width or direction of channel (e.g., meandering channel) |
| 241 | ![[Patents]](../gifs/ps.gif) | . . Multiple channels (e.g., converging or diverging or parallel channels) |
| 242 | ![[Patents]](../gifs/ps.gif) | . . Vertical charge transfer |
| 243 | ![[Patents]](../gifs/ps.gif) | . . Channel confinement |
| 244 | ![[Patents]](../gifs/ps.gif) | . . Comprising a groove |
| 245 | ![[Patents]](../gifs/ps.gif) | . . Structure for applying electric field into device (e.g., resistive electrode, acoustic traveling wave in channel) |
| 246 | ![[Patents]](../gifs/ps.gif) | . . . Phase structure (e.g., doping variations to provide asymmetry for 2-phase operation; more than four phases or "electrode per bit") |
| 247 | ![[Patents]](../gifs/ps.gif) | . . . . Uniphase or virtual phase structure |
| 248 | ![[Patents]](../gifs/ps.gif) | . . . . 2-phase |
| 249 | ![[Patents]](../gifs/ps.gif) | . . . Electrode structures or materials |
| 250 | ![[Patents]](../gifs/ps.gif) | . . . . Plural gate levels |
| 251 | ![[Patents]](../gifs/ps.gif) | . . Substantially incomplete signal charge transfer (e.g., bucket brigade) |
| 252 | ![[Patents]](../gifs/ps.gif) | . Responsive to non-optical, non-electrical signal |
| 253 | ![[Patents]](../gifs/ps.gif) | . . Chemical (e.g., ISFET, CHEMFET) |
| 254 | ![[Patents]](../gifs/ps.gif) | . . Physical deformation (e.g., strain sensor, acoustic wave detector) |
| 255 | ![[Patents]](../gifs/ps.gif) | . With current flow along specified crystal axis (e.g., axis of maximum carrier mobility) |
| 256 | ![[Patents]](../gifs/ps.gif) | . Junction field effect transistor (unipolar transistor) |
| 257 | ![[Patents]](../gifs/ps.gif) | . . Light responsive or combined with light responsive device |
| 258 | ![[Patents]](../gifs/ps.gif) | . . . In imaging array |
| 259 | ![[Patents]](../gifs/ps.gif) | . . Elongated active region acts as transmission line or distributed active element (e.g., "transmission line" field effect transistor) |
| 260 | ![[Patents]](../gifs/ps.gif) | . . Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell) |
| 261 | ![[Patents]](../gifs/ps.gif) | . . Junction gate region free of direct electrical connection (e.g., floating junction gate memory cell structure) |
| 262 | ![[Patents]](../gifs/ps.gif) | . . Combined with insulated gate field effect transistor (IGFET) |
| 263 | ![[Patents]](../gifs/ps.gif) | . . Vertical controlled current path |
| 264 | ![[Patents]](../gifs/ps.gif) | . . . Enhancement mode or with high resistivity channel (e.g., doping of 1015cm-3 or less) |
| 265 | ![[Patents]](../gifs/ps.gif) | . . . In integrated circuit |
| 266 | ![[Patents]](../gifs/ps.gif) | . . . With multiple parallel current paths (e.g., grid gate) |
| 267 | ![[Patents]](../gifs/ps.gif) | . . . . With Schottky barrier gate |
| 268 | ![[Patents]](../gifs/ps.gif) | . . Enhancement mode |
| 269 | ![[Patents]](../gifs/ps.gif) | . . . With means to adjust barrier height (e.g., doping profile) |
| 270 | ![[Patents]](../gifs/ps.gif) | . . Plural, separately connected, gates control same channel region |
| 271 | ![[Patents]](../gifs/ps.gif) | . . Load element or constant current source (e.g., with source to gate connection) |
| 272 | ![[Patents]](../gifs/ps.gif) | . . Junction field effect transistor in integrated circuit |
| 273 | ![[Patents]](../gifs/ps.gif) | . . . With bipolar device |
| 274 | ![[Patents]](../gifs/ps.gif) | . . . Complementary junction field effect transistors |
| 275 | ![[Patents]](../gifs/ps.gif) | . . . Microwave integrated circuit (e.g., microstrip type) |
| 276 | ![[Patents]](../gifs/ps.gif) | . . . . With contact or heat sink extending through hole in semiconductor substrate, or with electrode suspended over substrate (e.g., air bridge) |
| 277 | ![[Patents]](../gifs/ps.gif) | . . . . With capacitive or inductive elements |
| 278 | ![[Patents]](../gifs/ps.gif) | . . . With devices vertically spaced in different layers of semiconductor material (e.g., "3-dimensional" integrated circuit) |
| 279 | ![[Patents]](../gifs/ps.gif) | . . Pn junction gate in compound semiconductor material (e.g., GaAs) |
| 280 | ![[Patents]](../gifs/ps.gif) | . . With Schottky gate |
| 281 | ![[Patents]](../gifs/ps.gif) | . . . Schottky gate to silicon semiconductor |
| 282 | ![[Patents]](../gifs/ps.gif) | . . . Gate closely aligned to source region |
| 283 | ![[Patents]](../gifs/ps.gif) | . . . . With groove or overhang for alignment |
| 284 | ![[Patents]](../gifs/ps.gif) | . . . Schottky gate in groove |
| 285 | ![[Patents]](../gifs/ps.gif) | . . With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface) |
| 286 | ![[Patents]](../gifs/ps.gif) | . . With non-uniform channel thickness or width |
| 287 | ![[Patents]](../gifs/ps.gif) | . . With multiple channels or chanel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET) |
| 288 | ![[Patents]](../gifs/ps.gif) | . Having insulated electrode (e.g., MOSFET, MOS diode) |
| 289 | ![[Patents]](../gifs/ps.gif) | . . Significant semiconductor chemical compound in bulk crystal (e.g., GaAs) |
| 290 | ![[Patents]](../gifs/ps.gif) | . . Light responsive or combined with light responsive device |
| 291 | ![[Patents]](../gifs/ps.gif) | . . . Imaging array |
| 292 | ![[Patents]](../gifs/ps.gif) | . . . . Photodiodes accessed by FETs |
| 293 | ![[Patents]](../gifs/ps.gif) | . . . . Photoresistors accessed by FETs, or photodetectors separate from FET chip |
| 294 | ![[Patents]](../gifs/ps.gif) | . . . . With shield, filter, or lens |
| 295 | ![[Patents]](../gifs/ps.gif) | . . With ferroelectric material layer |
| 296 | ![[Patents]](../gifs/ps.gif) | . . Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell) |
| 297 | ![[Patents]](../gifs/ps.gif) | . . . With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection) |
| 298 | ![[Patents]](../gifs/ps.gif) | . . . Capacitor for signal storage in combination with non-volatile storage means |
| 299 | ![[Patents]](../gifs/ps.gif) | . . . Structure configured for voltage converter (e.g., charge pump, substrate bias generator) |
| 300 | ![[Patents]](../gifs/ps.gif) | . . . Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., nondestructive readout dynamic memory cell structure) |
| 301 | ![[Patents]](../gifs/ps.gif) | . . . Capacitor in trench |
| 302 | ![[Patents]](../gifs/ps.gif) | . . . . Vertical transistor |
| 303 | ![[Patents]](../gifs/ps.gif) | . . . . Stacked capacitor |
| 304 | ![[Patents]](../gifs/ps.gif) | . . . . Storage node isolated by dielectric from semiconductor substrate |
| 305 | ![[Patents]](../gifs/ps.gif) | . . . . With means to insulate adjacent storage nodes (e.g., channel stops or field oxide) |
| 306 | ![[Patents]](../gifs/ps.gif) | . . . Stacked capacitor |
| 307 | ![[Patents]](../gifs/ps.gif) | . . . . Parallel interleaved capacitor electrode pairs (e.g., interdigitized) |
| 308 | ![[Patents]](../gifs/ps.gif) | . . . . . With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post) |
| 309 | ![[Patents]](../gifs/ps.gif) | . . . . With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes) |
| 310 | ![[Patents]](../gifs/ps.gif) | . . . With high dielectric constant insulator (e.g., Ta2Os) |
| 311 | ![[Patents]](../gifs/ps.gif) | . . . Storage node isolated by dielectric from semiconductor substrate |
| 312 | ![[Patents]](../gifs/ps.gif) | . . . Voltage variable capacitor (i.e., capacitance varies with applied voltage) |
| 313 | ![[Patents]](../gifs/ps.gif) | . . . Inversion layer capacitor |
| 314 | ![[Patents]](../gifs/ps.gif) | . . Variable threshold (e.g., floating gate memory device) |
| 315 | ![[Patents]](../gifs/ps.gif) | . . . With floating gate electrode |
| 316 | ![[Patents]](../gifs/ps.gif) |