This class provides for active solid-state electronic devices, that is, electronic devices or components that are made up primarily of solid materials, usually semiconductors, which operate by the movement of charge carriers - electrons or holes - which undergo energy level changes within the material and can modify an input voltage to achieve rectification, amplification, or switching action, and are not classified elsewhere.
SCOPE OF THE CLASS
Active solid-state electronic devices include diodes, transistors, thyristors, etc., but exclude pure resistors, capacitors, inductors, or combinations solely thereof. The latter class of devices is characterized as passive.
The subject matter to be found here includes only active solid-state devices, per se. It may include one or more such devices combined with contacts or leads, or structures configured to be tested on a semiconductor chip, or merely semiconductor material without contacts or leads where the sole disclosed use is an active solid-state device. This subject matter does not include active solid-state devices combined with significant circuits.
Claims reciting an integrated circuit nominally with significant metallization will be classified in Class 257, whereas otherwise, nominal recitation of an integrated
circuit (i.e., without significant active solid-state device recitation) will not be sufficient to permit the device to be classified in Class 257.
KEY CONCEPTS
See Subclass References to the Current Class, below, for references that relate to key concepts and terms found in Class 257. An indication that a particular concept or term occurs in one or more subclasses does not mean that the indicated subclass or subclasses are the only places that subject matter may be found. That subject matter may possibly be found elsewhere in Class 257 listed under a related term or concept that may be broader or narrower or of the same scope.

LINES WITH OTHER CLASSES AND WITHIN THIS CLASS
A. Classes related to Class 257 subject matter in the sense that they employ active solid-state devices in electronic circuits and the relationship of these classes to Class 257 is mainly that of a combination to a subcombination or of a genus to a specie. See References to Other Classes, below, referencing this section.
B. Classes related to Class 257 subject matter in the sense that they employ active solid-state devices in electronic circuits and the use of active solid-state electronic devices primarily as a perfecting feature. See References to Other Classes, below, referencing this section.
C. See References to Other Classes below for classes that provide for materials used in active solid-state electronic devices.
D. See References to Other Classes, below, for classes related to Class 257 because they provide for methods of making, cleaning, coating, etc., active solid-state devices, e.g., Class 438, Semiconductor Device Manufacturing: Process.
E. See References to Other Classes, below, for Classes related to Class 257 because they provide for active solid-state electronic devices structures with a specified use, e.g., Class 136, Batteries: Thermoelectric and Photoelectric.
F. See References to Other Classes, below, for classes providing for provide for subcombination subject matter that can be used as component part of active solid-state electronic devices (e.g., lead frames) or perfect the device (e.g., a heat sink).
G. Classes which provide for passive solid-state electronic devices with names that may refer to either active or passive solid-state electronic devices, e.g., coherers, varistors, varactors. luminescent or electroluminescent devices. The
devices may be part of the main subject matter of the class or may be used as circuit elements in circuits or control or measuring systems which form the main subject matter of the class.
See References to Other Classes, below, referencing this section.

SEE OR SEARCH THIS CLASS, SUBCLASS:
1 through 8, for bulk effect device.
2 - 5, 16, 52-63, and 646, for amorphous semiconductor material.
4 72, 91, 144, 150, 151, 175-177, 181, 182, 207-211, 246-250, 276, 309, 317, 401, 448, 457, 459, 503, 508, 573, 584, 587, 602, 621, 625, 666-676, and 692-697, for configuration of electrode, contact, lead or pad.
4 32, 33, 81, 91, 99, 144, 150-153, 177-179, 181, 182, 203, 207-211, 276, 377, 382-385, 459, 503, 522, 554, 573, 576, 584, 602, 621, 625, 661-677, 690-700, and 734-786, for electrical contact or lead.
6 through 8, for Gunn effect (intervalley transfer).
7 for intervalley transfer (e.g., Gunn) device in integrated circuit.
10 through 11, and 407, for controlled work function material.
10 and 11, for electron emissive layer.
10 through 27, and 104-106, for heterojunction involving quantum-mechanical tunneling.
10 and 11, for photocathode.
10 54, 73, 155, 192-195, 217, 260, 267, 269, 275-277, 280-284, 449-457, 471-486, and 928, for Schottky barrier.
10 11, 30-39, and 314-326, for tunneling-insulator layer.
10 11, and 407, for work function of material, controlled, e.g., low.
13 76, 78, 85, 90, and 94-97, for heterojunction light emitter.
13 79-103, and 918, for light emitting device.
13 through 25, for quantum well device.
15 through 22, and 28, for superlattice.
16 55, 63, and 65, for heterojunction in non-single-crystal material.
18 19, and 190, for mismatched or strained lattice.
18 19, and 190, for mismatch of lattice constant.
18 and 19, for strained layer superlattice heterojunction.
19 76, 78, 103, 200-201, and 613-616, for alloy of two different semiconductors (e.g., Ga[subscrpt]x[end subscrpt]In[subscrpt]1-x[end subscrpt]As).
20 24, 27, 57-61, 66-72, 133-145, 192-195, 202-211, 213, and 252-413, for field effect devices.
20 24, and 194, for HEMT (High electron mobility transistor).
20 27, 187, and 192-195, for heterojunction FETs.
21 85, 184-189, for heterojunction in light responsive device.
21 for light responsive or activated device (superlattice quantum well heterojunction).
21 53-56, 59, 72, 80-85, 113-118, 184-189, 222, 223, 225-234, 257, 258, 290-294, 325, 428-466, 680, 681, and 749, for radiation responsive.
21 and 187, for light responsive heterojunction transistor.
21 187, 443, and 462, for photosensitive bipolar transistor.
26 27, and 29, for ballistic transport device.
26 27, and 29, for ballistic transport transistor.
31 through 36, for Josephson device.
31 through 36, and 661-663, for superconductive element/device.
31 through 36, 468, and 661-663, for thermal device operated at cryogenic temperature.
33 for high temperature (30 K) Josephson device.
40 for organic semiconductor material.
41 for point contact device.
42 for Selenium (elemental).
44 through 47, for alloyed junction.
45 for thermal gradient zone melting (TGZM).
46 104, and 105, for Esaki diode.
46 and 104-106, for p-n junction type (Esaki type) tunneling.
47 197, 205, 273, 350, 361, 370, 378, 423, 462, 477 though 479, 511, 512, 517, 518, 525, 526, 539-543, and 552-593, for bipolar transistor structure.
47 for alloyed junction bipolar transistor.
48 and 797, for calibration or test structure.5, for array of bulk effect amorphous switches.
48 for test structures.
49 through 75, for non-single crystal, as active layer.
49 through 51, 64-75, 359, 377, 380-382, 385, 412, 505, 518, 520, 524-527, 538, 554, 576, 581, 588, and 754-757, for polycrystalline semiconductor material.
49 through 51, and 64-75, for polycrystalline active junction material.
49 through 51, and 64-75, for recrystallized active semiconductor layer.
50 and 530, for anti-fuse component or element.
50 530, and 928, for shorted devices, in general, e.g., anti-fuse elements.
53 through 56, for amorphous semiconductor material device.
53 through 56, 108, 225, 252, and 414, for responsiveness to nonelectric signal.
55 and 63, for alloy of amorphous semiconductor materials.
55 63, and 65, and 646, for silicon nitride to increase band gap of amorphous or polycrystalline silicon.
56 58, 62, and 65, for for dangling bond.
56 58, 62, and 68, for passivation of dangling bonds in nonsingle crystal semiconductor.
57 through 61, 66-72, and 368-401, for insulated gate FET in integrated circuit.
57 through 61, and 66-72, for FET in non-single crystal or recrystallized semiconductor material (e.g., amorphous or polycrystalline semiconductor as channel).
59 72, and 88-93, for array as imager, or with transparent electrode, or as display (with plural light emitters).
59 72, 449-457, and 749, for electrical contact or lead transparent to light.
59 72, and 293, for photoresistor combined with accessing FET.
59 72, 453, and 749, for transparent electrode.
60 135, 136, 263-267, 302, and 328-334, for vertical channel field effect device.
64 255, 521, 627, and 628, for crystal axis or plane.
65 for alloy of polycrystalline semiconductor materials.
66 67, 69, 379-381, 903, and 904, for static memory cell using FET.
67 through 70, for stacked FETs.
67 69, 70, and 74, for stacked FETs.
68 through 71, 296-313, 296, 298, 300, 906, and 908, for capacitance combined with insulated gate device. (e.g., DRAM).
68 71, and 295-313, for insulated gate device (capacitor or combined with capacitor).
68 71, 296-313, and 905-908, for memory device component involving a capacitor (e.g., dynamic memory cell).
68 71, 303, and 306-309, for stacked capacitors in DRAM cell.
68 and 301-305, for capacitor in trench.
68 283, 284, 330-334, 374, 397, 513, 514, 622, 647, and 648, for vertical walled groove in semiconductor.
69 195, 204, 206, 338, 350, 351, 357-359, and 365-377, for CMOS.
69 195, 204, 206, 274, 338, 350, 351, 357-359, and 369-377, for complementary field effect transistors.
74 and 278, for three-dimensional integrated circuit.
76 through 78, and 183-201, for heterojunction, generally.
76 through 78, for wide band gap semiconductor material other than GaAsP or GaAlAs.
80 through 85, for light responsive or activated device
combined with light emitting device.
81 99, 177 -181, 584, 625, 675, 688, 689, 705, 707, 712-722, and 796, for heat sink.
81 82, and 99, for housing or package for light emitter.
81 and 82, for housing or package for light emitter combined with light receiver.
81 82, 433, 434, 680, 681, for housing or package for light responsive device.
81 99, and 666-677, for lead frame.
83 for light coupled transistor structure.
86 and 87 for indirect band gap active layer - light emitter.
87 131, 156, 439, 523, 590, and 608-612, for deep level dopant/impurity.
87 126, 131, 156, 523, 590, 609-612, and 617, for recombination centers.
91 98, 151, 175, 176, 249, 250, 276, 282-284, 309, 317, 401, 418, 435, 448, 457, 459, 503, 508, 534, 573, 587, 602, 621, 662, and 664, for shape(d) contact, electrode, conductor, or terminal.
91 98, 294, 323, 435, and 659, for optical shield.
93 for plural light emitters in integrated circuit.
93 374, 446, 499 and 564, for electrical isolation of components in integrated circuit.
95 117, 118, 127, 170, 244, 283, 284, 301-305, 330-334, 418, 419, 447, 460, 466, 496, 534, 571, 586, and 618-628, for grooves, generally.
95 170, 171, 452, 466, 496, 571, 586, 594, 600, 618, and 623-626, for mesa structure.
95 for shaped contact, electrode, etc., external of heterojunction light emitter.
98 116, 117, 294, and 432, for light fiber, guide, or pipe.
98 for luminescent material used with light emitter.
98 181, 418, 688, 710, 711, 728, and 730, for shaped housing or package.
98 99, 116, 434, 680, and 681, for window (optical) for housing.
100 433, 434, 667, 687, 767-and 796, for encapsulated.
101 194, 219-221, 264, 269, 285, 335-345, 404, 430, 450, 458, 463, 492, 493, 497, 498, 543, 545, 548, 558, 583, 591, 592, 596, 597, 605, 606, 655-657, 927, and 929, for dopant/impurity concentration, incl., graded profile.
102 227, 439, and 607-612, for specified, generally (e.g., photoionizable).
106 for reverse conducting diode (tunnel diode).
106 for Zener diode.
107 through 182, and 918, for regenerative switching device.
108 252, and 421-427, for magnetic field responsive.
108 225, 254, and 415 and-419, for device responsive to pressure.
108 222, 225, 254, and 417-419, for strain sensor.
108 225, 252, and 467-470, for passivating device responsive to temperature.
109 for Shockley diode.
110 and 119-131, for bidirectional device (diac, rectifier).
113 through 118, for regenerative-type switching device.
115 123, and 157-161, for amplified gate in thyristor.
121 for reverse conducting thyristor.
121 for Static Induction Transistor (SIT) - Bipolar transistor as reverse path of bidirectional conducting thyristor.
122 141, 146, and 162, for lateral structure in regenerative device.
124 125, and 133-145, for FET in or combined with thyristor.
125 137, 138, 143, and 149, for shunt, regenerative device.
125 137, 138, 143, 149, and 154, for shorted emitter, anode or cathode, in thyristor.
127 446, 510-522, 571, 577, and 594, for groove to define plural devices.
127 170, 339, 372-376, 394-400, 409, 452, 484, 490, 493-495,
and 605, for guard ring or region.
131 156, 376, 424, 523, 590, and 617, for crystal damage.
133 145, 195, 205, 273, 337, 350, 361, 362, 370, and 378, for field effect combined with bipolar type (including regenerative type) device.
134 through 136, 217, 256-287, and 504, for JFET.
136 205, 264, 268, 269, 392, for enhancement mode.
139 through 145, and 212, for conductivity modulated transistor.
139 through 145, 147-153, for extended latching current device.
139 through 145, 147-153, and 372-376, for means to prevent latchup.
139 through 145, and 211, for conductivity modulated transistor.
142 148, 376, 553, and 583, for doping for gain reduction.
146 476-479, and 499-564, for structure with elec. isolated components.
150 151, 177-181, for housing or package for regenerative type switching device.
154 169, 194, 195, 218, 264, 523, 646, and 656, for high resistivity semiconductor region - see, also, intrinsic material; PIN device.
154 350, 358, 359, 363, 379-381, 516, 533, 536-543, 571, 572, 577, 580-582, and 904, for resistive element (resistor) (passive device).
164 and 580-582, for ballasting of current (e.g., by resistors).
164 through 166, 560-561, 563, and 579- 581, for multiple/plural emitter.
170 for edge, beveled - preventing breakdown.
171 496, 586, and 618+, for bevel.
171 452, 483, and 484, for protection against edge breakdown.
171 and 496, for reverse bevels.
173 174, 328, 355-363, 487-496, and 546, for protection against overcurrent or overvoltage.
173 529, 665, and 910, for fuse/fusible link.
173 for overvoltage protection means in thyristor.
177 through 181, 467, 468, 573, 625, 675, 688, 705-707, and 712-722, for cooling.
178 179, and 746-748, for stress avoidance between electrode and semiconductor.
178 through 179, 633, 747, and 748, for thermal expansion matching or compensation.
180 and 733, for stud-type mount for housing.
180 and 733, for stud mount.
181 182, 688, 689, 726, 727, and 785 for press contact of electrode and semiconductor.
184 through 189, for heterojunction.
185 and 191, for graded band gap.
185 for staircase (light responsive heterojunction).
187 197, and 198, for heterojunction bipolar transistor.
193 215-251, and 912, for charge transfer device.
193 for charge transfer device.
198 for wide band gap emitter heterojunction bipolar transistor.
199 481, 482, 551, and 603-606, for avalanche diode.
199 482, and 604, for IMPATT.
199 259, 275-277, 482, 523, 604, 624, 625, 659, 662, 664, and 728, for for microwave device component.
202 and 909, for master slice (gate array).
202 and 909, for gate arrays.
202 through 211, and 909, for gate arrays.
205 273, 350, 361, 370, and 378, for bipolar combined with field effect type device.
205 273, 350, 361, 370, and 378, for bipolar transistor structure combined with FET.
206 208, 210, and 211, for configuration of elements in gate array.
209 for gate array with programmable signal paths.
210 and 758-760, for multi-level metallization.
212 for double-base diode (unijunction transistor).
212 for Static Induction Transistor (SIT) - Unijunction transistor.
212 for unijunction transistor.
214 for charge injection device.
215 218, and 225-251, for surface channel charge transfer device.
216 for bulk channel device.
216 and 285, for buried channel.
219 through 221, for nonuniform channel doping in buried channel CCD.
223 230, and 445, for antiblooming.
223 230, and 445, for suppression of blooming in light imager.
224 and 243, for channel confinement.
225 253, and 414, for chemical sensor.
225 for CCD with fixed pattern memory as ROM.
228 447, 460, for backside illumination.
239 for floating diffusion as CCD Output Tap.
239 261, and 315-323, for floating gate.
240 for nonuniform channel thickness in CCD.
241 for parallel channels in CCD.
245 364, and 489, for resistive electrode.
246 through 248, for nonuniform channel doping in CCD, for directionality.
249 317, 359, 363, 364, 377, 380-382, 384, 385, 387, 407, 412, 413, 489, 505, 518, 520, 524-527, 538, 554, 576, 581, 588, 646, 754-756, 904, and 914, for polycrystalline material (including polysilicon contacts) other than active junction material.
251 for bucket-brigade device.
254 and 416, for acoustic energy detector.
256 and 257, for light responsive PIN device combined with JFET.
257 and 258, for JFET.
227 and 439, for photoionization.
258 291-294, 443-448, and 911, for array of electrode field effect devices.
260 and 262, in or combined with a JFET device.
260 and 261, for memory device component involving a JFET (e.g., taper isolated or floating pn junction gate type).
265 for vertical current path JFET in integrated circuit.
266 267, and 287, for parallel channels in JFET.
269 and 285, for nonuniform channel doping in JFET.
272 through 278, for JFET in integrated circuit.
275 through 278, 662, and 664, for stripline lead.
276 for air bridge electrical lead.
276 for air bridge contact.
283 and 284, for groove alignment of Schottky gate to source region in MESFET.
283 through 284, 330-334, for gate electrode of FET formed in groove.
286 for nonuniform channel thickness in JFET.
290 and 294, for IGFET.
291 through 294, 326, 334, 337, 338, 347-363, and 368-401, for insulated gate device (IGFET in integrated circuit).
294 297, 340, 409, 435, 488-490, 503, 508, 630, 659-660, and 662, for shield electrode.
295 298, and 314-326, for EPROM/EEPROM.
295 298, 314, and 324-326, for MNOS insulated gate-type memory device component.
297 349, 547, and 620, for means to prevent charge leakage or leakage current.
297 349, 354, 372-376, 503, 547, and 620, for means to
prevent leakage current or charge leakage.
297 660, and 921, for protection against radiation (e.g., alpha particles).
297 660, and 921, for radiation protection.
297 422, and 659-660, for ionizing radiation shield, charged particles, electric or magnetic fields.
298 and 315-326, for insulated gate device (floating gate memory device).
298 and 315-323, for floating insulated gate memory-type memory device component.
299 for substrate bias (electrical generator.
301 through 305, 534, and 599, for groove involving a capacitor.
305 354, 376, 398-400, 519, 620, 648, and 652, for channel stop.
305 333, 374, 389, 395-399, 510-521, and 632-651, for field oxide.
312 480, and 595-602, for voltage variable capacitance device.
314 through 326 for variable threshold insulated gate device (e.g., EEPROM, non-volatile memory MOSFET).
322 for programming of floating gate MISFET (avalanche breakdown).
323 680, and 681, for light erasure of EPROM.
325 for oxynitride as insulator in MNOS memory IGFET.
327 through 346, for short channel.
328 and 355-363, for overvoltage protection means in IGFET.
328 and 355-363, for MOSFET gate protection.
331 341, 342, and 401, for parallel channels in IGFET.
332 346, 387, 388, 412, and 413, for self-aligned MOSFET gate.
333 340, and 386-389, for reduction of gate capacitance (FET).
333 346, 387, and 388, for overlap of gate electrode with source or drain in IGFET.
334 337, and 338, for VMOS or DMOS short channel IGFET in integrated circuit.
336 344, 408, and 900, for LDD (lightly doped drain) device.
339 409, 483, 484, and 487-496, for preventing avalanche breakdown.
339 409, and 488-490, for field relief electrode.
339 409, 490, and 495, for floating pn junction guard region.
340 394, and 630, for field shield electrode.
345 and 404, for nonuniform channel doping in IGFET. depletion mode.
347 through 354, and 507, for insulating substrate integrated circuit.
347 through 354, and 507, for single crystal insulating substrate.
347 through 354, and 507, for single crystal semiconductor layer on insulating substrate (SOI).
348 391, 392, and 402-407, for depletion mode Insulated Gate FET.
349 354, 372-376, 503, and 547, for controlling, reducing, etc. parasitics.
350 511, 512, 525, and 555-562, for lateral bipolar transistor in integrated circuit.
354 through 374, 395-399, 501, and 506-527, for dielectric isolation.
355 through 363, for gate insulator breakdown protection in IGFET integrated circuit.
360 and 367, for insulated gate device (controlling pn junction breakdown).
361 362, and 497-499, for punch-device.
366 for overlap of plural gate electrodes in IGFET.
368 through 401, for PN junction isolation in MOSFET integrated circuit.
374 394-398, 626, 631-651, and 758-760, for insulating/passivating coating.
374 396-398, 510-521, 647, and 648, for groove (dielectric isolation means).
377 382-385, 388, 412, 413, 454-458, 486, 518, 554, 576, 588, 747, 748, 754-757, 761, 763-764, and 768-770, for refractory electrode material.
377 382-384, 388, 412, 413, 454-456, 485, 486, 576, 587, 751, 754-757, and 768-770, for silicide.
379 through 381, and 903-904, for static RAM arrangement.
379 through 381, 516, 528-543, 903, 904, 919, and 924, for passive components in integrated circuits.
382 through 384, 576, 757, 768, and 769, for metal or silicide of platinum group metal, as ohmic contact.
383 388, 412, 485, 486, 763, 764, and 770, for pure or alloyed titanium.
388 407, 412, and 413, for metal or silicide of platinum group metal, as MOSFET gate.
390 and 391, for array of IGFETs.
390 and 391, for nonerasable (e.g., ROM).
390 and 391, for mask-programmed MOSFET ROM.
401 for nonuniform channel thickness in IGFET.
410 411, 639-641, 649, and 760, for silicon nitride.
411 and 760, for composite insulator material.
411 for oxynitride as gate insulator in IGFET, in general.
422 and 659, for magnetic field shielding
423 511, 512, 525, 526, 556, 557-562, 575, and 576, for lateral bipolar transistor structure.
423 for magnetic field sensing bipolar transistor.
426 and 469, for passivating means to reduce temperature sensitivity.
427 for magnetic field sensor in integrated circuit.
430 and 458, for light or radiation responsive PIN device, in general.
431 466, for light responsive or activated device generally.
437 for anti-reflection coating.
444 for matrix or array of light sensor elements overlying active switching elements in integrated circuit.
446 for matrix or array of light sensors with specific isolation means in integrated circuit.
449 through 457, for Schottky barrier.
453 through 455, 485, and 486, for metal or silicide of platinum group metal, as Schottky barrier material.
458 523, 538, and 656, for intrinsic material or region.
458 for PIN diode.
459 676, and 786, for bonding flag or pad
465 592, 599, 653, and 654, for configuration of junction geometry.
466 496, 571, 586, 594, 599, 600, and 618-628, for configuration of external portion of active device.
474 for bipolar transistor with Schottky barrier transistor as emitter-base or base-collector junction.
474 through 479, 512, 525, 555, 556, and 574-576, for integrated injection logic.
477 through 479, for bipolar transistor in integrated circuit with Schottky barrier diode.
479 and 570, for anti-saturation diode.
479 for baker clamp.
486 740, 751, and 767, for diffusion barrier.
491 and 492, for means to increase breakdown voltage in integrated circuit.
492 and 493, for RESURF device.
494 for reverse biased (electrical) pn junction guard region.
494 for reverse biased guard ring to prevent breakdown.
497 and 498, for punchthrough transistor.
504 for JFET isolation in integrated circuit (i.e., pinched-off region used for integrated circuit isolation).
509 through 521, 544-556, and 929, for isolated PN junction.
509 through 521, for PN junction isolation in integrated circuit combined with dielectric isolation.
511 512, 525, 555, 556, 569, and 574-576, for complementary bipolar transistor structure.
511 512, 525, 555, 556, 569, and 574-576, for complementary bipolar transistors.
511 512, 514, 515, 517, 518, 525, 526, 539-543, and 552-563, for bipolar transistors in integrated circuit.
511 512, 514, 517, 518, and 552-556, for bipolar transistors with pn junction isolation.
512 569, and 574-576, for bipolar transistor structure with common active region.
512 569, and 574-576, for complementary bipolar transistors with common active region.
512 555, 556, and 574-576, for logic device (superintegrated) using Integrated Injection Logic (I[supscrpt]2[end supscrpt]L).
514 and 515, for walled emitter bipolar transistor.
522 for air isolation of integrated circuit.
531 for inductance in integrated circuit.
532 through 535, for capacitance as passive component in non-FET I.C.
540 for dynamic isolation pocket bias (electrical).
541 for pinch resistor.
544 through 556, for PN junction isolation in integrated circuit in general.
545 for reduction of isolation junction capacitance.
546 for overvoltage protection means in pn junction isolated integrated circuit.
546 for reverse voltage polarity protection, in pn junction isolated integrated circuit.
549 for collector diffused type isolation.
559 lateral transistor formed along groove.
560 through 564, for multiple/plural collectors.
560 563, and 579-581, for plural emitters in bipolar transistor.
562 for logic device (superintegrated) using Current Hogging Logic (CHL).
565 through 593, for bipolar transistor structure, in general.
571 for groove resistor in Darlington bipolar device.
573 and 584, for housing or package for bipolar transistor devices.
592 for configuration of bipolar transistor base region.
602 for housing or package for voltage-variable capacitance device.
607 and 917, for plural dopants of same conductivity type.
610 for platinum (as deep level dopant).
620 for scribe line or region.
624 for prevention of skin effect, microwave device, by low resistance ohmic contact along mesa surface.
626 and 629-652, for passivation of semiconductor surface.
634 for passivating glass with ingredient to adjust softening or melting temperature.
639 and 649, for oxynitride as passivating insulating layer.
642 643, and 759, for organic insulating material or layer.
643 759, and 788, for polyamide.
643 759, and 792, for polyimide.
653 654, for shaped PN junction.
655 for reverse doping concentration gradient profile.
656 for PIN device in general.
657 for stepped profile.
657 for stepped dopant concentration profile.
660 for housing or package for radiation shielded device.
662 and 664, for transmission line lead.
663 for superconductive contact or lead on integrated circuit.
669 670, 673, 674, 676, 688, 689, 692-697, 728, 735-739, 752, 758, 773-776, and 780-786, for shaped contact, electrode, etc.
669 for lead frame having stress relief.
676 for die bonding flag.
676 for lead frame-type mount for chip.
678 through 733, for housing or package, generally.
679 and 922, for smart card (e.g., "credit card" integrated circuit package).
686 for stacked housings.
700 701, and 703-707, for ceramic housing or package material.
705 for high thermal conductivity ceramic for package.
711 for metal housing with mount for chip.
713 for cooling of housing or contents for integrated circuit.
714 through 716, for liquid coolant.
719 for press contact of heat sink and semiconductor.
720 for high thermal conductivity insert in heat sink.
731 for mount for housing.
732 for flanged type mount for housing.
735 through 739, 746, 758-760, 773-776, 780-781, 786, 920, 923, 926, for configuration of electrode, etc.
738 780, and 781, for ball-shaped leads, contacts or bonds.
740 for prevention of spiking of contact metal.
741 through 745, and 751, for gold (deep level dopant as contact or electrode).
742 and 743, for dopant/impurity conductivity type in electrical contact material.
746 for composite electrode material.
746 for electrode material.
749 for electrode transparent to light.
751 767, and 915, for titanium nitride.
758 through 760, for multiple metallization layers separated by insulating layer on integrated circuit.
760 for oxynitride between metal levels in integrated circuit.
764 765, and 768-771, for alloy of materials forming electrical contacts.
767 for electromigration prevention or reduction.
777 for chip on chip mount for chip.
778 for flip chip mount for chip.
779 and 780-784, for die or lead bond.
782 and 783, for die bond.
900 for MOSFET type gate sidewall insulating spacer.
901 for MOSFET substrate bias (electrical).
901 for MOSFET substrate bias.
902 for FET with metal source region.
903 and 904, for configuration of FETs for Static Memory Cell (SRAM).
905 through 908, for configuration of Dynamic Memory (DRAM).
905 for trench shared by plural DRAM cells.
906 Electrode use for accessing capacitance, in DRAM.
910 for array of diodes.
911 for vidicon array (cross-reference collection).
915 for titanium nitride.
919 for parallel electrical connections to average out manufacturing variations.
920 for parallel electrical connections to reduce resistance.
922 for anti-tamper device.
922 for diode arrays.
922 for anti-tamper or inspection means for
923 for conductor aspect ratio.
925 for bridge rectifier module.
927 for shaped depletion layer.
930 for Peltier cooling (cross-reference collection).

REFERENCES TO OTHER CLASSES

SEE OR SEARCH CLASS:
29, Metal Working, 25.01 for process and apparatus for making barrier layer or semiconductor devices not elsewhere classified; subclass 25.35 for piezoelectric device making not elsewhere classified; subclasses 25.41+ for electric condenser making not elsewhere classified; subclasses 592.1+ for process of mechanical manufacture of electrical devices, not elsewhere classified; and subclasses 825+ for electrical conductor manufacturing processes, including subclass 827 regarding beam lead frames and beam leads. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D)
29, Metal Working, subclass 612 for making thermally variable resistors. (see G, Lines With Other Classes and Within This Class, above)
29, Metal Working, appropriate subclasses for manufacturing methods of beam lead frame or beam lead devices. (Class providing for subcombination subject matter used as component part of active solid-state electronic devices. See Lines with Other Clases and Within This Class, F, above)
40, Card, Picture, or Sign Exhibiting, subclass 544 for electroluminescent signs. (see B, Lines With Other Classes and Within This Class, above.)
62, Refrigeration, 3.2 for thermoelectric, e.g., Peltier effect cooling processes and apparatus. (see B, Lines With Other Classes and Within This Class, above.)
65, Glass Manufacturing, 138 for Electronic envelope header, terminal, or stem making means and subclass 155 for electronic device making involving fusion bonding. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D)
73, Measuring and Testing, subclass 31.06 for gas analysis semiconductor detector details; subclass 777 for semiconductor stress sensor structure; and subclass 754 for semiconductor type fluid pressure gauges. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
84, Music, subclass 676 and 678 for transistorized analog oscillator circuits. (see B, Lines With Other Classes and Within This Class, above.)
102, Ammunition and Explosives, subclass 202.4 for semiconductor voltage variable resistance shunts in devices used to prevent accidental fuse ignition. (see G, Lines With Other Classes and Within This Class, above)
102, Ammunition and Explosives, subclass 202.4 for semiconductor fuse shunts and subclass 220 for silicon controlled rectifier ignition or detonation switch devices. (see B, Lines With Other Classes and Within This Class, above.)
116, Signals and Indicators, digest 35 for electroluminescent dials. (see B, Lines With Other Classes and Within This Class, above.)
117, Single-Crystal, Oriented-Crystal, and Epitaxy Growth Processes; Non-Coating Apparatus Therefor, for processes and non-coating apparatus for growing therein-defined single-crystal of all types of materials, including those which may be suitable as or to produce an active solid-state device. Class 118 generally provides for coating apparatus, including single-crystal (e.g., epitaxy) coating means. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D)
118, Coating Apparatus, subclass 900 for semiconductor vapor doping. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D)
123, Internal-Combustion Engines, 650 for ignition systems with power supplies having diode and transistor features. (see B, Lines With Other Classes and Within This Class, above.)
134, Cleaning and Liquid Contact With Solids, subclass 1.2, 1.3, and 902 for semiconductor wafer cleaning. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D, above)
136, Batteries: Thermoelectric and Photoelectric, 203 for Peltier effect device; subclasses 200+ for batteries which generate electricity under the action of heat (thermoelectric); and subclasses 243+ for batteries which generate electricity under the action of light, such as photovoltaic batteries, some of these batteries utilize potential barrier layers. (class providing for active solid-state electronic devices structures with a specified use.)
148, Metal Treatment, 33 for PN type barrier layer stock material treatment and numerous digests concerning treatment of semiconductor materials, dopants, and active solid-state electronic devices. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See
Lines With Other Classes and Within This Class, D, above)
148, Metal Treatment, digest 171 for metal treatment involving varistors. (see G, Lines With Other Classes, above)
165, Heat Exchange, 80.2 and 104.33 for electrical device or component heat exchangers. (Class providing for subcombination subject matter used as component part of active solid-state electronic devices. See Lines with Other Clases and Within This Class, F, above)
178, Telegraphy, subclass 117 for coherer type AC systems. (see B, Lines With Other Classes and Within This Class, above.)
178, Telegraphy, subclass 117 for coherer type AC systems. (see G, Lines With Other Classes and Within This Class, above)
194, Check-Actuated Control Mechanisms, 216 for value accumulator having solid-state circuitry. (see B, Lines With Other Classes and Within This Class, above.)
174, Electricity: Conductors and Insulators, subclasses 15.1-16.3 for fluid cooling of electrical conductors or insulator; subclasses 52.1+ for housings with electric devices or mounting means; and subclasses 250-268 for printed circuit devices. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
204, Chemistry: Electrical and Wave Energy, 400 for active solid-state devices used in measuring and testing involving electrolytic analysis. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
204, Chemistry: Electrical and Wave Energy, subclass 192.25 for semiconductor coating, forming, or etching by sputtering. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D, above)
216, Etching a Substrate: Processes, subclass 16 for active solid state devices involved in an etching process. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D, above)
219, Electric Heating, subclass 501 for automatic regulation or control means for heating devices which include semiconductor, e.g., transistor, means. (see B, Lines With Other Classes and Within This Class, above.)
228, Metal Fusion Bonding, subclass 123 for processes of bonding metal to semiconductor-type material and subclasses
179+ for processes of bonding electrical device (e.g., semiconductor) joints. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D, above)
250, Radiant Energy, subclass 492.2 for irradiation of semiconductor devices. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D, above)
250, Radiant Energy, subclass 338.4 for infrared responsive semiconductor devices, subclasses 370.01-370.15 for invisible radiant energy responsive semiconductor devices; subclass 371 for invisible radiant energy responsive methods using semiconductor devices; subclass 492.2 for irradiation of semiconductor devices; subclasses 552 and 553 for photocell circuits and apparatus involving solid-state light sources; subclasses 211 for photocells including photosensitive junctions; and subclasses 208.1-208.6 for plural photosensitive elements, including arrays. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
264, Plastic and Nonmetallic Article Shaping or Treating: Processes, subclass 272.11 for electrical component encapsulating processes, including subclass 272.17 for encapsulating semiconductor or barrier layer device. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D, above)
252, Compositions, subclass 62.3 for barrier layer device compositions, e.g., N-material, P-material and, subclasses 500+ for electrically conductive or emissive compositions. (Class providing for materials used in active solid-state devices, Lines With Other Classes and Within This Class, C, above)
273, Amusement Devices: Games, digest 24 for luminescent devices. (see B, Lines With Other Classes, above.)
307, Electrical Transmission or Interconnection Systems, 401 for nonlinear reactor systems which typically employ active solid-state devices; subclass 91 for magnetic or electrostatic field shielding; and subclasses 109+ for systems involving capacitors.
310, Electrical Generator or Motor Structure, subclass 303 for energy conversion devices employing pn semiconductor junction devices, and digest 3 for Hall effect generators and converters. (see B, Lines With Other Classes and Within This Class, above.)
313, Electric Lamp and Discharge Devices, 498 for electric lamp and discharge devices having solid-state luminescent
materials, including nominally recited luminescent semiconductor type materials; subclasses 329 and 367+ for mosaic electrodes; subclasses 366+ for semiconductor depletion layer type image pickup tubes; subclass 463 for electroluminescent cathoderay tube screens; subclasses 346 and 346 for photoemissive cathodes; and subclass 504 for solid-state organic phosphor material luminescent devices. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
315, Electric Lamp and Discharge Devices: Systems, subclass 12.1 for secondary emissive stage in a cathoderay tube; subclass 407 for a deflection coil circuit including a diode; subclass 408 for deflection coil circuits including a solid-state switch; and digest 7 for starting and control circuits using transistors. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
323, Electricity: Power Supply or Regulation Systems, 229 for power supply or regulation systems using a diode in shunt with a source or load; subclasses 237+, 254, 257, 258, 263, 265+, and 292 for output level devices employing three or more terminal semiconductor devices; subclass 300 for input level devices or systems employing three or more terminal semiconductor devices; subclasses 311+ for self-regulating systems employing three or more terminal semiconductor devices; subclasses 325+, 339, 343, and 349+ for external or operator controlled systems employing three or more terminal semiconductor devices; subclass 360 for superconductor type transformers or inductors; digest 902 for device with optical coupling to a semiconductor; and digest 907 for temperature compensation of a semiconductor. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
318, Electricity: Motive Power Systems, subclass 681 for positional servomechanisms using solid-state servo amplifiers. (see B, Lines With Other Classes and Within This Class, above.)
315, Electric Lamp and Discharge Devices: Systems, subclass 311 for variable impedance device in automatic regulator in supply circuit of an electric lamp or discharge device. (see G, Lines With Other Classes and Within This Class, above)
318, Electricity: Motive Power Systems, subclass 662 for variable capacitor type positional servo systems and subclasses 788 and 792 for variable temperature impedance (e.g., resistor) elements in induction motor systems. (see G, Lines With Other Classes and Within This Class, above)
320, Electricity: Battery or Capacitor Charging or Discharging, appropriate subclass for an active solid-state device included in a charging or discharging circuit for a battery or capacitor. (see B, Lines With Other Classes,
above.)
322, Electricity: Single Generator Systems, digest 5 for Hall effect elements. (see B, Lines With Other Classes and Within This Class, above.)
323, Electricity: Power Supply or Regulation Systems, subclass 298 for output level responsive devices including a variable resistor. (see G, Lines With Other Classes and Within This Class, above)
324, Electricity: Measuring and Testing, 765 for diode, SCR and transistor testing and subclasses 244+ for magnetometers, many of which employ active solid-state devices, e.g., subclasses 248 (thin film), 251 (Hall plate) and 252 (semiconductor type solid-state or magneto resistive). (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, appropriate subclasses for miscellaneous nonlinear circuits utilizing an active device. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, 185 for a stable state circuit utilizing an electron tube and a transistor and subclasses 568+ for a miscellaneous negative resistance circuit. (see B, Lines With Other Classes and Within This Class, above.)
329, Demodulators, subclass 370 for diode demodulators and subclass 371 for coherer type demodulators. (see B, Lines With Other Classes and Within This Class, above.)
329, Demodulators, subclass 370 for diode demodulators and subclass 371 for coherer type demodulators. (see G, Lines With Other Classes and Within This Class, above)
330, Amplifiers, subclass 145 for diode type variable impedances for signal channel controlled by a separate control path and subclasses 282+ for semiconductor amplifier devices with gain control means and feedback means acting as a variable impedance.
330, Amplifiers, subclass 4.9 for semiconductor type parametric amplifiers; subclass 183 for DC interstage coupling with as nonlinear device; and subclasses 250+ for semiconductor amplifying devices. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
331, Oscillators, subclass 51 for semiconductor type cascade or tandem connected oscillators and subclasses 107-117 for solid-state active element oscillators. (class employing
active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
331, Oscillators, 36 for AFC devices using particular frequency control means, including reactance devices (e.g., variable capacitors) and subclass 177 for voltage sensitive capacitor type frequency adjusting means. (see G, Lines With Other Classes and Within This Class, above)
332, Modulators, subclass 105, 116, 135+, 146, 152, 168, and 178 for modulators with discrete semiconductor devices (subclass 136 includes varactors). (see B, Lines With Other Classes and Within This Class, above.)
332, Modulators, subclass 105, 116, 135+, 146, 152, 168, and 178 for modulators with discrete semiconductor devices (subclass 136 includes varactors). (see G, Lines With Other Classes and Within This Class, above)
333, Wave Transmission Lines and Networks, subclass 263 for variable impedance devices connected in circuit with a long line element or component. (see G, Lines With Other Classes and Within This Class, above)
333, Wave Transmission Lines and NetWorks, subclass 103 and 104 for branched circuits with switching means having semiconductor operating means; subclass 165 for frequency or time domain filters using charge transfer devices; subclasses 216 and 217 for negative impedance devices; subclass 247 for semiconductor mounts for strip type long line elements; and subclass 99 for super conductive devices. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
334, Tuners, subclass 66 and 69 for series tuned circuits with variable impedance elements.
334, Tuners, subclass 15 for semiconductor reactance tuning circuits. (see B, Lines With Other Classes and Within This Class, above.)
338, Electrical Resistors, subclass 1 for coherer type resistors, subclass 22 for semiconductor type thermistors, and subclass 32 for magnetic field responsive devices, including Hall effect types and super conductive types. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
338, Electrical Resistors, subclass 1 for coherer type resistors; subclass 22 for semiconductor type thermistors; and subclass 32 for magnetic field responsive devices, including Hall effect types and superconductive types. (see G, Lines With Other Classes and Within This Class, above)
343, Communications: Radio Wave Antennas, subclass 745 for antennas with variable reactance tuning; subclass 750 for
adjustable lumped reactance antenna tuning; and subclass 861 for adjustable impedance matching network leadins. (see G, Lines With Other Classes and Within This Class, above)
340, Communications: Electrical, subclass 598 for barrier layer thermal sensors in condition responsive device; subclass 815.03 for a visual indicator using a light emitting diode; and subclasses 825.79-825.96 for selective systems comprising matrix elements, e.g., light emitting diodes. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
341, Coded Data Generation or Conversion, 133 for analog-to-digital conversion with particular solid-state devices; subclass 150 for digital to analog conversion using charge coupled devices or switched capacitances; and subclass 172 for analog to digital conversion using charge transfer devices. (see B, Lines With Other Classes and Within This Class, above.)
345, Computer Graphics Processing, Operator Interface Processing, and Selective Visual Display Systems, 30 for selective visual display systems which may employ active solid-state device light sources, including subclasses 44 and 82 for visual display systems having solid-state light emitters. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
348, Television, 272 and 294+ for solid-state image sensors in television cameras and subclasses 800+ for electroluminescent video display with solid-state scanned matrix. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
358, Facsimile and Static Presentation Processing, subclass 482 and 483 solid-state picture generators, including charge coupled devices. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
359, Optics: Systems (Including Communication) and Elements, subclass 248 for semiconductor polarization type light modulators and subclasses 321+ for modulators having significant chemical composition or structure. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
361, Electricity: Electrical Systems and Devices, subclass 2 for solid-state switch type arc suppressors; subclasses 98, 100, and 101 for current fault responsive sensors involving semiconductor active solid-state devices; subclasses 196+ for semiconductor time delay devices; subclass 205 for threshold devices including SCR thyratrons; subclasses 275.1+ for
electrical, e.g., fuse element for electrolytic capacitors; subclasses 277+ for variable capacitor not involving active solid-state devices; subclasses 525 for solid electrolytic capacitors with significant semiconductor; subclasses 679+ for cooling devices, housings, supports, electrical contacts, etc., for diverse electrical components; subclass 421 for lead frames; and subclasses 523+ for solid electrolytic capacitors. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
361, Electricity: Electrical Systems and Devices, subclass 188 for variable impedance condition responsive devices for relay or solenoid safety or protection; and subclasses 277+ for variable electrostatic capacitors. (see G, Lines With Other Classes and Within This Class, above)
361, Electricity: Electrical Systems and Devices, subclass 421 for lead frames. (Class providing for subcombination subject matter used as component part of active solid-state electronic devices. See Lines with Other Clases and Within This Class, F, above)
362, Illumination, subclass 84 for light source or light source support and luminescent material and subclass 800 (cross-reference art collection) for light emitting diode light sources. (see B, Lines With Other Classes and Within This Class, above.)
363, Electric Power Conversion Systems, 10 for combined phase and frequency conversion using a semiconductor device converter, and subclasses 13-147 for current conversion devices many of which explicitly call for semiconductor active solid-state devices, and subclasses 159-163 for frequency conversion using semiconductor type devices. (see B, Lines With Other Classes and Within This Class, above.)
364, Electrical Computers and Data Processing Systems, subclass 490 and 491 for design and analysis of integrated circuits. (see B, Lines With Other Classes and Within This Class, above.)
365, Static Information Storage and Retrieval, 52 for hardware, including shields, for storage elements; subclass 71 for negative resistance; and subclass 72 for transistor or diode interconnection arrangement; subclass 96 for fusible link storage elements; subclasses 103-105 for semiconductive semipermanent read only systems; subclasses 106+ for systems involving radiant energy, including subclasses 109-115 for photoconductive, electroluminescent, amorphous, semiconductive and diode devices; subclasses 129+ for systems using a particular element, including subclasses 154-188 for systems using particular elements including active solid-state devices; subclasses 185.01+ for floating gate memory storage (e.g., flash memory); and subclasses 208 and 212 for semiconductive differential (e.g., thermal) noise suppression means in read/write circuits. (class employing
active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
367, Communications, Electrical: Acoustic Wave Systems and Devices, 140 for signal transducers which may be active solid-state devices, and including support structures, diaphragm, and pressure compensation means. (see B, Lines With Other Classes and Within This Class, above.)
368, Horology: Time Measuring Systems or Devices, subclass 83 for solid body light emitters, e.g., diodes; subclasses 86 and 87 for transistorized pulse transforming means; subclasses 56+ for solid-state oscillating time base circuits; and subclasses 239+ for optical display devices, including subclass 241 for solid-state, e.g., LED light emitting displays. (see B, Lines With Other Classes and Within This Class, above.)
369, Dynamic Information Storage or Retrieval, subclass 44.12 for optical servo systems having solid-state optical elements; subclasses 121+ for light sources, including solid-state light source; subclass 145 for semiconductive information handling transducers. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
372, Coherent Light Generator, subclasses 43-50 for semiconductor layers and subclass 75 for semiconductor optical laser pump devices. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
374, Thermal Measuring and Testing, subclass 178 for barrier layer (e.g., semiconductor junction) heat sensors and subclasses 183+ for current modifying sensors. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
377, Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems, subclasses 57-63 for charge transfer device systems; subclass 74 for input circuits involving field-effect transistors; subclass 79 and 117 for transfer means including a field effect transistor; and subclass 93 for superconductive elements. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
378, X-Ray or Gamma Ray Systems or Devices, subclass 104 for X-ray source power supplies with specified rectifier. (see B, Lines With Other Classes and Within This Class, above.)
379, Telephonic Communications, subclass 294 for semiconductor line finders. (see B, Lines With Other Classes, above.)
381, Electrical Audio Signal Processing Systems and Devices, subclass 100 for crossover filters with active devices and subclass 175 for semiconductor junction microphones. (see B, Lines With Other Classes and Within This Class, above.)
388, Electricity: Motor Control Systems, subclasses 917-920 for thyristor or SCR devices or control circuit elements and subclass 926 for a specific feedback control or device which controls a solid-state device in a motor circuit.
388, Electricity: Motor Control Systems, subclass 807 for variable impedance type field control circuits and subclasses 855+ for selectable or variable impedance armature control devices. (see G, Lines With Other Classes and Within This Class, above)
427, Coating Processes, 58, especially 62, 63, 66, 74-76, 79-81, 96-99, 100, and 101-103 for electrical product produced by coating processes. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D, above)
428, Stock Material or Miscellaneous Articles, subclass 620 for composite metallic stock having a semiconductor component, subclasses 690 and 691 for fluorescent, phosphorescent or luminescent inorganic layer composites; subclasses 917 for electroluminescent material; and subclasses 928-931 for materials with special properties, including magnetic properties, electrical contact features and superconductivity. (Class providing for materials used in active solid-state devices, Lines With Other Classes and Within This Class, C, above)
430, Radiation Imagery Chemistry: Process, Composition, or Product Thereof, subclasses 56-96 for radiation sensitive compositions or products; subclass 139 for luminescent imaging process, composition or product; and subclass 900 for donor-acceptor complex photoconductors. (Class providing for materials used in active solid-state devices, Lines With Other Classes and Within This Class, C, above)
430, Radiation Imagery Chemistry: Process, Composition, or Product Thereof, subclasses 56-96 for radiation sensitive compositions or products; subclass 139 for luminescent imaging process, composition or product; and subclass 900 for donor-acceptor complex photoconductors. (class providing for methods of making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D, above)
438, Semiconductor Device Manufacturing: Process, for (a) combined operations (steps) for producing a semiconductor substrate having a junction, usually between p-type and n-type material or (b) a unit operation involving semiconductor material, not elsewhere provided; see the search notes therein. (class providing for methods of
making, cleaning, coating, etc., active solid-state devices, See Lines With Other Classes and Within This Class, D, above)
439, Electrical Connectors, appropriate subclasses for features related or analogous to electrical contact or housing features of active solid-state devices, e.g., 271 for sealing elements, or subclasses 449+ for stress relief means for conductor to terminal joint. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes and Within This Class, A, above)
455, Telecommunications, subclass 253.1 for semiconductor gain, level or volume control; subclass 291 for receivers having a wave collector with coupling to a stage of the receiver using an active device, and subclass 333 for transistorized or integrated circuit type frequency conversion structure or circuitry. (see B, Lines With Other Classes and Within This Class, above.)
455, Telecommunications, subclass 261 and 262 for variable reactance, e.g., variable capacitance type automatic local oscillator control devices. (see G, Lines With Other Classes and Within This Class, above)
505, Superconductor Technology: Apparatus, Material, Process, 150 for high temperature (T[subscrpt]c[end subscrpt] > 30 K) superconducting devices, and particularly subclasses 161 and 162 for bolometers or SQUIDs, subclasses 190+ for Josephson junctions, per se, and subclasses 191+ for other thin film solid-state devices; and pertinent cross-reference art collections, including subclasses 831+, for static information storage and retrieval system or device; subclasses 857+ for nonlinear solid-state device, system, or circuit; subclasses 873+ for active solid-state devices; subclass 883 for housing and mounting assemblies with plural diverse electrical components; subclasses 884+ for conductors; and subclasses 900+ for heat exchangers. (see B, Lines With Other Classes and Within This Class, above.)
505, Superconductor Technology: Apparatus, Material, Process, 150 for high temperature (T[subscrpt]c[end subscrpt] > 30 K) superconducting devices, and particularly subclasses 161 and 162 for bolometers or SQUIDs, subclasses 190+ for Josephson junctions, per se, and subclasses 191+ for other thin film solid-state devices; and pertinent cross-reference art collections, including subclasses 831+, for static information storage and retrieval system or device; subclasses 857+ for nonlinear solid-state device, system, or circuit; subclasses 873+ for active solid-state devices; subclass 883 for housing and mounting assemblies with plural diverse electrical components; subclasses 884+ for conductors; and subclasses 900+ for heat exchangers. (Class providing for materials used in active solid-state devices, Lines With Other Classes and Within This Class, C, above)
600, Surgery, 486 and 505 for active solid-state devices inserted inside a body and used for measuring and testing. (class employing active solid-state devices in electronic circuits. See Lines With Other Classes, A, above)
708, Electrical Computers: Arithmetic Processing and Calculating, subclass 190 for integrated circuit type digital computers.
902, Electronic Funds Transfer, subclass 26 for identification, means with a semiconductor chip, e.g., a smart card. (see B, Lines With Other Classes and Within This Class, above.)
D10, Measuring, Testing or Signalling Instruments, subclass 77 for transistor testers. (see B, Lines With Other Classes and Within This Class, above.)
D13, Equipment for Production, Distribution or Transformation of Energy, appropriate subclass for semiconductor, transistor or integrated circuit energy conversion or transformation. (see B, Lines With Other Classes and Within This Class, above.)

GLOSSARY:
ACCEPTOR IMPURITY
An atom or ion different from or foreign to, but present in, a semiconductor material and which has insufficient valence electrons to complete the normal bonding arrangement in the semiconductor crystal structure. An acceptor impurity accepts an electron from an adjacent atom to create a hole. Acceptor impurities are also referred to as p-type impurities. Common acceptor impurities in silicon or germanium are boron, gallium, and indium.
ACTINIDES
Ac, Th, Pa, U, Np, Pu, Am, Cm, Bk, Cf, E, Fm, Mv, No, Lw.
ALKALI METALS
Li, Na, K, Rb, Cs, Fr.
ALKALINE-EARTH METALS
Ca, Sr, Ba, Ra.
ACTIVE solid-state ELECTRONIC DEVICE
An electronic device or component that is made up primarily of solid materials, usually semiconductors, which operates by the movement of charge carriers - electrons or holes - which undergo energy level changes within the material and can modify an input voltage to achieve rectification, amplification, or switching action. Active solid-state
electronic devices include diodes, transistors, thyristors, etc., but exclude pure resistors, capacitors, inductors, or combinations solely thereof. The latter class of devices is characterized as passive.
ALLOY JUNCTION
A fused junction produced by combining one or more elemental impurity metals with a semiconductor. Typical alloyed junctions include indium- germanium and aluminum-silicon.
ALLOY TRANSISTOR
A transistor in which the emitter-base and collector-base junctions are alloy junctions.
AVALANCHE BREAKDOWN
A sudden change from high dynamic electrical resistance to very low dynamic resistance in a reverse biased semiconductor device, e.g., a reverse biased junction between p-type and n-type semiconductor materials, wherein current carriers are created by electrons or holes which have gained sufficient speed to dislodge valence electrons. Avalanche breakdown can cause structural damage to a semiconductor device.
AXIAL LEAD
A wire lead coming from the end of and along the axis of a resistor, capacitor, or other component.
BACK BONDED
The bonding of active chips to a substrate using the back of the chip opposite the side containing active solid-state devices.
BALL BOND
A bond formed by a round, ball-shaped lead on a semiconductor device.
BALLISTIC TRANSPORT DEVICE
An active solid-state electronic device in which an active layer is present through which carriers* pass, wherein the active layer is thinner than the mean free path of the carriers* in the material in that layer, so that carriers* can pass through the layer without scattering. Carriers* are typically injected into the ballistic transport layer as "hot" carriers*, having an energy, in the case of electrons, substantially greater than the minimum of the conduction band*, or in the case of holes, substantially lower than the maximum of the valence band. Ballistic electron injectors include heterojunctions, tunnel barriers, and punchthrough (e.g., planar doped or camel) barriers.
BAND GAP
The difference between the energy levels of electrons bound to their nuclei (valence electrons) and the energy levels that allow electrons to migrate freely (conduction electrons). The band gap depends on the particular semiconductor involved.
BARRIER REGION OR LAYER
A region which extends on both sides of a semiconductor junction in which all carriers are swept away from the junction region. The region is depleted of carriers. This is also referred to as a depletion region.
BARRITT DIODE
Barrier injection transit time diode. A bipolar or device in which a type of breakdown known as punchthrough occurs and wherein the punchthrough structure device is operable at microwave frequencies. In bipolar transistors a direct current path is formed from emitter to collector due to the formation of a depletion region throughout the base region and charge carriers from the emitter punch through to the collector. Carriers flowing from the emitter to the collector take a controlled time to pass through the depletion layer, leading to a controlled delay in current after a voltage is applied, and effective negative impedance.
BASE REGION
The region between the emitter and collector of a bipolar transistor into which minority carriers are injected by the emitter.
BASE CURRENT
The electrical current that flows in the base terminal of a bipolar transistor.
BEAM LEADS
Flat, metallic leads which extend beyond the edges of a chip component like wooden beams extend from a roof overhang. Beam leads are used to interconnect a component to film circuitry.
BIAS
A direct current or voltage applied to an active solid-state device that establishes certain operating characteristics of the device.
BI-FET
An active solid-state electronic device that contains both
bipolar and field effect transistors.
BILATERAL
A characteristic of an active solid-state electronic device that permits it to support current flow in opposite directions.
BINARY COMPOUND
A substance that always contains the same two elements in a fixed atomic ratio.
BIPOLAR
An active solid-state electronic device in which both positive and negative current carriers are used to support current flow.
BIPOLAR TRANSISTOR
An active solid-state electronic device with a base electrode and two or more junction electrodes in which both positive and negative current carriers are used to support current flow.
BLOCH WAVELENGTH
The effective wavelength of electrons in a semiconductor crystal, sometimes referred to as a wave packet or wave function. It can be an order of magnitude larger than the de broglie wavelength of electrons having the same energy.
BONDING AREA
The area, defined by the extent of a metallization land or the top surface of a terminal, to which a lead is or is to be bonded.
BONDING PAD
A metallized area to which an electrical connection is to be made. It is also called a bonding island or a controlled collapse chip connection.
BONDING WIRE
Fine wire for making electrical connections in hybrid circuits between various bonding pads on the semiconductor device substrate and device terminals or substrate lands.
BREAKDOWN
A sudden change from high dynamic electrical resistance to a very low dynamic resistance in a reverse biased semiconductor device, e.g., a reverse biased junction between p-type and n-type semiconductor materials, wherein reverse current
increases rapidly for a small increase in reverse applied voltage, and the device behaves as if it had negative electrical resistance.
BREAKDOWN POINT/VOLTAGE
The voltage value at which breakdown occurs.
BREAKOVER
The start of current flow in a silicon controlled rectifier.
BUCKET BRIGADE DEVICE
A charge transfer device in which only a portion of the charge carriers (electrons or holes) at each storage site are transferred to the next storage site.
BUMP CONTACT
A term used to describe, typically, solder bumps on a chip or substrate which are found on only one side of the chip or substrate as, for example, on a flip-chip.
BULK-CHANNEL CCD
A charge coupled device in which charge is stored and transferred below the surface of the device.
BULK-EFFECT DEVICE
An active solid-state device made up of a semiconductor material whose electrical characteristics and electronic properties are exhibited throughout the entire body of the material, rather than in just a localized region thereof, e.g., the surface.
BURIED CHANNEL CCD
See BULK-CHANNEL CCD.
CB JUNCTION
The collector-base junction of a bipolar transistor.
CAPACITOR
A component used in electrical and electronic circuits which stores a charge of electricity, usually for very brief periods of time, with the ability to rapidly charge and discharge. A capacitor is usually considered a passive component since it does not rectify, amplify, or switch and because charge carriers do not undergo energy level changes therein, although some active solid-state devices function as voltage variable capacitors.
CARRIER
A mobile free electron or hole.
CARRIER CONCENTRATION
The number of electrical charge carriers in a given volume, usually a cubic centimeter, of semiconductor material.
CELL
An individual integrated circuit element located on a large, or master chip of, semiconductor material.
CHANNEL
A path for conducting current between a source and drain of a field effect transistor.
CHANNEL LENGTH EFFECTS
Operating characteristics of FETs which depend on the length (distance between source and drain) of the channel regions. Such effects include switching speed change and threshold voltage change with channel length change.
CHANNEL WIDTH EFFECTS
Operating characteristics of FETs which depend on the width (horizontal distance perpendicular to channel length and parallel to upper surface of device) of the channel. Such effects include conductance and threshold voltage change with channel width change.
CHANNEL STOP
Means for limiting channel formation in a semiconductor device by surrounding the affected area with a ring of highly doped, low resistivity semiconductor material. In a field effect transistor, it is a region of highly doped material of the same type as the lightly doped substrate used to prevent leakage paths along the chip surface from developing. Also referred to as "chanstop."
CHANNEL PINCH-OFF REGION
The location in a current channel portion of a field effect transistor (FET) where the current is reduced to a minimum value due to its diameter being reduced to a minimum.
CHARACTERISTIC CURVE
A graph showing the relationship between two or more changing parameters, e.g., current and voltage of an electronic device.
CHARGE CARRIER
A mobile conduction electron or hole in a semiconductor.
CHARGE CONFINEMENT
Restriction of electrical charge carriers, e.g., electrons or holes, to specified locations, e.g., by quantum wells, gate electrode potentials, etc.
CHARGE-COUPLED DEVICE
A charge transfer device in which all carriers (electrons or holes) are transferred from one storage site to the next upon application of a shifting voltage.
CHARGE INJECTION DEVICE
A field effect device in which storage sites for packets of electric charge are induced at or below the surface of an active solid-state device by an electric field applied to the device and wherein carrier potential energy per unit charge minima are established at a given storage site and such charge packets are injected into the device substrate or into a data bus. This type device differs from a charge transfer device in that, in the latter, charge is transferred to adjacent charge storage sites in a serial manner, whereas, in a charge injection device, the charge is injected in a non-serial manner to the device substrate or to a data bus.
CHARGE TRANSFER DEVICE
A semiconductor device in which discrete packets of electrical charge are transferred from one location to another. Examples of charge transfer devices include charge-coupled devices (CCDs) and bucket-brigade devices (BBDs).
CHIP
A single crystal substrate of semiconductor material on which one or more active or passive solid-state electronic devices are formed. A chip may contain an integrated circuit. A chip is not normally ready for use until packaged and provided with external connectors.
CHIP CARRIER
A package with terminals, for solid-state electronic devices, including chips which facilitates handling of the chip during assembly of the chip to other electronic elements.
CHIP COMPONENT
A circuit element (active or passive) for use in microelectronics. Besides integrated circuits, the term includes diodes, transistors, resistors, and capacitors.
CIRCUIT
A number of devices interconnected in a one or more closed paths to perform a desired electrical or electronic function.
CLADDING BARRIER
A higher band gap material which encases a lower band gap material that defines the walls of a quantum well.
CMOS
See COMPLEMENTARY METAL OXIDE SEMICONDUCTOR.
COHERENCE LENGTH
The typical distance an electron can travel before it is scattered (e.g., by a phonon, a defect, or an impurity).
COHERER
A term which encompasses both active and passive type devices, the passive type being a resistor whose resistance decreases when subjected to a high frequency signal, and the active type being a rectifier which is made up of active solid-state particles which conduct and rectify current when connected into a cohesive element but which loses that characteristic when the particles are separated (e.g., by shaking a container in which the particles are located).
COLLECTOR
That end region of a bipolar transistor which forms one of the main current regions and which is reverse biased in operation with respect to the base region.
COLLECTOR CURRENT
The current which flows through the terminal of the collector region of a bipolar transistor.
COLLECTOR DIFFUSION ISOLATION (CDI)
An electrical isolation technology used for bipolar devices which employs an epitaxial layer, which forms transistor base regions, laid on a substrate of the same conductivity type (p or n) as the epitaxial layer, with an opposite conductivity type region, more heavily doped than the epitaxial base layer and located between the layer and the substrate, forming the collector and isolating the transistor from the substrate.
COMMON-BASE CONFIGURATION
A bipolar transistor in which the base region is common to both the input and output circuit. This is also known as a grounded-base bipolar transistor circuit.
COMMON-COLLECTOR CONFIGURATION
A bipolar transistor in which the collector region is common to both the input and output circuit. It is also known as an emitter-follower bipolar transistor circuit.
COMMON-DRAIN CONFIGURATION
A unipolar transistor in which the drain region is common to both the input and output circuit.
COMMON-EMITTER CONFIGURATION
A bipolar transistor in which the emitter region is common to both the input and output circuit. It is also known as a grounded-emitter bipolar transistor circuit.
COMMON- or GATE-CONFIGURATION
A unipolar transistor in which the gate region is common to both input and output circuits.
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS)
Both n-type and p-type metal oxide semiconductor devices, e.g., transistors, formed on the same substrate.
COMPONENT
An electronic device - active or passive - which has distinct electrical characteristics and has terminals for connection to other components to form a circuit.
COMPOUND
A homogeneous material which has definite proportions of chemically combined atoms or ions.
CONCENTRATION GRADIENT
A difference in dopant concentration (p- or n-type) from one position to another in a semiconductor.
CONDUCTION BAND
A partially filled energy band in which electrons can move freely, permitting a material to carry electric current where electrons are the current carriers.
CONDUCTION ELECTRONS
In a conductor or n-type semiconductor, outer shell electrons that are bound so loosely that they can move freely in the conduction band of a solid material under the influence of an electric field.
CONDUCTIVITY
The ability of a material to conduct electric current. Its converse is resistivity.
CONDUCTOR
A material which offers comparatively little resistance to the flow of current.
CONDUCTOR SPACING
The distance between adjacent edges (not centerline to centerline) of isolated conductive patterns in a conductor layer.
CONNECTOR AREA
That portion of metallized conductors used for providing external electrical connections from a component to a chip or other component.
CONTACT
The parts of a conductor designed to touch or be touched by other such parts of an electrical conductor to carry current to or from the conductor.
CONTACT WINDOW
An opening in an insulating layer to expose an underlying conductor to permit electrical contact thereto. It is also called a via hole.
COVALENT BONDING
The sharing of electrons by atoms in which each atom contributes one of a pair of electrons shared by another atom and forming a bond between those two atoms.
CRYOSAR
An active solid-state device which operates at cryogenic temperatures, i.e., at temperatures at or below 77 degrees Kelvin, by avalanche breakdown caused by impact ionization of device impurities.
CRYSTAL
A solid substance whose atoms are arranged with periodic geometric regularity, called a lattice.
CRYSTAL DEFECT
Any nonuniformity in a crystal lattice. There are four categories of crystal defects: (1) point defects, (2) line defects, (3) area defects, and (4) volume defects. Point defects include any foreign atom at a regular lattice site
(substitutional site) or between lattice sites (interstitial site), anti-site defects in compound semiconductors, e.g., Ga in As or As in Ga, missing lattice atoms, and host atoms located between lattice sites and adjacent to a vacant site (Frenkel defects). Line defects, also called edge dislocations, include extra planes of atoms in a lattice. Area defects include twins or twinning (a change in crystal orientation across a lattice) and grain boundaries (a transition between crystals having no particular positional orientation to one another. Volume defects include precipitates of impurity or dopant atoms caused by volume mismatch between a host lattice and precipitates.
CUTOFF
A minimum value of voltage or current applied to an active device which stops the device from operating in a particular manner.
DE BROGLIE WAVELENGTH
The wavelength of a particle, based on L.V. de Broglie's theory that particles exhibit wavelike characteristics.
DEEP DEPLETION
The condition in which a depletion layer formed in a MOS active device due to voltage applied to the gate electrode of the device, is deeper than the maximum depth at which inversion would normally be expected to occur at room temperature in a semiconductor device at the surface closest to the gate electrode, without formation of an inversion layer.
DEEP GROOVE ISOLATION
Electrical isolation of adjacent devices in a single monolithic semiconductor chip by grooves extending deeply into and below the surface of the chip between the devices.
DEEP-LEVEL CENTERS
Energy levels that can act as traps located in the forbidden band of a semiconductor material that are not near the conduction or valence band edges.
DEGENERATION
Doping of a semiconductor to such an extent that the Fermi level lies within the conduction band (N+ semiconductor) or within the valence band (P+ semiconductor). Also, in circuit applications, negative feedback between two or more active solid-state devices.
DEPLETION LAYER
See DEPLETION REGION.
DEPLETION MODE
The operation of a field-effect transistor having appreciable channel conductivity for zero gate- source voltage and whose channel conductivity may be increased or decreased according to the polarity of the applied gate-source voltage, by changing the gate-to-source voltage from zero to a finite value, resulting in a decrease in the magnitude of the drain current.
DEPLETION REGION
The region extending on both sides of a reverse biased semiconductor junction in which free carriers are removed from the vicinity of the junction. It is also called a space charge region, a barrier region, or an intrinsic semiconductor region.
DEVICE (ACTIVE)
The physical realization of an individual electrical element in a physically independent body which cannot be further divided without destroying its stated function. Examples are transistors, pnpn structures, and tunnel diodes.
DIE
A tiny piece of semiconductor material, separated from a semiconductor slice, on which one or more active electronic components are formed. Sometimes called a chip.
DIE BOND
Attachment of a semiconductor chip to a substrate or chip carrier or package, usually with an epoxy, eutectic, or solder alloy.
DIFFUSED JUNCTION
A junction between two different conductivity regions within a semiconductor and which is formed by diffusion of appropriate impurity atoms into the material.
DIFFUSED TRANSISTOR
A transistor in which the emitter and collector junctions are formed by diffusion of dopant atoms into the semiconductor material.
DIFFUSION
(1) The movement of carriers from a region of concentration to one of lower concentration; (2) a process of adding impurities to a semiconductor material to change its electrical characteristics.
DIFFUSION BARRIER
An obstacle to the diffusion of charge carriers in an active solid-state device.
DIFFUSION CURRENT
Current caused by charge carriers diffusing from a volume of high carrier concentration to a volume of lower carrier concentration in a solid-state material.
DIFFUSION LENGTH
In a homogeneous semiconductor material, the average distance minority carriers move during their lifetime (i.e., between generation and recombination).
DIODE
An electronic device which has two terminals and an asymmetrical or nonlinear voltage-current characteristic.
DIODE ISOLATION
A technique in which a high electrical resistance between an integrated circuit element and its substrate is achieved by surrounding the element with a reverse biased pn junction.
DIP (DUAL-IN-LINE PACKAGE)
A chip carrier or package consisting of a plastic or ceramic body with two rows of vertical leads in which a semiconductor integrated circuit is assembled and sealed. The leads are typically inserted into a circuit board and secured by soldering.
DIRECT BAND GAP SEMICONDUCTOR
A semiconductor material in which an electron transition from the conduction to the valence band, or vice versa, does not require a change in crystal momentum for the electron. Gallium arsenide is a direct band gap semiconductor material.
DISCRETE CIRCUIT
A circuit which has an individual identity and which is fabricated prior to installation, or is separately packaged and is not part of an integrated circuit.
DISLOCATION
A region in a crystal in which the atoms are not arranged in a perfect lattice-like structure. See CRYSTAL DEFECT for examples of crystal defects/dislocations.
DMOSFET
Depletion type metal oxide semiconductor field effect transistor. Such devices are normally in the on condition with no applied gate voltage.
DONOR IMPURITY
An element which when added to a semiconductor provides unbound or free electrons to the semiconductor which may serve as current carriers. Typically, donors are atoms which have more valence electrons than the atoms of the semiconductor material into which they are introduced in small quantities as an impurity or dopant. Since such donor impurities have more valence electrons than the semiconductor, a semiconductor doped with donor impurities is an n-type semiconductor.
DOPANT
An impurity added to a semiconductor material to change its electrical conductivity or other characteristics. N-type (negative) dopants, such as phosphorus, for a group IV semiconductor such as silicon typically come from group V of the periodic table. When added to silicon n-type dopants create a material that contains conduction electrons. P-type (positive) dopants, such as boron, for a group IV semiconductor such as silicon, typically come from group III and result in holes.
DOPING PROFILE
The point to point concentration throughout a semiconductor of an impurity atom doped into the semiconductor.
DOUBLE-DIFFUSED MOS (DMOS)
A metal oxide semiconductor having diffused junctions in which successive diffusions of different impurity types are made in the same well-defined region of the semiconductor.
DRAIN
The electrode of a field effect transistor which receives charge carriers which pass through the transistor channel from the source electrode.
DRAIN CURRENT
The flow of charge carriers in the drain region of a field effect transistor.
DRAIN-SOURCE SATURATION CURRENT
The maximum amount of current carried by the drain of a field-effect transistor when the gate- source voltage equals zero volts.
DRIFT CURRENT
Current produced in a solid-state electronic device by charge carriers (e.g., holes or electrons) drifting in the direction of an applied electric field.
DUAL GUARD-BAND ISOLATION
A type of electrical isolation of functional elements of an integrated circuit comprised of two distinct unused areas of chip surface area adjacent to the elements desired to be electrically isolated.
DUAL-IN-LINE (DIP)
See DIP.
DYNAMIC RANDOM ACCESS MEMORY (DRAM)
solid-state memory in which the information decays over time and needs to be periodically refreshed.
EB JUNCTION
Emitter base junction in a bipolar transistor.
ELECTRON
The negatively charged particle in an atom that orbits the nucleus in specific energy levels.
ELECTRON FLOW
Movement of electrons from a source of negative potential to a positive potential.
ELECTRON-HOLE PAIR
A positive charge carrier (i.e., hole) and a negative charge carrier (i.e., electron) considered together as being created or destroyed as part of one and the same event.
EMITTER
The region of a bipolar junction transistor from which charge carriers flow through the emitter-base junction into the base region of the device.
EMITTER CURRENT
The amount of current flowing from the emitter across the emitter-base junction into the base region of the device.
E-MOSFET
Enhancement mode metal oxide semiconductor device. See ENHANCEMENT MODE and MOSFET.
ENERGY LEVELS
The possible energy values that an atom or molecule or subatomic particle (e.g., an electron) can have.
ENHANCEMENT MODE
The operation of a field effect transistor which has a channel formed therein between its source and drain regions and which normally does not conduct current through its channel with zero voltage applied to its gate electrode. Voltage of the correct polarity will accumulate minority carriers in the channel to permit conduction of current in the channel, thus turning on the transistor.
EPITAXY
The growth of a crystal of one substance on the surface of a crystal of the same or another substance so that the crystal lattice of the base substance controls the orientation of the atoms in the grown crystal.
EPITAXIAL LAYER
An added layer of crystal that takes on the same crystalline orientation as the substrate crystal.
ESAKI DIODE
A heavily doped pn junction diode where conduction occurs through the junction potential barrier due to a quantum mechanical effect even though the carriers which tunnel through the potential barrier do not have enough energy to overcome the potential barrier. Esaki tunneling involves a tunneling barrier formed by a macroscopic depletion layer between n-type and p-type regions. It does not involve a resonant tunneling barrier using controlled quantum confinement, a layer located between junctions, nor a thin superlattice layer.
EXCESS CARRIERS
Charge carriers present in a semiconductor in excess of those present in thermal equilibrium.
EXTRINSIC SEMICONDUCTOR
A semiconductor whose charge carrier concentration and, therefore, electrical properties depend on impurity, atoms introduced therein.
FACE BONDED
A chip mounting technique wherein semiconductor chips are provided with small mounting pads, turned face down, and bonded directly to conductors on a substrate.
FANNED LEADS
Leads placed through a package wall at closer intervals than normal and radiated (fanned) out on the exterior of the package until a desired center-to-center lead spacing is achieved.
FET
Acronym for field effect transistor.
FIELD EFFECT TRANSISTOR
A unipolar transistor in which current carriers are injected at a source terminal and pass to a drain terminal through a channel of semiconductor material whose conductivity depends largely on an electric field applied to the semiconductor from a control electrode. There are two main types of FET, a junction FET and an insulated-gate FET. In the junction FET, the gate is isolated from the channel by a pn junction. In an insulated-gate FET, the gate is isolated from the channel by an insulating layer, so that the gate and channel form a capacitor with the insulating layer as the capacitor dielectric.
FIELD OXIDE
A thin (on a macroscopic scale) film made up of an oxide of a material which overlies a device substrate to reduce parasitic capacitive coupling between conductors overlying the oxide and the substrate or devices below the oxide layer (e.g., in the substrate).
FLAT PACK
An integrated circuit package with leads extending from it in the same plane as that of the package. It has a low profile.
FLIP-CHIP
A term which describes the situation wherein a semiconductor device which has all terminations on one side thereof in the form of bump contacts, has a passivated surface and has been flipped over and attached to a matching substrate.
FLOATING DIFFUSION
A region of a semiconductor device in which impurity atoms have been doped and which is electrically floating, that is, has no direct electrical connection.
FLOATING GATE
A gate electrode that is electrically floating, that is, has no direct electrical connection.
FOOTPRINT
Also called a land pattern. It is a combination of lands used to mount a surface mount component. Metal pads on a substrate surface are arranged in the same pattern as the leads or pads on the component itself.
FORBIDDEN ENERGY BAND/REGION/GAP
The energy band of a material which is located between a solid material's conduction and valence bands. It is defined by the amount of energy that is needed to release an electron from its valence band to its conduction band. Electrons cannot exist in this gap. They are either below it, and bound to an atom, or above it, and able to move freely.
FORWARD BIAS
An external voltage applied in the conducting direction of a pn junction. A positive potential is connected to the p-type material and a negative potential to the n-type semiconductor material.
FORWARD BREAKOVER POTENTIAL
The value of positive terminal voltage at which a regenerative device (e.g., a silicon controlled rectifier), with its gate circuit open, becomes conductive.
FORWARD CURRENT
The current which flows across a semiconductor junction when a forward bias is applied across the junction.
FOUR-LAYER DIODE
A semiconductor diode with three junctions and only two terminals connected to the outer layers forming the junctions. This includes two terminal pnpn thyristors.
FOUR-PHASE CCD
A charge coupled device having four electrode sets and four gate voltages.
FOUR-SIDE LEAD LAYOUT
The situation wherein there are leads through all four sides of an integrated circuit package.
FRAME TRANSFER CCD
A charge coupled device area imager array with a separate image area, storage area, and read-out register area, the storage area being located between the image area and the readout area. This is distinguished from an
interline-transfer CCD in which the sensing and storage/readout function areas are located next to each other.
FREE ELECTRON
An electron not bound to a particular atom, but free to circulate among the atoms of a solid material.
GAIN
The ratio of the magnitude of the electrical output of a device to the magnitude of its electrical input.
GALLIUM ARSENIDE
A semiconducting chemical compound which is often used in active solid-state devices.
GATE
The control electrode or region of a field effect transistor, located between the source and drain electrodes, and regions thereof.
GATE ARRAY
A repeating geometric arrangement of groups of active solid-state devices, each group being connectable into a logic circuit, in one integrated, monolithic semiconductor chip.
GATE CHARGE
The electrical charge on a gate electrode.
GATE CONTROLLED DIODE
A three terminal semiconductor diode with the ability to be turned on or off by a pulse applied to its gate electrode.
GATE TRIGGER CURRENT
The amount of current needed to commence gate current flow in a four layer semiconductor device (e.g., a thyristor).
GATE TRIGGER VOLTAGE
The amount of voltage needed to begin gate current flow in a four layer semiconductor device (e.g., a silicon controlled rectifier).
GERMANIUM
A semiconductor material used in active solid-state devices.
GULL-WING
The name given to lead configurations of some surface mounted devices. Gull wings extend from the side of a component package and have an L-shaped bend at component ends, which extend down to the substrate surface and away from the component.
GUNN DIODE
A diode in which electrons under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the conduction band of the active semiconductor device material or holes under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the valence band of the active semiconductor device material. A Gunn diode does not normally have a pn junction and cannot be used as a rectifier.
GUNN EFFECT
An inter valley transfer effect wherein electrons under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the conduction band of the active semiconductor device material, or holes under the influence of sufficiently high electric fields are transferred between energy valleys of different momentum in the valence band of the active semiconductor device material.
HALL EFFECT DEVICE
An active solid-state device in which a current is flowing and is in a magnetic field perpendicular to the current, and in which a voltage is produced that is perpendicular to both the current flow direction and the magnetic field direction.
HALOGENS
F, Cl, Br, I, At.
HEADER
A slab-like or flat plug-in base for a package that is designed to be used with a cover or lid.
HEAT SINK
Devices used to absorb or transfer heat away from heat sensitive devices or device components.
HEAVY METALS
Metals other than light metals - see LIGHT METALS.
HETEROJUNCTION /HETEROINTERFACE
An interface between two dissimilar semiconductor materials. For example, one material may by InAs and the other may be InAlAs, or one material may be GaAs and the other material may be GaAlAs.
HETEROSTRUCTURE
See HETEROJUNCTION.
HIGH ELECTRON (HOLE) MOBILITY TRANSISTOR (HEMT)
A heterojunction field effect transistor with impurity ions located on the side of the hetero junction with lower affinity for the charge carriers (holes or electrons) injected at the source that pass to the drain via a channel adjacent the hetero junction.
HOLDING CURRENT
The minimum current needed to maintain a generative type active solid-state device (e.g., a thyristor) in an "on" or conducting condition.
HOLE
An empty energy level in the valence band of a semiconductor crystal which exhibits properties of a real particle and can act as a mobile positive charge carrier.
HOLE FLOW
The current in a semiconductor material due to the movement of holes therein.
HOMOJUNCTION
An interface between regions of opposite polarity in the same semiconductor material.
HOT CARRIER DIODE
A diode in which electrons (or holes) have energies greater than those that are in thermal equilibrium with the material of at least one of the regions forming the diode. Schottky barrier diodes typically have "hot carriers" (hot electrons) injected into the metal from the semiconductor.
HOT ELECTRONS
See HOT CARRIER DIODE.
HYBRID CIRCUIT
A small printed circuit having miniature components, which may include passive components (resistors, capacitors, and inductors, deposited on a printed circuit board. A "hybrid circuit" is NOT an integrated circuit, and is not
classifiable in this class.
IMPURITY
A foreign material present in a semiconductor crystal, such as boron or arsenic in silicon, which is added to the semiconductor to produce either p-type or n-type semiconductor material, or to otherwise result in material whose electrical characteristics depend on the impurity dopant atoms.
INDIRECT BAND GAP SEMICONDUCTOR
A semiconductor material in which a change in semiconductor crystal momentum for an electron is required when it moves from the conduction band to the valence band and vice versa. Silicon is an indirect band gap semiconductor.
INSULATED-GATE FIELD EFFECT TRANSISTOR (IGFET)
A unipolar transistor with source, gate, and drain regions and electrodes, in which conduction takes place in a channel controlled by action of the voltage applied to the gate electrode of the device, in which the gate electrode is separated from the channel by an insulator layer.
INSULATOR
A material which has a high resistance to the flow of electric current. It has such low electrical conductivity that the flow of current therethrough can usually be neglected.
INTEGRATED CIRCUIT
See MONOLITHIC DEVICE (e.g., IC) as contrasted to HYBRID CIRCUIT.
INTRINSIC CONCENTRATION
The number of minority carriers in a semiconductor due to thermal generation of electron-hole pairs.
INTRINSIC SEMICONDUCTOR
A pure semiconductor, i.e., one with no impurity atoms introduced therein.
INVERSION
A condition in a semiconductor material in which the concentration of minority carriers exceeds the concentration of majority carriers.
INVERSION LAYER/CHANNEL
A region in a semiconductor material in which the
concentration of minority carriers exceeds the concentration of majority carriers.
IRON GROUP METALS
Fe, Co, Ni.
ISOLATION
Prevention of the flow of electric current between electronic component parts of a solid-state electronic device.
ISOPLANAR CMOS
A semiconductor device in which relatively thick regions of silicon dioxide, recessed into the semiconductor surface, are used to electrically isolate device areas and prevent parasitic device formation. More commonly called LOCOS CMOS.
ISOPLANAR ISOLATION
A type of electric isolation in which relatively thick regions of silicon dioxide, recessed into the semiconductor surface, are used to electrically isolate device areas and prevent parasitic device formation. More commonly called LOCOS ISOLATION.
J-LEAD
A rolled-under, J-shaped configuration of some surface mounted component leads.
JUNCTION
A joining of two different semiconductors or of a semiconductor and a metal at an interface. Types of junctions include HETEROJUNCTIONS, SCHOTTKY BARRIER JUNCTIONS, and PN JUNCTIONS.
JUNCTION BARRIER
The opposition to the diffusion of majority carriers across a pn junction due to the charge of the fixed donor and acceptor ions.
JUNCTION CAPACITANCE
The capacitance across a pn junction. It depends on the width of the depletion layer, which increases with increased reverse bias voltage across the junction.
JUNCTION GATE FIELD EFFECT TRANSISTOR (JFET)
See FIELD EFFECT TRANSISTOR.
JUNCTION ISOLATION
Electrical isolation of devices on a monolithic integrated circuit chip using a reverse biased junction diode to establish a depletion layer that forms the electrical isolation between devices.
JUNCTION RESISTANCE
The electrical resistance across a semiconductor PN junction.
LAND
The conductive areas, normally metal patterns, on a semiconductor integrated circuit, which form part of the contacts and interconnections between components on the integrated circuit.
LAND PATTERN
A combination of lands on an integrated circuit.
LANTHANIDE ELEMENTS
La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho,Er, Tm, Yb, Lu.
LATCHING/LATCHED/LATCHUP
The state or condition of a regenerative feedback device, e.g., a thyristor, in which the device remains ON when the initializing signal is removed.
LCCC
An abbreviation for a leadless ceramic chip carrier which is a hermetically-sealable ceramic package in which an integrated chip can be placed to create a surface mounted component. It has pads around its perimeter for connection to a substrate.
LEAD
The conductor brought out from a component.
LEAD FRAME
A metal frame which provides support for an integrated circuit chip or die as well as electrical leads to interconnect the integrated circuit on the die or chip to other electrical components or contacts.
LEAKAGE CURRENT
Unwanted current flow.
LIFETIME
The average time interval between the introduction of and recombination of minority charge carriers in a semiconductor.
LIGHT EMITTING DIODE (LED)
Junction diodes which give off light when energized.
LIGHT METALS
Alkali metals, alkaline-earth metals, Be, Al, Mg.
LINE DEFECT
A planar crystal defect (e.g., an extra plane of atoms in a crystal). It is also called an edge dislocation.
LOCAL OXIDE CMOS (LOCMOS)
Local oxide complementary metal oxide semiconductor structure which features oxide isolation which is recessed into the semiconductor surface.
LOCOS
(Local Oxidation of Silicon) Patterns of oxide isolation which are recessed into the semiconductor surface. Sometimes also called isoplanar, ROX (Recessed Oxide Isolation), or planox.
LUMINESCENCE
Emission of light by directly converting some other type of energy. Types include thermoluminescence, photoluminescence, cathodoluminescence, and electroluminescence. It includes fluorescence and phosphorescence. Active solid-state luminescent devices are semiconductors which operate via injection luminescence. Active devices include pn junctions (including heterojunctions), Schottky barrier junctions, metal-insulator-semiconductor (MIS) structures, and high speed traveling domains, e.g., Gunn domain and acoustoelectric wave generated domains; whereas passive solid-state electroluminescent devices (phosphors) are insulators which operate in an intrinsic luminescence phenomena, i.e., where an applied electric field generates free carriers (there being no free carriers in an insulator to be accelerated by an applied field unless the field also generates them) to initiate the light emission mechanism.
MAJORITY CARRIER
The predominant charge carrier in a semiconductor. Electrons are majority carriers in n-type semiconductors. Holes are majority carriers in p-type semiconductors.
MAJORITY CURRENT
Current caused by the flow of majority carriers.
MASTERSLICE ARRAY/MASTERCHIP
A substrate that contains active and passive electronic components in a predetermined pattern which may be connected into different logic or analog circuits.
MBM JUNCTION
Active solid-state devices having metal-barrier-metal layer junctions.
METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET)
See INSULATED GATE FIELD EFFECT TRANSISTOR.
METAL-GATE FET
A field effect transistor having a gate conductor made of metal, rather than polycrystalline semiconductor material.
METALLIZATION
A single or multilayer film pattern of electrically conductive material deposited on a substrate to interconnect electronic components, or the metal film on the bonding area of a substrate which becomes part of the bond and performs both an electrical and a mechanical function.
METALS
Elements other than non-metals. See NON-METALS.
MIM DIODE
A junction diode with a thin insulating layer of material sandwiched between two metallic surface layers which operates as a tunneling (direct or Fowler-Nordheim type) diode.
MINORITY CARRIER
The less predominant charge carrier in a semiconductor. In a p-type semiconductor, minority carriers are electrons, whereas in n-type semiconductor material, minority carriers are holes.
MINORITY CURRENT
The current caused by flowing minority carriers.
MIS
Acronym for metal-insulator-semiconductor. Typically active solid-state devices with MIS technology have a silicon dioxide layer formed on a single crystal silicon substrate. A polysilicon conductor layer is formed on the oxide.
MOBILITY
The facility with which carriers move through a semiconductor when subjected to an applied electric field. Electrons and holes typically have different mobilities in the same semiconductor.
MODFET
Acronym for a modulation doped field effect transistor. A high speed semiconductor FET in which dopant atom containing semiconductor layers alternate with non-doped semiconductor layers, so that the carriers (electrons or holes) resulting from the dopant atoms can travel in the undoped material, so that there is little scattering of carriers from dopant atoms. Typically, the dopant atoms are in semiconductor material having a lower carrier affinity than the undoped layers, to facilitate carrier spill over into the undoped layers. Such a structure may typically constitute a superlattice. See also HIGH ELECTRON MOBILITY TRANSISTOR (HEMT).
MODULATION DOPING
Spatial modulation of dopant atoms in a semiconductor crystal.
MONOLITHIC DEVICE (e.g., IC)
A device in which all components are fabricated on a single chip of silicon. Interconnections among components are provided by means of metallization patterns on the surface of the chip structure, and the individual parts are not separable from the complete circuit. External connecting wires are taken out to terminal pins or leads.
MSM
Acronym for metal-semiconductor-metal semiconductors. Active solid-state semiconductor devices having a semiconductor layer sandwiched between two layers of metal.
MULTILAYER METALLIZATION
Two or more layers of interconnecting metallization patterns in a monolithic integrated circuit separated by insulator material except in interconnection areas.
N-TYPE SEMICONDUCTOR
An extrinsic semiconductor in which electron density exceeds hole density.
NDM
Negative differential mobility (e.g., Gunn effect)
intervalley active semiconductor devices wherein an applied electric field imparts energy to electrons or holes to permit them to jump to higher quantum electronic intervalley energy levels in which electrons have lowered electron mobility.
NEGATIVE RESISTANCE REGION
An operating region of an active solid-state electronic device in which an increase in applied voltage results in a decrease in output current.
NEGATIVE TEMPERATURE COEFFICIENT
The amount of reduction in a device parameter, such as capacitance or resistance, for each degree of device operating temperature.
NMOS
N-channel metal oxide semiconductor devices which use electrons as majority carriers.
NOBLE GASES
He, Ne, Ar, Kr, Xe, Rn.
NON-METALS
H, B, C, Si, N, P, O, S, Se, Te, noble gases, halogens.
NPN TRANSISTOR
A transistor in which the base is made of p-type material and both source and drain are made of n-type semiconductor material.
N-CHANNEL FET
A field effect transistor that has an n-type conduction channel.
N-TYPE SEMICONDUCTOR
An extrinsic semiconductor having n-type dopant atoms, e.g., atoms with one more valence electron than the host atoms.
ORGANIC SEMICONDUCTOR
A semiconductor compound in which the molecule is characterized by two or more carbon atoms bonded together, one atom of carbon bonded to at least one atom of hydrogen or halogen (i.e., chlorine, fluorine, bromine, iodine) or one atom of carbon bonded to at least one atom of nitrogen by a single or double bond.
(1) Note. Exceptions to this rule include HCN, CN-CN, HNCO, HNCS, cyanogen halides, cyanamide, fulminic acid, and metal
carbides. These are not regarded as organic semiconductor materials. Also, note that graphite and diamond are not regarded as organic semiconductors since they are not compounds; silicon carbide is not regarded as organic.
OXIDE ISOLATION
Electrical isolation of semiconductor electronic devices in a monolithic integrated circuit by an oxide (e.g., silicon oxide).
PACKAGE
A container, case, or enclosure for protecting a solid-state electronic device from the environment.
PAD
(1) The portion of a conductive pattern on a solid-state electronic device for making external connection thereto; (2) the portion of a conductive pattern on a chip or a printed circuit board designed for mounting or attaching a substrate or solid-state active electronic device.
PARASITIC CURRENT
Unintended current which flows between devices in an integrated circuit, or which flows between device regions and isolation regions.
PARASITIC DEVICES/CHANNELS
Junctions forming unintended active solid-state devices which interconnect intended active solid-state devices, which unintended devices are not designed to carry current flow.
PARASITIC THYRISTOR ACTION
Unwanted active solid-state device formation in which four adjacent complementary doped regions not designed to act as an active solid-state device, lack sufficient isolation therebetween and act as a thyristor. Parasitic thyristor action is typically a problem encountered in CMOS integrated circuits.
PARASITIC TRANSISTOR ACTION
Unwanted transistor formation in an integrated circuit structure.
PASSIVE DEVICE
A solid-state electronic device or component in which charge carriers do not change their energy levels and that does not provide rectification, amplification, or switching, but which does react to voltage and current. Examples are pure resistors, capacitors, and inductors.
P-CHANNEL
A conduction path, made of p-type semiconductor material, located between the source and drain of a field effect device.
PERISTALTIC CCD
See BULK CHANNEL CCD.
PERMISSIBLE ENERGY LEVEL
An energy level in a conduction or valence band which a charge carrier (electron or hole) may have.
PHOTODIODE
A diode in which charge carriers are created by light which illuminates the diode junction. It is a photovoltaic as well as a photoconductive device.
PHOTOTRANSISTOR
A transistor having no base terminal and in which charge carriers are created by light which illuminates its collector-base junction.
PHOTOVOLTAIC CELL
An active solid-state device with a pn junction that generates a voltage in response to light impinging on the junction.
PINCH-EFFECT RESISTOR
A monolithic integrated circuit resistor having a layer of one conductivity type, typically a P-layer formed at the same time as integrated circuit bipolar transistor base regions, which is thinned by an inset region of opposite conductivity type, typically an N-layer formed at the same time as integrated circuit bipolar transistor emitter regions.
PINCH-OFF
The condition in a depletion mode field effect transistor wherein the conducting channel is depleted of majority carriers and is thereby pinched off, no path remaining for the source-to-drain majority carrier (e.g., electron) flow.
PIN DIODE/DEVICE
A diode having an intrinsic semiconductor (i.e., one with no dopants) sandwiched between a p-type layer and an n-type layer. The depletion region (the intrinsic semiconductor layer) thickness can be tailored to optimize quantum efficiency for use as a photo diode or frequency response for
use as a microwave diode.
PIN-GRID ARRAY
A semiconductor chip package having leads in the form of pins arranged in columns and rows.
PLANAR TRANSISTOR
A bipolar transistor in which the emitter base and collector regions terminate at the same plane surface without indentations in or protrusions from the surface. Hence, the emitter and base regions form dish shaped portions extending into the semiconductor from the common surface.
PLUG-IN PACKAGE
An electronic package for an active solid-state device in which the lead pins are perpendicular to the mounting area of the substrate, as contrasted with a flat package in which the leads are in the same plane as the substrate.
P-MOSFET
A metal oxide semiconductor field effect transistor having p-type source and drain regions and a p-type conduction channel which may be formed by a p type doped region (depletion mode) or induced by a voltage on the gate (enhancement mode).
PN-JUNCTION
The interface and region of transition between p-type and n-type semiconductors.
PN-JUNCTION DIODE
A semiconductor device having two terminals connected to opposite type semiconductor materials with a junction therebetween and exhibiting a non-linear voltage-current characteristic, usually used for switching or rectification.
PNP TRANSISTOR
A bipolar transistor with a p type emitter, an n-type base and a p-type collector.
POINT DEFECT
A crystal defect occurring at a point in a crystal. Examples include, (1) a foreign atom incorporated into the crystal lattice at either a substitutional (regular lattice) site or interstitial (between regular lattice sites) site, (2) a missing atom in the lattice, or (3) a host atom located between regular lattice sites and adjacent to a vacancy (called a Frenkel defect).
POLYCRYSTALLINE
A material composed of more than one crystal.
POLYSILICON
A polycrystalline form of silicon.
POSITIVE CARRIER
A charge carrier which has a net positive charge (e.g., a hole).
POSITIVE IONS
Atoms which are missing a valence shell electron.
POTENTIAL BARRIER
The difference in electrical potential across a pn junction in a semiconductor.
POTENTIAL HILL
See POTENTIAL BARRIER.
POTTING
An embedding process in which an electronic component is placed in a can, shell, or other container and buried in a liquid dielectric polymer which subsequently changes to a solid material. The container is not removed from the finished part, and a release agent is not used. This process differs from casting - which involves a removable mold.
PRINTED CIRCUIT BOARD
A structure formed on one or more layers of electrically insulating material having electrical terminals and conductive material deposited thereon, in continuous paths, from terminal to terminal, to form circuits for electronic apparatus such as chips or substrates.
P-TYPE CONDUCTIVITY
Electrical conductivity associated with positive charge carriers (holes) in a semiconductor material.
P-TYPE SEMICONDUCTOR
An extrinsic semiconductor in which the hole density exceeds the conduction electron density.
PUNCHTHROUGH
Expansion of a depletion region* from one junction to another junction in an active solid-state device.
PURPLE PLAGUE
A brittle, inter metallic electrically conductive compound which has a purplish color and is formed when aluminum and gold, used as electrical contact materials in semiconductor electronic devices, contact each other and interact. It is usually considered undesirable because it breaks easily, reduces device reliability, and lowers product yield.
QUANTIZED STATES
Discrete energy levels due to the quantum mechanical properties of a material.
QUANTUM TRANSISTOR
Transistors whose operation is based on the properties of electrons confined in quantum wells - semiconductor films only a hundred or so angstroms thick sandwiched between high confining walls made of a second semiconductor material.
QUANTUM WELL
Semiconductor films only a hundred or so angstroms thick sandwiched between high confining walls made of a second material.
RARE EARTHS
Sc, Y, Lanthanides.
READ-OUT REGISTER
Gated semiconductor devices which receive and accumulate charges and make them available to an output device.
RECOMBINATION
The process by which excess holes and electrons in a semiconductor crystal recombine and and no longer function as charge carriers in the semiconductor. Basic recombination processes are band-to-band recombination which occurs when an electron in the conduction band recombines with a hole in the valence band, and trapping recombination which occurs when an electron or hole is captured by a deep energy level, such as produced by a deep level dopant, before recombining with an opposite conductivity type carrier.
REFRACTORY METALS
Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W.
RESISTIVITY
A measure of the resistance of a material to electric current. Resistivity is a bulk material property, measured
in ohm-cm.
RESONANT TUNNELLING DEVICE
A device that works on the principle of resonant electron (or hole) tunneling through a pair of matched potential barriers. This occurs when the energy of the electrons (or holes) matches that of a quantum energy level in the quantum well formed between the barriers.
REVERSE BIAS
A voltage applied across a semiconductor junction in the reverse direction, i.e., wherein a positive potential is connected to the n-type semiconductor and a negative potential is applied to the p-type semiconductor.
REVERSE BREAKDOWN VOLTAGE
The reverse bias voltage value at which electrical resistance drops appreciably and operating current sharply increases.
REVERSE CURRENT
The current flowing through a rectifying junction with a reverse voltage thereacross.
SATURATION
The current between the base and collector of a bipolar transistor when an increase in emitter to base voltage causes no further increase in the collector current.
SCATTERING CENTERS
The impurities (dopants) in semiconductors that cause electrons or holes flowing through the semiconductor to scatter. These reduce carrier mobility and represent a problem in quantum devices because they affect electron coherence length.
SCHOTTKY BARRIER
A metal to semiconductor interface in which the carrier affinity and doping level of the semiconductor are such that a rectifying junction is formed. Usually, minority carriers in the semiconductor do not significantly contribute to the current flowing in a device with such a barrier.
SCHOTTKY DIODE
A diode with a Schottky barrier.
SEMICONDUCTOR
A material whose electrical resistivity is between that of insulators and conductors. The resistivity is commonly
changed by light, heat, electric, or magnetic fields incident on the material. Current flow is achieved by transfer of positive holes as well as by movement of electrons.
SEMICONDUCTOR DEVICE
A device in which current conduction takes place within a semiconductor.
SEMICONDUCTOR LASER
A light emitting diode that uses stimulated emission of radiation to produce coherent light output.
SILICON BILATERAL SWITCH (SBS)
A silicon controlled switch that can conduct current in both directions.
SILICON CONTROLLED RECTIFIER (SCR)
A four layer pnpn device that, when in a normal state, blocks applied voltage in either direction. Application of a correct voltage to a gate terminal permits the device to conduct in a forward direction.
SILICON CONTROLLED SWITCH (SCS)
A four layer pnpn semiconductor switching device that can be triggered into conduction by applying either positive or negative pulses.
SILICON-GATE FET
A field effect transistor which has a gate electrode made of silicon.
SILICON ON INSULATOR (SOI)
A semiconductor structure using an insulating substrate, instead of silicon as a substrate material, with an overlying active layer of single crystal silicon containing active solid-state devices. The substrate may typically be of the form of an insulating layer which is itself formed on a single crystal substrate.
SILICON ON SAPPHIRE (S0S) CMOS
A complementary metal oxide semiconductor device (e.g., a transistor) wherein single crystal silicon is grown on a passive insulating base of sapphire (single crystal alpha phase aluminum oxide) with complementary MOS transistors formed in the silicon in one or more island portions.
SILICON TRANSISTOR
A transistor which uses silicon as the semiconductor
material.
SINGLE-IN-LINE PACKAGE
A plug-in semiconductor device package with one row of pins with specified spacings therebetween.
SINGLE CRYSTAL
A body of material having atoms regularly located at periodic lattice sites throughout.
SINKER
A buried electrically conductive, low resistance path in an integrated circuit which connects an electrical contact to a conductive region buried in the integrated circuit. It may be made up of a heavily doped impurity region.
SIS
An MIS structure (Metal-Insulator-Semiconductor) in which the "metal" layer is made of semiconductor material, typically polycrystalline silicon.
SOLAR CELL
A photovoltaic cell in the form of a semiconductor diode, usually made of silicon, that generates electricity directly from sunlight impingent on the cell.
SOLID-STATE DEVICE
An electronic device or component that uses current flow through solid (as opposed to liquid), gas, or vacuum materials. solid-state devices may be active or passive.
SOURCE
In a field effect transistor, the electrode to which the source of charge carriers is connected.
SPACE CHARGE REGION
The region around a pn junction in which holes and electrons recombine to leave no mobile charge carriers and a net charge density due to the residual dopant ions.
STEP RECOVERY DIODE
A pn junction active solid-state device in which a forward bias voltage injects charge carriers across the junction but prior to recombination of the carriers, a reverse voltage is applied to return the charge carriers to their source as a group.
SUBSTRATE
The supporting material on or in which the components of an integrated circuit are fabricated or attached.
SUBSTRATE BIAS
The electric potential applied to a substrate, which typically serves as the reference potential against which other voltages are measured. Also, in a MISFET, a voltage applied to the substrate with respect to the source region.
SUPERLATTICE
A periodic sequence of variations in carrier potential energy in a semiconductor, of such magnitude and spacing that the current carrier wave function is spread out over many periods, so that carrier energy and other properties are determined in part by the periodic variations. The variation may be in chemical composition of the material, as in a sequence of heterojunctions, or in impurity concentration, forming a doping superlattice, or both.
SURFACE-CHANNEL CCD
A charge coupled device in which charge resides at the semiconductor surface.
SURFACE MOUNT DEVICES
Active or passive solid-state devices which are structured and configured to be mounted directly to a printed circuit board surface. This type of mounting is distinguished from "through-hole" mounting which involves the electrical and physical connection of devices to a printed circuit board using drilled and plated holes through the conductive pattern of the board.
SURFACE RESISTIVITY
The resistance of a material between two opposite sides of a unit square of its surface. Also called Sheet Resistance. Measured in ohms, often written as "ohms per square" in this case.
TEST PROBES
Mechanical points of contact used for electrical measurement.
THERMISTOR
A semiconductor device whose electrical resistance varies with temperature. Its temperature coefficient of resistance is high, nonlinear, and usually negative.
THICK-FILM DEVICES
Printed thin-film circuits. Silk screen printing techniques are used to make the desired circuit patterns on a ceramic substrate. Active devices may be added thereto as separate devices (see HYBRID CIRCUIT).
THIN-FILM DEVICES
solid-state electronic devices which are constructed by depositing films of conducting material on the surface of electrically insulating bases.
THYRISTOR
A four layer p-n-p-n bistable switching device that changes from an off or blocking state to an on or conducting state which uses both electron and hole type carrier transport.
THRESHOLD VOLTAGE
The voltage at which a pn junction begins to conduct current.
THROUGH-HOLE MOUNTING
The electrical and physical connection of components to the surface of a conductive pattern using drilled and plated holes through the conductive and insulating layers of a printed circuit board.
TRANSFERRED ELECTRON DEVICE
See GUNN EFFECT. In such devices, advantage is taken of the negative differential mobility of electrons or holes in certain semiconducting compounds, particularly GaAs or InP.
TRANSISTOR
An active solid-state semiconductor device having three or more electrodes in which the current flowing between two specified electrodes is modulated by the voltage or current applied to one or more specified electrodes, and is capable of performing switching or amplification.
TRANSITION ELEMENTS
Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Te, Ru, Rh, Pd, Ag, Cd, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Ac, Th, Pa, U, Np, Pu, Am, Cm, Bk, Cf, E, Fm, Mv, No, Lw.
TRAPATT DEVICE
An acronym for trapped plasma avalanche triggered transit diodes, which are biased into avalanche condition. As the diode breaks down, a highly conducting electron-hole plasma quickly fills the entire n-type region, and the voltage across the diode drops to a low value. The plasma is then
extracted from the diode by the low residual electric field, thus causing a large current flow even though the voltage is low. Once extraction of the plasma is completed, the current drops and the voltage rises.
TRENCH ISOLATION
Electrical isolation of electronic components in a monolithic integrated circuit by the use of holes or other indentations in the surface of the device filled with dielectric material.
TUNNEL DIODE
A semiconductor diode in which the electrons penetrate a quantum barrier that is impenetrable in terms of classical physics, but which is penetrable in terms of quantum physics due to the quantum mechanical uncertainty in position of current carriers.
TUNNEL EFFECT/TUNNELLING
See TUNNEL DIODE and RESONANT TUNNELING DEVICE.
TWIN-TUB STRUCTURE
CMOS device structure in which both p-type and n-type deep wells are formed into a substrate for the n-channel and p-channel device (e.g., a transistor), respectively.
TWO-DIMENSIONAL ELECTRON GAS
A description of the motion of electrons which are confined in only one direction, such as electrons in the conducting channel of a MOSFET. In an electron gas, the electrons move around without apparent restriction. The behavior of electrons in conducting metals (e.g., copper) is an example of a three-dimensional electron gas. In a two dimensional electron gas, motion is restricted to a single plane (two dimensions).
UNIPOLAR
An active solid-state electronic device in which only one type of charge carrier, positive or negative, is used to support current flow.
UNIPOLAR TRANSISTOR
A transistor in which the source to drain current involves only one type of charge carrier.
VARACTOR
A semiconductor diode that changes capacitance with a change in applied voltage, comprising a two terminal active device using the voltage variable capacitance of a pn junction or a
Schottky junction.
VARISTOR
A term applied to both passive and active solid-state devices. A varistor is a two-electrode semiconductor device with a voltage dependent nonlinear resistance which falls significantly as the voltage is increased. In an active device, the non-linear property is due to the presence of one or more potential barriers, whereas, in a passive type varistor, it is due to electrical heating of the material due to current flow therethrough. Varistors are to be contrasted with passive variable resistors such as rheostats or potentiometers.
VERTICAL JUNCTION
A junction of finite width which has a vertical axis. The materials which form it lie on either horizontal side thereof.
VIA
A metallized or plated-through hole, in an insulating layer, e.g., a substrate, chip or a printed circuit board which forms a conduction path itself and is not designed to have a wire or lead inserted therethrough.
WAFER
A thin slice of semiconductor material with parallel faces used as the substrate for active solid-state devices in discrete or monolithic integrated circuit form.
WIRE BOND
Attachment of a tiny wire, as by thermocompression bonding, to a bonding pad on a semiconductor chip.
WIRING CHANNEL
An area on an integrated circuit, such as a gate array, which is left free of active devices and in which interconnection metallization patterns are formed.
WORK FUNCTION
The minimum energy required to remove an electron from the Fermi level of a material and liberate it to free space outside the solid.
ZENER CURRENT
The current generated by a Zener diode when its reverse voltage is increased above the Zener breakdown value.
ZENER DIODE
A single pn junction, two terminal semiconductor diode reversed biased into breakdown caused by the Zener effect, i.e., by field emission of charge carriers in the device's depletion layer. NOTE: True Zener breakdown occurs in silicon at values below 6 volts. It is to be distinguished from the avalanche breakdown mechanism that occurs in reverse biased diodes at higher (about 6 volts) voltages.

BULK EFFECT DEVICE:
This subclass is indented under the class definition. Subject matter in which the active device is made up of a semiconductor material whose electrical characteristics are due to the electronic properties of the semiconductor material, which are exhibited throughout the entire body of material rather than in just a localized region thereof (e.g., the surface).
(1) Note. Excluded from this subclass are semiconductive devices whose nonlinear characteristic is due to a junction rather than to the bulk properties of the semiconductor, whether they are homojunctions (i.e., made up of the same semiconductor material with different dopant ions on opposite sides of a junction) or heterojunctions (i.e., made up of different materials on either side of a junction).

SEE OR SEARCH THIS CLASS, SUBCLASS:
289 for insulated electrode devices having significant semiconductor compound in bulk crystal.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, subclass 900 for methods of making a bulk effect semiconductor device.

Bulk effect switching in amorphous material:
This subclass is indented under subclass 1. Subject matter wherein the bulk material is an amorphous material, i.e., one in which active solid material is non-crystalline in the sense that (1) there is either complete disorder in the arrangement of atoms/mole or molecules of the material or (2) there is an absence of any long range structural order that is detectable by electron or X-ray diffraction patterns of
the material and the device is used as an electronic switch.

With means to localize region of conduction (e.g., "pore" structure):
This subclass is indented under subclass 2. Subject matter wherein means (e.g., a porous structure) is provided to confine the operating current to a particular region of the bulk effect amorphous material.

With specified electrode composition or configuration:
This subclass is indented under subclass 2. Subject matter wherein the amorphous material bulk effect switching device has electrodes which have a particular chemical constituency or shape.

In array:
This subclass is indented under subclass 2. Subject matter in which the amorphous bulk effect switch has a group of individual switch elements with a predetermined (often regular) spacing extended in one or more directions.
(1) Note. The elements often extend in two dimensions to form two-dimensional arrays.

Intervalley transfer (e.g., Gunn effect):
This subclass is indented under subclass 1. Subject matter wherein electrons under the influence of sufficiently high electric fields are transferred between energy minima having different momentum in the conduction band of the active semiconductor material, or holes under the influence of sufficiently high electric fields are transferred between energy minima having different momentum in the valence band of the active semiconductor material.

SEE OR SEARCH CLASS:
331, Oscillators, subclass 107 for Gunn-type bulk effect
device oscillators.
341, Coded Data Generation or Conversion, subclass 133 for analog to or from digital conversion with particular solid-state devices (e.g., Gunn effect devices).
365, Static Information Storage and Retrieval, subclass 169 for systems using a Gunn effect device.

In monolithic integrated circuit:
This subclass is indented under subclass 6. Subject matter wherein the intervalley transfer devices are integrally combined with one or more other active (e.g., diode or transistor) or passive (e.g., resistor or capacitor) devices in a single solid-state electronic device.

Three or more terminal device:
This subclass is indented under subclass 6. Subject matter wherein an intervalley transfer device contains three or more electrical terminals.

THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE):
This subclass is indented under the class definition. Subject matter wherein the active material is a thin physical layer of material located between materials which have different electrical properties than the thin layer and wherein the thin active physical layer is (1) a potential well layer thin enough to establish discrete quantum energy levels or (2) a potential barrier layer thin enough to permit quantum mechanical tunneling or (3) a layer thin enough to permit carrier transmission therethrough with substantially no scattering of the carriers.
(1) Note. Examples of such devices are superlattice, quantum well, and ballistic transport devices.
(2) Note. Esaki tunneling is not the type of tunneling which this subclass and those indented thereunder contemplate. Esaki tunneling, while being quantum mechanical in nature, merely involves a tunneling barrier formed by a macroscopic depletion layer between n-type and p-type regions, but which neither a resonant tunneling barrier using controlled quantum mechanical charge confinement, a layer located between junctions, a thin layer as defined above. Esaki tunneling devices are found classified below, in subclasses 104+.
(3) Note. Active junction devices may employ a plurality of barrier junctions forming layers of material therebetween, but those layers are only classified in this subclass if they are thin enough to have the properties set forth in the definition. If those layers do not meet the definition, then the devices are classified below.

SEE OR SEARCH CLASS:
372, Coherent Light Generators, 43 for semiconductor lasers which may contain thin layer devices of this type for producing coherent light.

Low workfunction layer for electron emission (e.g., photocathode electron emissive layer):
This subclass is indented under subclass 9. Subject matter wherein a layer of material from which electrons are emitted with less input energy than that necessary to emit them from adjacent material is provided.
(1) Note. The adjacent material and the low workfunction layer form either a heterojunction or a Schottky barrier, depending on whether both materials are semiconductors or one of the materials is a metal.
(2) Note. Typical low workfunction layer devices include cold cathode emitters in electron tubes.

SEE OR SEARCH CLASS:
313, Electric Lamp and Discharge Devices, 346 and 373+ for photoemissive cathodes and subclasses 527, 530, 541, and 542+ for photocathodes in general.
438, Semiconductor Device Manufacturing: Process, subclass 20 for processes of making an electron emissive device utilizing a semiconductor substrate.

Combined with a heterojunction involving a III-V compound:
This subclass is indented under subclass 10. Subject matter in which the thin active layer and low workfunction layer for electron emission are combined with a heterojunction, i.e., a transition region between two materials with different energy band gaps, one material of which is a III-V compound, i.e., a compound wherein one material is found in group III of the periodic table and another material is found in group V of the periodic table.

Heterojunction:
This subclass is indented under subclass 9. Subject matter wherein the device includes at least two adjacent active layers, one of which is made of a substance that differs from that of the other.
(1) Note. See the illustration of a heterojunction device, in subclass 183.

SEE OR SEARCH THIS CLASS, SUBCLASS:
194 for heterojunction FETs having doping on the side of the heterojunction with lower carrier affinity.

Incoherent light emitter:
This subclass is indented under subclass 12. Subject matter wherein the device emits incoherent light.
(1) Note. Coherent light generators are explicitly excluded from this subclass. This means that cross-references from Class 372, Coherent Light Generators, are not to be placed in this subclass. It is not desired to create a duplicate set of heterostructure lasers in this subclass.

SEE OR SEARCH CLASS:
372, Coherent Light Generators, subclasses 43-50 for coherent semiconductor light generators.

Quantum well:
This subclass is indented under subclass 12. Subject matter wherein at least two heterojunctions are formed with a thin active layer of material having a relatively large carrier affinity between two materials with smaller carrier affinities, resulting in a quantum mechanical energy well located in the thin active layer with the relatively large carrier affinity.
(1) Note. Quantum well devices appear in many forms, including (a) heterostructures; (b) only those high electron mobility transistors (HEMTs) which use a quantum well or a plurality of quantum wells; (c) superlattices which comprise many quantum wells so tightly coupled that the individual wells are not distinguishable, but rather the wells become analogous to atoms in a lattice and superlattice devices may behave more like new types of materials rather than as groups of coupled quantum wells; and (d) resonant tunneling devices - which exhibit quantum coupling, charge confinement and resonant tunneling.
(2) Note. See the illustration, below, for a s:graphic example of a quantum well device. [figure]

Superlattice:
This subclass is indented under subclass 14. Subject matter wherein a large number of quantum wells are present, the quantum wells being sufficiently close to each other that carrier quantum wave functions are spread out over plural quantum wells and the intervening barriers formed by the boundaries between adjacent layers having different carrier affinities.
(1) Note. Thicknesses of both the quantum well layers and the barrier layers are typically a few angstroms to a few hundred angstroms (10[supscrpt]-10[end supscrpt] meter) thick.
(2) Note. See the illustration, below, for energy level diagrams showing band edge energy discontinuities at four types of superlattice heterointerfaces. [figure]

SEE OR SEARCH CLASS:
148, Metal Treatment, digest 160 for superlattice treatment.

Of amorphous semiconductor material:
This subclass is indented under subclass 15. Subject matter
wherein a superlattice active layer is made of a semiconductor crystal with no regular crystalline structure.

With particular barrier dimension:
This subclass is indented under subclass 15. Subject matter wherein the superlattice has a specific quantum electronic potential barrier dimension (e.g., height or width).

Strained layer superlattice:
This subclass is indented under subclass 15. Subject matter wherein the crystalline lattice characteristics of adjacent thin active superlattice layers are mismatched so that alternate layers are in elastic tension or compression.

Si[subscrpt]x[end subscrpt]Ge[subscrpt]1-x[end subscrpt]:
This subclass is indented under subclass 18. Subject matter wherein at least one of the strained superlattice materials is a silicon-germanium alloy.

Field effect device:
This subclass is indented under subclass 15. Subject matter wherein the superlattice active layer forms the conduction channel of a field effect device (i.e., one which has two or more terminals denoted as source and gate with a conduction channel therebetween, and in which the current through the conducting channel is controlled by an electric field coming from a voltage which is applied between the gate and source terminals thereof).

Light responsive structure:
This subclass is indented under subclass 15. Subject matter wherein absorption of light (ultraviolet, visible, or
infrared) by a superlattice active layer or junction causes a change in the current-voltage characteristic of the device.

With specified semiconductor materials:
This subclass is indented under subclass 15. Subject matter wherein the superlattice is formed of specified materials.

Current flow across well:
This subclass is indented under subclass 14. Subject matter wherein the device operation involves flow of carriers (electrons or holes) across the quantum well (as contrasted with tunneling through the well).
(1) Note. Current flow is considered to be "across" the well if the carriers have sufficient energy to pass over the barrier layers confining the quantum well, as contrasted to passing through the barriers by quantum mechanical tunneling.

SEE OR SEARCH THIS CLASS, SUBCLASS:
25 for devices which operate by resonant tunneling through the barriers, rather than over them.

Field effect device:
This subclass is indented under subclass 14. Subject matter wherein the quantum well device is a field effect device, i.e., one which has two or more terminals denoted as source and gate, with a conduction channel therebetween, and in which the current through the conducting channel is controlled by an electric field coming from a voltage which is applied between the gate and source terminals thereof.
(1) Note. See illustration under subclass 213 for various field effect devices.

Employing resonant tunneling:
This subclass is indented under subclass 14. Subject matter wherein the operation of the device depends not only on carrier charge confinement by the quantum well, but the quantum well layer also acts as an intermediate layer through which carriers pass by resonantly tunneling through both confining barriers and the well.

Ballistic transport device:
This subclass is indented under subclass 12. Subject matter in which an active layer is present through which carriers pass, wherein the active layer is thinner than the mean free path of the carriers in the material in that layer, so that carriers can pass through the layer without scattering.
(1) Note. Carriers are typically injected into the ballistic transport layer as "hot" carriers, having an energy, in the case of electrons, substantially greater than the minimum of the conduction band, or in the case of holes, substantially lower than the maximum of the valence band.

Field effect transistor:
This subclass is indented under subclass 26. Subject matter wherein the ballistic transport device is a field effect transistor, i.e., one which has two or more terminals denoted as source and gate with a conduction channel therebetween, and in which the current through the conducting channel is controlled by an electric field coming from a voltage which is applied between the gate and source terminals thereof.
(1) Note. See illustration, below, of various field effect devices under subclass 213.

Non-heterojunction superlattice (e.g., doping superlattice or alternating metal and insulator layers):
This subclass is indented under subclass 9. Subject matter wherein there are a plurality of active layers and barrier regions, the active layers being sufficiently close to each other that carrier quantum wave functions are spread out over plural active layers and the intervening barriers, and wherein the active layers and barrier regions do not form heterojunctions between different semiconductor materials.
(1) Note. Typically the active layers and barrier layers may be doped with opposite conductivity type dopants. Thicknesses of both the active layers and the barrier layers are typically a few angstroms to a few hundred angstroms (10[supscrpt]-10[end supscrpt] meter) thick.

Ballistic transport device (e.g., hot electron transistor):
This subclass is indented under subclass 9. Subject matter in which an active layer is present through which carriers pass, which active layer is thinner than the mean free path of the carriers in the material in that layer, so that carriers can pass through the layer without scattering.
(1) Note. Carriers are typically injected into the ballistic transport layer as "hot" carriers, having an energy, in the case of electrons, substantially greater than the minimum of the conduction band, or in the case of holes, substantially lower than the maximum of the valence band.

Tunneling through region of reduced conductivity:
This subclass is indented under subclass 9. Subject matter wherein the active layer through which carrier tunnelling occurs has lower electrical conductivity than the material adjacent thereto.

SEE OR SEARCH CLASS:
29, Metal Working, subclass 25.01 for methods of making barrier layer devices of the metal-insulator-metal type.
331, Oscillators, subclass 107 for superconductive element and tunneling element oscillators.

Josephson:
This subclass is indented under subclass 30. Subject matter wherein the device is of the form of a pair of superconductive electrodes separated by a thin, less conductive, portion, through which superconductive tunneling may occur.

SEE OR SEARCH CLASS:
29, Metal Working, subclass 25.01 for methods of making barrier layer devices possessing a Josephson junction.
216, Etching a Substrate: Processes, subclass 3 for Josephson Junction device manufacture involving etching.
505, Superconductor Technology: Apparatus, Material, Process, subclass 1 for high temperature superconductor Josephson devices with particular electrode materials and pertinent cross-reference art collections, including subclasses 857+ for nonlinear solid-state device, system, or circuit; and subclasses 873+ active solid-state devices.

Particular electrode material:
This subclass is indented under subclass 31. Subject matter wherein the electrode material is specified.

High temperature (i.e., >30 deg. Kelvin):
This subclass is indented under subclass 32. Subject matter wherein the device can operate at temperatures above 30 degrees on the Kelvin temperature scale.

SEE OR SEARCH CLASS:
505, Superconductor Technology: Apparatus, Material, Process, subclass 1 for high temperature superconductor materials and devices.

Weak link (e.g., narrowed portion of superconductive line):
This subclass is indented under subclass 31. Subject matter wherein the active layer is a superconductive material of lower current capacity than the pair of superconductive electrodes.

Particular barrier material:
This subclass is indented under subclass 31. Subject matter wherein the active layer material is specified.

With additional electrode to control conductive state of Josephson junction:
This subclass is indented under subclass 31. Subject matter wherein a specific electrode in addition to the pair of superconductive electrodes forming the Josephson junction is used to control the conductive state of the junction.

At least one electrode layer of semiconductor material:
This subclass is indented under subclass 30. Subject matter wherein the tunneling device has at least one electrode layer comprised of a semiconductive material.

Three or more electrode device:
This subclass is indented under subclass 37. Subject matter wherein the tunneling device has three or more electrodes, at least one of which is made of a semiconductive material.

Three or more electrode device:
This subclass is indented under subclass 30. Subject matter wherein the tunneling device has three or more electrodes.

ORGANIC SEMICONDUCTOR MATERIAL:
This subclass is indented under the class definition. Subject matter comprising a semiconductor compound that includes an organic material characterized by two or more carbon atoms bonded together, one atom of carbon bonded to at least one atom of hydrogen or halogen (i.e., chlorine, fluorine, bromine, iodine), or one atom of carbon bonded to at least one atom of nitrogen by a single or double bond.
(1) Note. Certain compounds are exceptions to this rule,
i.e., HCN, CN-CN, HNCO, HNCS, cyanogen halides, cyanamide, fulminic acid, and metal carbides. These are not regarded as organic materials.
(2) Note. Graphite and diamond are not regarded as organic, since they are not compounds; silicon carbide is not regarded as organic. Active solid-state devices using silicon carbide or diamond as the semiconductor are in subclass 77 of this class.
(3) Note. Organic insulating materials, as opposed to semiconducting materials, do not go in this subclass.

SEE OR SEARCH CLASS:
136, Batteries: Thermoelectric and Photoelectric, subclass 263 for photoelectric cells containing organic active material.
260, Chemistry of Carbon Compounds, and other classes which form integral parts of Class 260, appropriate subclasses for organic materials
313, Electric Lamp and Discharge Devices, subclass 504 for solid-state organic phosphor material luminescent devices.
361, Electricity: Electrical Systems and Devices, subclass 527 for solid electrolytic capacitors containing an organic salt.
438, Semiconductor Device Manufacturing: Process, subclass 82 for processes of making a light responsive device utilizing an organic semiconductor, and subclass 99 for methods of making an electrical device utilizing as a semiconductor component an organic semiconductor.

POINT CONTACT DEVICE:
This subclass is indented under the class definition. Subject matter including a junction between a semiconductor and a metallic element (e.g., wire) at a single point of contact therebetween.

SEMICONDUCTOR IS SELENIUM OR TELLURIUM IN ELEMENTAL FORM:
This subclass is indented under the class definition. Subject matter including a semiconductor material comprised of selenium or tellurium in elemental form (i.e., not in a compound).

SEE OR SEARCH CLASS:
430, Radiation Imagery Chemistry: Process, Composition or Product, subclass 57.8 for electrophotographic plates containing selenium or a selenium alloy.

SEMICONDUCTOR IS AN OXIDE OF A METAL (E.G., CuO, ZnO) OR COPPER SULFIDE:
This subclass is indented under the class definition. Subject matter wherein a semiconductor material includes a metal oxide or copper sulfide.
(1) Note. Those variable resistors known as "coherers" which are active solid-state devices, and are made of a metal oxide, are found in this subclass.

SEE OR SEARCH THIS CLASS, SUBCLASS:
798 for other active solid-state device type coherers.

SEE OR SEARCH CLASS:
338, Electrical Resistors, subclass 1 and 223+ for passive solid-state coherers.
438, Semiconductor Device Manufacturing: Process, subclass 85 for processes of making a light responsive device utilizing as the semiconductive component a metal oxide or copper sulfide and subclasses 104 for methods of forming an electrical device utilizing as a semiconductive component a metal oxide or copper sulfide.

WITH METAL CONTACT ALLOYED TO ELEMENTAL SEMICONDUCTOR TYPE PN JUNCTION IN NONREGENERATIVE STRUCTURE:
This subclass is indented under subclass 107. Subject matter under the class definition wherein the active solid-state device has a pn junction formed by alloying one or more impurity metal contacts to an elemental semiconductor, and wherein the active solid-state device is not a regenerative device of this class.
(1) Note. The impurity metal contact alloys with a semiconductor material to form a p-region or n-region, depending on the impurity used.

Elongated alloyed region (e.g., thermal gradient zone melting, TGZM):
This subclass is indented under subclass 44. Subject matter wherein the alloyed region has at least one dimension substantially larger than another.

In pn junction tunnel diode (Esaki diode):
This subclass is indented under subclass 44. Subject matter wherein the alloyed pn junction device is a tunnel diode, i.e., wherein the active solid-state device includes a heavily doped pn junction wherein conduction occurs through the junction potential barrier due to a quantum mechanical effect even though the carriers which tunnel through the potential barrier do not have enough energy to overcome the barrier potential.

In bipolar transistor structure:
This subclass is indented under subclass 44. Subject matter wherein the alloyed pn junction device is a bipolar transistor, i.e., a transistor structure whose working current passes through semiconductor material of both polarities (p and n).

TEST OR CALIBRATION STRUCTURE:
This subclass is indented under the class definition. Subject matter in which structures are provided on active solid-state devices to permit or facilitate the measurement, test, or calibration of the characteristics of the devices.
(1) Note. Active solid-state device standards are also included herein.

SEE OR SEARCH CLASS:
324, Electricity: Measuring and Testing, subclass 158 for semiconductor device test apparatus and methods.
438, Semiconductor Device Manufacturing: Process,
particularly subclass 18 for methods under the class definition having combined therewith a step of measuring an electrical condition utilizing a test element.

NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION):
This subclass is indented under the class definition. Subject matter wherein there is an active junction (e.g., a junction between dissimilar materials, or a junction induced by an applied electric field, which exhibits non-linear current-voltage characteristics) and at least part of the active junction is formed by a semiconductor material in polycrystalline or amorphous form.

SEE OR SEARCH CLASS:
136, Batteries: Thermoelectric and Photoelectric, subclass 258 for photoelectric cells with polycrystalline or amorphous semiconductor material.
438, Semiconductor Device Manufacturing: Process, particularly subclass 96 and 482+ for methods of depositing amorphous semiconductive material functioning as an active region for an electrical device and subclasses 97 and 488+ for methods of depositing polycrystalline semiconductive material functioning as an active region for an electrical device.

Non-single crystal, or recrystallized, active junction adapted to be electrically shorted (e.g., "anti-fuse" element):
This subclass is indented under subclass 49. Subject matter wherein the active junction is structured or arranged to form an electrical short circuit between the electrical terminals of the active device.

Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction):
This subclass is indented under subclass 49. Subject matter wherein the active junction is formed by both non-single
crystal material and single crystal material.

Amorphous semiconductor material:
This subclass is indented under subclass 49. Subject matter wherein the non-single crystal semiconductor material is amorphous, i.e., non-crystalline in the sense that (1) there is either complete disorder in the arrangement of atoms or molecules of the material or (2) there is an absence of any long range structural order that is detectable by electron or X-ray diffraction patterns of the material.

SEE OR SEARCH THIS CLASS, SUBCLASS:
2 through 5, for bulk effect switching in amorphous material.
16 for superlattice quantum well heterojunction devices of amorphous semiconductor material.
646 for amorphous semiconductor material coating to control surface effects.

SEE OR SEARCH CLASS:
136, Batteries: Thermoelectric and Photoelectric, subclass 258 for photoelectric cells with polycrystalline or amorphous semiconductor material.
438, Semiconductor Device Manufacturing: Process, particularly 482 for methods for depositing amorphous semiconductor.

Responsive to nonelectrical external signals (e.g., light):
This subclass is indented under subclass 52. Subject matter wherein the amorphous semiconductor active junction generates an electrical signal when subjected to non-electrical (e.g., optical, thermal, or vibratory) signals.

SEE OR SEARCH CLASS:
430, Radiation Imagery Chemistry: Process, Composition or Product, subclass 57.4 for electrophotographic plates containing amorphous silicon.

With Schottky barrier to amorphous material:
This subclass is indented under subclass 53. Subject matter wherein the amorphous semiconductor active junction is formed with a metal, thereby forming a Schottky barrier.

Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si[subscrpt]x[end subscrpt]Ge[subscrpt]1-x[end subscrpt], SiN[subscrpt]y[end subscrpt]):
This subclass is indented under subclass 53. Subject matter wherein the amorphous semiconductor is an alloy or contains material to change the band gap of the amorphous semiconductor material (e.g., Si[subscrpt]x[end subscrpt]Ge[subscrpt]1-x [end subscrpt]see below, SiN[subscrpt]y[end subscrpt]).

SEE OR SEARCH THIS CLASS, SUBCLASS:
63 for this subject matter except in a device which is not responsive to nonelectrical external signals.

With impurity other than hydrogen to passivate dangling bonds (e.g., halide):
This subclass is indented under subclass 53. Subject matter wherein the amorphous semiconductor material is doped with an impurity other than hydrogen (e.g., a halide) for providing electrical stability by completing chemical bonds between semiconductor atoms which were not completed due to the amorphous nature of the semiconductor active layer material.

Field effect device in amorphous semiconductor material:
This subclass is indented under subclass 52. Subject matter wherein the amorphous semiconductor active junction is a field effect device, i.e., one which has a conducting channel and two or more electrodes, one of which is denoted a source and the other a drain electrode, and in which the current through the conducting channel is controlled by an electric field coming from a voltage which is applied between the gate and source terminals thereof.
(1) Note. See illustration under subclass 213 for various field effect devices.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 149 for methods of forming a field effect transistor on an insulating substrate or layer (e.g., SOS, SOI, etc.).

With impurity other than hydrogen to passivate dangling bonds (e.g., halide):
This subclass is indented under subclass 57. Subject matter wherein the semiconductor active junction amorphous field effect device is doped with an impurity other than hydrogen (e.g., a halide) for providing electrical stability by completing chemical bonds between semiconductor atoms which were not completed due to the amorphous nature of the semiconductor active layer material.

In array having structure for use as imager or display, or with transparent electrode:
This subclass is indented under subclass 57. Subject matter wherein a plurality of semiconductor active junction amorphous field effect devices are interconnected in a monolithic chip device for generating an image of an object, light from which is incident on the device, or for displaying signals applied to the device, or having an electrode that transmits optical radiation in the infrared, visible, or ultraviolet wavelength bands.

With field electrode under or on a side edge of amorphous semiconductor material (e.g., vertical current path):
This subclass is indented under subclass 57. Subject matter wherein the semiconductor active junction amorphous field effect device has an electrode located under or on a side edge of the device to affect the current path through the device (e.g., providing a vertical current path).

With heavily doped regions contacting amorphous semiconductor material (e.g., heavily doped source and drain):
This subclass is indented under subclass 57. Subject matter wherein the semiconductor active junction amorphous field effect device has regions in contact with the amorphous material which contain dopant ions with relatively heavy concentrations (e.g., 10[supscrpt]18[end supscrpt] to 10[supscrpt]21[end supscrpt] dopant atoms per cubic centimeter).

With impurity other than hydrogen to passivate dangling bonds (e.g., halide):
This subclass is indented under subclass 52. Subject matter wherein the semiconductor active junction amorphous field effect device is doped with an impurity other than hydrogen (e.g., a halide) for providing electrical stability by completing chemical bonds between semiconductor atoms which were not completed due to the amorphous nature of the semiconductor active layer material.

Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si[subscrpt]x[end subscrpt]Ge[subscrpt]1-x[end subscrpt], SiN[subscrpt]y[end subscrpt]):
This subclass is indented under subclass 52. Subject matter wherein the amorphous semiconductor material is an alloy or contains material to change the energy gap between the valence and conduction bands.

SEE OR SEARCH THIS CLASS, SUBCLASS:
55 for this subject matter in a device which is responsive to nonelectrical external signals.

Non-single crystal, or recrystallized, material with specified crystal structure (e.g., specified crystal size or orientation):
This subclass is indented under subclass 49. Subject matter wherein the non-single crystal semiconductor material has a specified crystal structure, such as a specified grain size,
a preferred crystallos:graphic axis, or orientation; polycrystalline material in the form of elongated crystallites; or particular configuration of grain boundaries.

Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., Ge[subscrpt]x[end subscrpt]Si[subscrpt]1-[end subscrpt]x, polycrystalline silicon with dangling bond modifier):
This subclass is indented under subclass 49. Subject matter wherein the non-single crystal semiconductor is an alloy or contains an additive other than an electrically active dopant, such as a dangling bond passivator or an additive to change the band gap of the amorphous semiconductor material (e.g., Si[subscrpt]x[end subscrpt]Ge[subscrpt]1-x[end subscrpt], SiN[subscrpt]y[end subscrpt]).

Field effect device in non-single crystal, or recrystallized, Semiconductor material:
This subclass is indented under subclass 49. Subject matter wherein the active solid-state device is a field effect device, i.e., one which operates with the application of a voltage across electrical terminals thereof.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 149 for methods of forming a field effect transistor on an insulating substrate or layer (e.g., SOS, SOI, etc.).

In combination with device formed in single crystal semiconductor material (e.g., stacked FETs):
This subclass is indented under subclass 66. Subject matter wherein the field effect device is combined with an active or passive solid-state device located in a single crystal semiconductor material (i.e., one in which atoms are arranged in a regular three dimensional array).

Capacitor element in single crystal semiconductor (e.g., DRAM):
This subclass is indented under subclass 67. Subject matter wherein the device is a capacitor element in single crystal material.

Field effect transistor in single crystal material, complementary to that in non-single crystal, or recrystallized, material (e.g., CMOS):
This subclass is indented under subclass 67. Subject matter wherein there is a field effect transistor in single crystal material complementary in polarity to the field effect device in the non-single crystal, or recrystallized, material (e.g., a CMOS device).

Recrystallized semiconductor material:
This subclass is indented under subclass 67. Subject matter wherein the combined device contains a non-single semiconductor region of recrystallized material.
(1) Note. Recrystallized semiconductor material has been processed, typically by heat or laser irradiation to cause growth of large regions of substantially single crystal material to obtain properties approximating those of completely single crystal material.

In combination with capacitor element (e.g., DRAM):
This subclass is indented under subclass 66. Subject matter wherein the field effect device in the non-single crystal, or recrystallized, semiconductor material is combined with a capacitor element.

In array having structure for use as imager or display, or with transparent electrode:
This subclass is indented under subclass 66. Subject matter wherein a plurality of field effect devices in non-single crystal, or recrystallized, semiconductor material are interconnected in a monolithic chip device for generating an image of an object, light from which is incident on the device, or for displaying signals applied to the device, or having an electrode that transmits optical radiation in the infrared, visible, or ultraviolet wavelength bands.

Schottky barrier to polycrystalline semiconductor material:
This subclass is indented under subclass 49. Subject matter wherein the device contains a non-ohmic, rectifying metal-to-polycrystalline bulk material electrical contact.

Plural recrystallized semiconductor layers (e.g., "3-dimensional integrated circuit"):
This subclass is indented under subclass 49. Subject matter wherein the recrystallized material comprises more than one layer of recrystallized semiconductor material.

Recrystallized semiconductor material:
This subclass is indented under subclass 49. Subject matter wherein the device contains a non-single crystal semiconductor material whose amorphous nature is due to recrystallization.

SPECIFIED WIDE BAND GAP (1.5eV) SEMICONDUCTOR MATERIAL OTHER THAN GaAsP or GaAlAs:
This subclass is indented under the class definition. Subject matter including a semiconductor material with a band gap (between its valance and conduction bands) greater that 1.5 electron volts which is not gallium arsenide phosphide or gallium aluminum arsenide.

Diamond or silicon carbide:
This subclass is indented under subclass 76. Subject matter wherein the specified wide band gap material is diamond or silicon carbide.

II-VI compound:
This subclass is indented under subclass 76. Subject matter wherein the specified wide band gap material is a compound, one element of which comes from group II, and the other element of which comes from group VI of the periodic table of elements.

INCOHERENT LIGHT EMITTER STRUCTURE:
This subclass is indented under the class definition. Subject matter wherein the active solid-state device generates incoherent light when subjected to an appropriate input signal.
(1) Note. Lasers (coherent light generators) are classified in Class 372, and patents directed to lasers are not to be cross-referenced in this or indented subclasses unless such patent contains disclosure of a light emitting semiconductor device which is NOT a laser or coherent light generator.

SEE OR SEARCH THIS CLASS, SUBCLASS:
13 for incoherent thin physical layer light emitter devices with operating principles as specified therein.

SEE OR SEARCH CLASS:
250, Radiant Energy, 552 for solid-state light source circuits.
313, Electric Lamp and Discharge Devices, 498 for electric lamp and discharge devices having solid-state luminescent materials, including nominally recited luminescent semiconductor type materials; and subclass 504 for solid-state organic phosphor material luminescent devices.
340, Communications: Electrical, 760 and 766+ for solid-state light emitting arrays and array elements.
362, Illumination, subclass 84 for light source or light source support and luminescent material and subclass 800
(cross-reference art collection) for light emitting diode light sources.
438, Semiconductor Device Manufacturing: Process, particularly 22 for methods of forming a semiconductor device which may be emissive of either coherent or incoherent radiation.

In combination with or also constituting light responsive device:
This subclass is indented under subclass 79. Subject matter wherein the light emitting active semiconductor device is combined with a separate device which generates an electrical signal when light impinges upon it or the active device both emits light when stimulated and generates an electrical signal in response to light impingent thereupon.

SEE OR SEARCH CLASS:
250, Radiant Energy, subclass 551 for signal isolators involving a light source and photodetector.

With specific housing or contact structure:
This subclass is indented under subclass 80. Subject matter wherein the combined light emitting and light responsive device is provided with a particular housing or electrical contact structure.

Discrete light emitting and light responsive devices:
This subclass is indented under subclass 81. Subject matter wherein the device with a specific housing or contact structure contains separate light emitting and light responsive elements.

Light coupled transistor structure:
This subclass is indented under subclass 80. Subject matter wherein the active solid-state device has a pair of
rectifying junctions, a first of which when forward biased produces light which, when absorbed in the depletion region of the second junction when reverse biased, produces a current through the second junction, with the first junction functioning similarly to the emitter-base junction, and the second junction functioning similarly to the base-collector junction, of an ordinary bipolar transistor.

SEE OR SEARCH CLASS:
250, Radiant Energy, subclass 551 for signal isolator for optically coupled light emitter and light detector combinations wherein the devices are used to isolate electrical signals.

Combined in integrated structure:
This subclass is indented under subclass 80. Subject matter wherein the light emitting and light responsive devices are combined in a single crystal monolithic structure.

With heterojunction:
This subclass is indented under subclass 84. Subject matter wherein the device contains a heterojunction, i.e., wherein the junction separates semiconductor materials of different chemical composition.

Active layer of indirect band gap semiconductor:
This subclass is indented under subclass 79. Subject matter wherein the light emitting active region is in or between semiconductor materials in which direct transitions of electrons from conduction to valance bands do not take place.
(1) Note. Transitions may take place in steps due to trapping levels located in the forbidden band between the conduction and valance bands.

With means to facilitate electron-hole recombination (e.g.,
isoelectronic traps such as nitrogen in GaP):
This subclass is indented under subclass 86. Subject matter wherein the light emitting active region with an indirect band gap layer has means to facilitate electron-hole recombination (e.g., isoelectronic traps such as nitrogen in gallium phosphide).

Plural light emitting devices (e.g., matrix, 7-segment array):
This subclass is indented under subclass 79. Subject matter wherein the light emitting active semiconductor device contains more than one light emitting active junction.

SEE OR SEARCH CLASS:
340, Communications: Electrical, 760 and 766+ for solid-state light emitting arrays and array elements.

Multi-color emission:
This subclass is indented under subclass 88. Subject matter wherein different light emitting devices emit light of different hues.

With heterojunction:
This subclass is indented under subclass 89. Subject matter wherein there is at least one heterojunction, i.e., wherein the junction separates semiconductor materials of different chemical composition.

With shaped contacts or opaque masking:
This subclass is indented under subclass 88. Subject matter wherein the plural light emitting devices have electrical contacts with specific shapes or are combined with optical elements which are impervious to light emitted by the devices and are placed in the path of light emitted by the devices.

Alphanumeric segmented array:
This subclass is indented under subclass 88. Subject matter wherein the plural light emitting devices are structured and arranged in segments of Arabic numerals or alphabet letters.

SEE OR SEARCH CLASS:
340, Communications: Electrical, 760 and 766+ for solid-state light emitting arrays and array elements.

With electrical isolation means in integrated circuit structure:
This subclass is indented under subclass 88. Subject matter wherein means to provide electrical isolation, i.e., to prevent electrical short circuits, with respect to each light emitting device, are provided in a single, monolithic chip structure.

With heterojunction:
This subclass is indented under subclass 79. Subject matter wherein there is at least one junction between semiconductor materials of different chemical compositions.
(1) Note. See the illustration of a heterojunction device in subclass 183.

With contoured external surface (e.g., dome shape to facilitate light emission):
This subclass is indented under subclass 94. Subject matter wherein the light emitting device has an external surface with a particular geometric shape, for example, a dome shape to facilitate emission of light from the light emitting device, in spite of it being made of semiconductor material of relatively high index of refraction.

Plural heterojunctions in same device:
This subclass is indented under subclass 94. Subject matter wherein the heterojunction light emitting device has more than one heterojunction.

More than two heterojunctions in same device:
This subclass is indented under subclass 96. Subject matter wherein the light emitting device has more than two heterojunctions.

With reflector, opaque mask, or optical element (e.g., lens, optical fiber, index of refraction matching layer, luminescent material layer, filter) integral with device or device enclosure or package:
This subclass is indented under subclass 79. Subject matter wherein the light emitting active junction device is combined with one or more optical elements (e.g., to transmit or shape or otherwise affect light emitted by the device); and the optical element is an integral part of the device or of the housing, encapsulant, or other device enclosure or package.

With housing or contact structure:
This subclass is indented under subclass 79. Subject matter wherein the light emitting active junction device is combined with a housing or electrical contact structure.

Encapsulated:
This subclass is indented under subclass 79. Subject matter wherein the light emitting active junction device is embedded in a protective coating.

SEE OR SEARCH CLASS:
174, Electricity: Conductors and Insulators, subclass 52.2
for potted or encapsulated electrical devices.
439, Electrical Connectors, subclass 936 for potting material or coating for electrical conductors.

With particular dopant concentration or concentration profile (e.g., graded junction):
This subclass is indented under subclass 79. Subject matter wherein the light emitting active junction has a particular concentration of dopant ions or profile in a given direction or cross sectional area or volume.

With particular dopant material (e.g., zinc as dopant in GaAs):
This subclass is indented under subclass 79. Subject matter wherein the dopant material of the active junction is specified.

With particular semiconductor material:
This subclass is indented under subclass 79. Subject matter wherein the active junction is in or between semiconductor material whose composition is specified.

TUNNELING PN JUNCTION (E.G., ESAKI DIODE) DEVICE:
This subclass is indented under the class definition. Subject matter wherein the active solid-state device includes a heavily doped pn junction where conduction occurs through the junction potential barrier due to a quantum mechanical effect even though the carriers which tunnel through the potential barrier do not have enough energy to overcome the barrier potential.
(1) Note. PN Junction tunnel diodes operated under forward bias are often referred to as Esaki diodes.

SEE OR SEARCH THIS CLASS, SUBCLASS:
46 for an Esaki diode having a metal contact alloyed to elemental semiconductor type pn junction in a non-regenerative structure.

SEE OR SEARCH CLASS:
326, Electronic Digital Logic Circuitry, subclass 134 for a digital logic device which includes a tunnel diode.
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, subclass 195 for stable state circuits utilizing a tunnel diode; subclass 326 for limiting, clipping, or clamping using a tunnel diode; subclass 402 for a delay controlled switch with tunnel diode; subclasses 420 and 499 for gating circuits utilizing transistors or diodes respectively which use tunnel diodes; and subclass 570 for miscellaneous tunnel diode circuits.
331, Oscillators, subclass 107 for tunnel diode oscillators.
361, Electricity: Electrical Systems and Devices, subclass 100 for tunnel diode current responsive fault sensors.

In three or more terminal device:
This subclass is indented under subclass 104. Subject matter wherein the tunnel junction is part of an active solid-state electronic device which has three or more electrical terminals (e.g., transistors or thyristors).

Reverse bias tunneling structure (e.g., "backward" diode, true Zener diode):
This subclass is indented under subclass 104. Subject matter wherein the tunnel junction is structured to permit quantum mechanical tunneling of carriers in a reverse bias mode, i.e., when the p-side of the junction is connected to a negative voltage source and the n-side of the junction is connected to a positive voltage source.
(1) Note. In silicon, such conduction occurs when the junction breakdown voltage is less than approximately 5.6 volts.

SEE OR SEARCH CLASS:
148, Metal Treatment, digest 174 for treatment of Zener diodes.
323, Electricity: Power Supply or Regulation Systems, subclass 231 for systems using a Zener diode and being in shunt with a load.
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, subclass 194 and 195 for stable state circuits with a zener or back diode respectively; subclass 326 for limiting, clipping, or clamping utilizing a zener diode; subclass 421 for gating circuits having a transistor which utilizes a zener effect; subclass 502 for a gating circuit with zener diode; and subclass 584 for a miscellaneous circuit utilizing a zener diode.
361, Electricity: Electrical Systems and Devices, subclass 197, for relay time delay safety or protection devices including, for example, a Zener diode.
377, Electrical Pulse Counters, Pulse Dividers, or Shift Registers: Circuits and Systems, subclass 128 for pulse counting or dividing chains which include bi-stable semiconductor devices with only two electrodes, e.g., tunnel diodes.

REGENERATIVE TYPE SWITCHING DEVICE (E.G., SCR, COMFET, THYRISTOR):
This subclass is indented under the class definition. Subject matter wherein the active solid-state device acts as if it has two or more active emitter junctions each of which is associated with a separate, equivalent transistor having an individual gain and, when initiated by a base region current, the equivalent transistors mutually drive each other in a regenerative manner to lower the voltage drop between the emitters.
(1) Note. If the current is above a level I[subscrpt]H[end subscrpt], called the "holding current", then the device will remain ON when the triggering signal is removed by the regenerative feedback therebetween, and is then said to be "latched".

SEE OR SEARCH CLASS:
123, Internal-Combustion Engines, subclass 648 for circuits employing silicon controlled rectifiers (SCRs).
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, 199 for a bistable circuit which includes diverse solid-state devices such as an SCR, subclasses 392+ for a delay controlled switch which may include an SCR, and subclasses 438+ for gating circuits which may use a thyristor or SCR.
361, Electricity: Electrical Systems and Devices, 100 and 205 for circuits employing thyristors (e.g., silicon controlled rectifiers (SCRs)).
363, Electric Power Conversion Systems, 27, 54, 57+, 68, 85+, 96+, 128+, 135+, and 160+ for circuits employing thyristors (e.g., silicon controlled rectifiers (SCRs)).
388, Electricity: Motor Control Systems, 917 for circuits employing thyristors (e.g., silicon controlled rectifiers (SCRs)).
438, Semiconductor Device Manufacturing: Process, particularly 133 for methods of forming a regenerative type switching device.

Controlled by nonelectrical, nonoptical external signal (e.g., magnetic field, pressure, thermal):
This subclass is indented under subclass 107. Subject matter wherein the regenerative switching device is controlled by an input signal other than an optical or electrical signal (e.g., by a magnetic field) or by mechanical stress.

Having only two terminals and no control electrode (gate), e.g., Shockley diode:
This subclass is indented under subclass 107. Subject matter wherein the regenerative switching device has only two electrical terminals, neither one of which is a control electrode (e.g., gate or base electrode).

More than four semiconductor layers of alternating conductivity types (e.g., pnpnpn structure, 5 layer bidirectional diacs, etc.):
This subclass is indented under subclass 109. Subject matter wherein the two terminal device with no control electrode has more than four layers of semiconductor material, each layer having an electrical conductivity type (e.g., p-type or n-type) which differs from that of each adjacent layer.

Triggered by V[subscrpt]BO[end subscrpt] overvoltage means:
This subclass is indented under subclass 109. Subject matter wherein the two terminal device with no control electrode includes means to apply a voltage larger than the breakover voltage V[subscrpt]BO[end subscrpt] to initiate operation of the device.

With highly-doped breakdown diode trigger:
This subclass is indented under subclass 109. Subject matter wherein the two terminal device with no control electrode includes a diode portion which is heavily doped to decrease its breakdown voltage to trigger the device into operation.

With light activation:
This subclass is indented under subclass 107. Subject matter wherein the regenerative switching device is activated (e.g., turned on and/or off) by light impinging on a light sensitive portion of the device.

With separate light detector integrated on chip with regenerative switching device:
This subclass is indented under subclass 113. Subject matter wherein the light sensitive portion is separate from the regenerative switching device, and is contained in a physically separated area of a single, monolithic chip with the regenerative switching device.

With electrical trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.):
This subclass is indented under subclass 113. Subject matter wherein means are provided to amplify the electrical signal generated by the light sensitive portion, in order to trigger the regenerative switching device.

With light conductor means (e.g., light fiber or light pipe) integral with device or device enclosure or package:
This subclass is indented under subclass 113. Subject matter wherein the active semiconductor device is provided with means to conduct light (e.g., as light fiber or light pipe) to the light sensitive portion, and the light conductor means is an integral part of the device or of the housing, encapsulant or other device enclosure, or package.

In groove or with thinned semiconductor portion:
This subclass is indented under subclass 116. Subject matter wherein the light sensitive portion is located in a groove in the device or wherein it is covered by a relatively thin portion of semiconductor material.

With groove or thinned light sensitive portion:
This subclass is indented under subclass 113. Subject matter wherein the light sensitive portion is located in a groove in the surface of the device or is located close to the surface of the device in a thinned region of the device so that only a relatively thin portion of the device has to be traversed by light.

Bidirectional rectifier with control electrode (gate) (e.g., Triac):
This subclass is indented under subclass 107. Subject matter wherein the regenerative switching device has a control electrode, can conduct in both forward and reverse directions, and can be triggered into conduction by a pulse applied to its control electrode.

SEE OR SEARCH THIS CLASS, SUBCLASS:
110 for bidirectional rectifiers with no control electrode.

SEE OR SEARCH CLASS:
323, Electricity: Power Supply or Regulation Systems, subclass 240 and 325 for circuit having unidirectional elements with bidirectional pass.

Six or more semiconductor layers of alternating conductivity types (e.g., npnpnpn structure):
This subclass is indented under subclass 119. Subject matter wherein the bidirectional rectifier with control electrode contains six or more layers of semiconductor material, each of which has a different conductivity type, (e.g., n-type or p-type) which differs from that of each adjacent layer.

With diode or transistor in reverse path:
This subclass is indented under subclass 119. Subject matter wherein a diode (i.e., a device which passes current in only one direction) is connected to conduct current in one direction, with a regenerative switching device with a control electrode connected to conduct current in the other direction to produce a bi-directionally conducting regenerative switching device.

Lateral:
This subclass is indented under subclass 119. Subject matter wherein the bidirectional rectifier with control electrode is of the lateral type, i.e., when viewed in cross section, the two main electrodes (e.g., anode and cathode) are arranged horizontally, side-by-side in the same surface of the semiconductor body.

With trigger signal amplification (e.g., amplified gate):
This subclass is indented under subclass 119. Subject matter wherein the bidirectional rectifier with control electrode is combined with means to amplify the electrical signal applied to the control electrode to trigger the device.

Combined with field effect transistor structure:
This subclass is indented under subclass 119. Subject matter wherein the bidirectional rectifier with control electrode includes or is combined with a field effect transistor structure, i.e., a transistor in which the current through a conducting channel is controlled by an electric field coming from a voltage which is applied between the gate and source terminals thereof.
(1) Note. See illustration under subclass 213 for various field effect devices.

Controllable emitter shunting:
This subclass is indented under subclass 124. Subject matter wherein the field effect transistor structure is connected to shunt one of the emitter-base junctions of the regenerative structure under control of the voltage applied to the gate of the field effect transistor.

With means to separate a device into sections having different conductive polarity:
This subclass is indented under subclass 119. Subject matter wherein the bidirectional rectifier with control electrode has means separating portions thereof which have different conductive polarity.

Guard ring or groove:
This subclass is indented under subclass 126. Subject matter wherein the means to separate portions of the device having different conductive polarity is or includes a groove, or a guard ring, i.e., a pn junction region in the body of the device located and/or configured to reduce electric field strength at a given applied voltage.

Having overlapping sections of different conductive
polarity:
This subclass is indented under subclass 119. Subject matter wherein the bidirectional rectifier with control electrode has outer emitter regions which overlap one another in at least one portion.

With means to increase reverse breakdown voltage:
This subclass is indented under subclass 119. Subject matter wherein the bidirectional rectifier with control electrode has means associated therewith to increase the reverse voltage which may be applied without causing electrical breakdown.

Switching speed enhancement means:
This subclass is indented under subclass 119. Subject matter wherein the bidirectional rectifier with control electrode includes or is combined with means to increase the speed at which the device switches.

Recombination centers or deep level dopants:
This subclass is indented under subclass 130. Subject matter wherein the switching speed enhancement means include (1) centers wherein excess holes and electrons recombine and are removed as charge carriers in the device or (2) dopant ions with energy levels that are located in the forbidden band of the active semiconductor material of the device.

Five or more layer unidirectional structure:
This subclass is indented under subclass 107. Subject matter wherein the regenerative active solid-state device has five or more layers of semiconductor material producing at least four active junctions, and is operable in a single electrical direction.

Combined with field effect transistor:
This subclass is indented under subclass 107. Subject matter wherein the regenerative device includes or is combined with a field effect transistor, i.e., a transistor in which the current through a conducting channel is controlled by an electric field coming from a voltage which is applied between the gate and source terminals thereof.

J-FET (junction field effect transistor):
This subclass is indented under subclass 133. Subject matter wherein the field effect transistor combined with the regenerative action junction type switching device is a junction field effect transistor, i.e., a field effect transistor wherein the gate region is isolated from the conducting channel by a rectifying pn junction or Schottky barrier junction.

SEE OR SEARCH THIS CLASS, SUBCLASS:
287 for power JFET devices.
504 for JFET type isolation.

Vertical (i.e., where the source is located above the drain or vice versa):
This subclass is indented under subclass 134. Subject matter wherein the operating current path of the JFET is perpendicular to the plane of its main surface.

Enhancement mode (e.g., so-called SITs):
This subclass is indented under subclass 135. Subject matter in which no current flows except for leakage current, when the gate to source voltage is zero.
(1) Note. Conduction does not begin until the gate voltage reaches a finite threshold value.
(2) Note. Compare this with depletion mode J-FETS in which maximum current is passed by the transistor at a zero gate
potential and current decreases as the gate voltage increases.

Having controllable emitter shunt:
This subclass is indented under subclass 133. Subject matter wherein the regenerative switching device is combined with a junction field effect transistor that is connected across an emitter-base junction of the regenerative device to controllably divert current from the emitter-base junction.

Having gate turn off (GTO) feature:
This subclass is indented under subclass 137. Subject matter wherein the regenerative switch is configured to permit application of sufficient gate current to switch the regenerative switch to the OFF state.

With extended latchup current level (e.g., COMFET device):
This subclass is indented under subclass 133. Subject matter wherein the regenerative active junction type switching device (e.g., a conductivity modulated FET) includes means to provide regenerative action without latchup over an extended current range of the device (i.e., by increasing I[subscrpt]H[end subscrpt]).

Combined with other solid-state active device in integrated structure:
This subclass is indented under subclass 139. Subject matter wherein the extended latchup current level device is combined with another solid-state active device in a monolithic single crystal chip structure.

Lateral structure, i.e., current flow parallel to main device surface:
This subclass is indented under subclass 139. Subject matter wherein the extended latchup current level device is structured so that operating current flows parallel to the main device surface (i.e., horizontally or laterally).

Having impurity doping for gain reduction:
This subclass is indented under subclass 139. Subject matter wherein the extended latchup current level device has impurity dopant to reduce device regenerative gain, i.e., the gain or amplification of one or more of the active junction portions connected in regenerative fashion.

Having anode shunt means:
This subclass is indented under subclass 139. Subject matter wherein the extended latchup current level device has means connected across the emitter-base junction of the PNP transistor portion of the regenerative device to controllably divert current from the emitter-base junction.

Cathode emitter or cathode electrode feature:
This subclass is indented under subclass 139. Subject matter wherein the extended latchup current level device has a particular cathode emitter or cathode electrode feature.

Low impedance channel contact extends below surface:
This subclass is indented under subclass 139. Subject matter wherein the extended latchup current level device has an electrical contact extending from the device surface into the body of the device which is connected to the channel of the field effect transistor portion and wherein the contact has a relatively low electrical impedance.

Combined with other solid-state active device in integrated structure:
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction type switching device is combined with one or more active or passive electronic solid-state devices in a unitary, monolithic, integrated structure.

With extended latchup current level (e.g., gate turn off "GTO" device):
This subclass is indented under subclass 107. Subject matter wherein the regenerative switching device includes means to provide regenerative action without latchup over an extended current range of the device, i.e., extends I[subscrpt]H[end subscrpt] as defined in subclass 107.
(1) Note. Another name for this device is a gate controlled switch.

Having impurity doping for gain reduction:
This subclass is indented under subclass 147. Subject matter wherein the regenerative switching device has impurity dopant to reduce device gain of one of the equivalent transistors.

SEE OR SEARCH THIS CLASS, SUBCLASS:
142 for this subject matter in a COMFET device.

Having anode shunt means:
This subclass is indented under subclass 147. Subject matter wherein the regenerative switching device has means connected across the emitter-base junction of the PNP transistor section of the regenerative device to divert current from the emitter-base junction.

With specified housing or external terminal:
This subclass is indented under subclass 147. Subject matter wherein the regenerative switching device is provided with means to enclose it or a terminal means located external to an enclosure for the device.

External gate terminal structure or composition:
This subclass is indented under subclass 150. Subject matter wherein the external electrical terminal structural features or material composition is specified.

Cathode emitter or cathode electrode feature:
This subclass is indented under subclass 147. Subject matter wherein the extended latchup current level device has a particular cathode emitter or cathode electrode feature.

Gate region or electrode feature:
This subclass is indented under subclass 147. Subject matter wherein the extended latchup current level device has a particular gate (control) electrode feature.

With resistive region connecting separate sections of device:
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction type switching device has a resistive region or portion connecting discrete regions of the device.

With switching speed enhancement means (e.g., Schottky contact):
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction type switching device is provided with means to increase its switching
speed.

Having deep level dopants or recombination centers:
This subclass is indented under subclass 155. Subject matter wherein the regenerative device has deep level dopants or electron-hole recombination centers with energy levels that are within the forbidden energy band and widely spaced from the conduction and valence bands of the semiconductor device.

With integrated trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.):
This subclass is indented under subclass 107. Subject matter wherein the regenerative switching device has means to amplify the control current of the device, which is physically integrated with the regenerative switching device.

SEE OR SEARCH THIS CLASS, SUBCLASS:
115 for light activated regenerative devices with trigger signal amplification.
123 for bidirectional regenerative devices with trigger signal amplification.

SEE OR SEARCH CLASS:
330, Amplifiers, 250 for semiconductor amplifying devices (e.g., transistors

Three or more amplification stages:
This subclass is indented under subclass 157. Subject matter wherein the amplification means has three or more stages of amplification.

Transistor as amplifier:
This subclass is indented under subclass 157. Subject matter wherein the amplification means is a transistor (i.e., an active semiconductor device having three or more electrodes).

With distributed amplified current:
This subclass is indented under subclass 157. Subject matter wherein the regenerative device with amplification means produces amplified current which is distributed by electrodes to other portions of the device.

With a turn-off diode:
This subclass is indented under subclass 157. Subject matter wherein the regenerative device with amplification means is integrally provided with a diode, i.e., a solid-state active rectifying two terminal device, to bypass the amplifying stage(s), in order to switch OFF the regenerative device.

Lateral structure:
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction type switching device has a lateral structure, i.e., one in which the active junctions are arranged so that electric current flows from side to side, rather than from top to bottom of the device.

Emitter region feature:
This subclass is indented under subclass 107. Subject matter wherein the active emitter junction region of the regenerative device has a particular characteristic.

Multi-emitter region (e.g., emitter geometry or emitter ballast resistor):
This subclass is indented under subclass 163. Subject matter wherein the regenerative switching device has more than one emitter region.

SEE OR SEARCH THIS CLASS, SUBCLASS:
580 for bipolar transistors with emitter ballast resistors.

Laterally symmetric regions:
This subclass is indented under subclass 164. Subject matter wherein the plural emitters are located in regions of the device which are symmetrical in a horizontal direction.

Radially symmetric regions:
This subclass is indented under subclass 164. Subject matter wherein the plural emitters are located in regions of the device which are symmetrical extending radially in a horizontal direction from a predetermined emitter location.

Having at least four external electrodes:
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction switching device has at least four electrodes connected to the outside of the device.

With means to increase breakdown voltage:
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction type switching device includes means to increase the reverse voltage which the device can sustain without breaking down.

High resistivity base layer:
This subclass is indented under subclass 168. Subject matter wherein the means for increasing breakdown voltage includes a base (as contrasted with emitter or collector) layer which has a relatively high electrical resistivity.

Surface feature (e.g., guard ring, groove, mesa, etc.):
This subclass is indented under subclass 168. Subject matter wherein the means for increasing breakdown voltage includes a surface feature (e.g., a guard ring or groove or mesa).

Edge feature (e.g., beveled edge):
This subclass is indented under subclass 170. Subject matter wherein the surface feature for increasing breakdown voltage is an edge feature (e.g., a beveled) as contrasted with a right angled edge.

With means to lower "ON" voltage drop:
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction type switching device comprises means to lower the voltage drop across the main terminals when the switch is operated in the ON mode.

Device protection (e.g., from overvoltage):
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction type switching device includes means for protecting the device from destructive overloads (e.g., from operating voltage above a particular threshold level).

SEE OR SEARCH CLASS:
361, Electricity: Electrical Systems and Devices, 91.1 for overvoltage protection in safety and protection of systems and devices.

Rate of rise of current (e.g., dI/dt):
This subclass is indented under subclass 173. Subject matter wherein the parameter for which protection means is provided is the rate of rise of operating current in the device.

With means to control triggering (e.g., gate electrode configuration, Zener diode firing, dV/Dt control, transient control by ferrite bead, etc.):
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction type switching device includes means for controlling device turn-on.
(1) Note. Transient electrical phenomena, e.g., damped oscillations or surges in operation current or voltage following a sudden change in the applied voltage or current to the device, may be controlled, for example, by use of ferrite bead or capacitive input means.

Located in an emitter-gate region:
This subclass is indented under subclass 175. Subject matter wherein the signal control mechanism is a transistor emitter junction with the gate region, and is used as the gate input.

With housing or external electrode:
This subclass is indented under subclass 107. Subject matter wherein the regenerative active junction type switching device includes a structure in which to place the device.

SEE OR SEARCH THIS CLASS, SUBCLASS:
81 and 82, for a light emitting device in combination with or constituting a light responsive device, with specific housing structure.
99 for light emitting device with specific housing structure.
433 and 434, for light responsive device with housing or
encapsulation means.
573 for Darlington configuration bipolar transistor structure with housing or contact structure.
584 for enlarged emitter device bipolar transistor means having housing or contact.
602 for a voltage variable capacitance device with specified housing or contact.
660 for means to shield a device contained in a housing.

With means to avoid stress between electrode and active device (e.g., thermal expansion matching of electrode to semiconductor):
This subclass is indented under subclass 177. Subject matter wherein the device has electrode means connected to its terminals and is further provided with means to avoid creation of stress between the active device and the electrode means.
(1) Note. The means to avoid such stress may include means to thermally match the electrode to the semiconductor.

SEE OR SEARCH CLASS:
439, Electrical Connectors, 449 for stress relief means for a conductor-to-terminal joint.

With malleable electrode (e.g., silver electrode layer):
This subclass is indented under subclass 178. Subject matter wherein the electrode means is soft and pliable.

Stud mount:
This subclass is indented under subclass 177. Subject matter wherein the housing is provided with a threaded or serrated insert or post used for connecting heat sinks or terminals to the device.

With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element, (e.g., ring):
This subclass is indented under subclass 177. Subject matter wherein the housing is provided with large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element (e.g., ring).

With lead feedthrough means on side of housing:
This subclass is indented under subclass 181. Subject matter wherein means are provided on a side of the housing through which electrical leads extending to or from the device can be located.

HETEROJUNCTION DEVICE:
This subclass is indented under the class definition. Subject matter wherein the active solid-state device contains a heterojunction, i.e., a boundary between different regions, one of which is made of a material that differs from that of the other region.
(1) Note. See illustration, below, for an example of a heterojunction bipolar transistor. [figure]

SEE OR SEARCH THIS CLASS, SUBCLASS:
10 and 11, for a heterojunction involving a low workfunction layer for electron emission.
12 through 27, for heterojunction devices which involve quantum well, superlattice or ballistic (hot carrier) transport devices.
51 for a non-single crystal material/monocrystal heterojunction device.
85 for a light emitting structure device combined with a light responsive device in an integrated structure wherein the light responsive device has a heterojunction.
90 for plural light emitting heterojunction devices.
94 through 97, for heterojunction light emitter structures.
193 for a heterojunction charge transfer device.

SEE OR SEARCH CLASS:
372, Coherent Light Generators, subclasses 43-50 for semiconductor lasers which may contain heterojunctions.

Charge transfer device:
This subclass is indented under subclass 183. Subject matter in which storage sites for packets of electric charge are induced at or below the surface of the active solid-state (semiconductor) device by an electric field applied to the device and wherein carrier potential energy per unit charge minima is established at a given storage site and such minima is transferred to one or more adjacent storage sites in a serial manner and which contains a junction between two semiconductor materials of different chemical compositions each different composition having a different carrier affinity.
(1) Note. Typically, heterojunctions are between materials which additionally have different band gaps, but that is not true of all heterojunctions.

SEE OR SEARCH THIS CLASS, SUBCLASS:
215 for charge transfer devices which do not involve heterojunctions.

Light responsive structure:
This subclass is indented under subclass 183. Subject matter wherein the heterojunction generates an electrical output when light impinges on it.

Staircase (including graded composition) device:
This subclass is indented under subclass 184. Subject matter wherein the active region contains a number of layers forming plural heterojunctions and the carrier (i.e., electron or hole) affinities of each layer incrementally increase or decrease progressively across the active region thickness, so that the energy level diagram of the active region, when
under electrical bias, resembles a staircase.
(1) Note. Staircase effect devices may also be provided with a graded composition, i.e., wherein the chemical composition of the semiconductor forming the heterojunction varies in a direction either perpendicular or parallel to the junction.
(2) Note. See illustration, below, for an example of a staircase bandgap. [figure]

Avalanche photodetection structure:
This subclass is indented under subclass 184. Subject matter wherein carriers generated in the active region of the device in response to light incident thereupon, achieve enough kinetic energy to knock further carriers from the crystalline lattice of the active region producing an avalanche or snowball increase in operating current level.
(1) Note. Avalanche photodetector devices may have bipolar transistor structure, i.e., wherein the heterojunction device has three terminals - an emitter, a collector and a base, the operating current comprising both positive and negative electrical charges.

Having transistor structure:
This subclass is indented under subclass 184. Subject matter wherein the light responsive heterojunction device has three terminals - an emitter, collector, and a base; a source, drain, and gate; or a hybrid combination of each, which can provide gain or can be used as a switch.

Having narrow energy band gap (<<1eV) layer (e.g., PbSnTe, HgCdTe, etc.):
This subclass is indented under subclass 184. Subject matter wherein the light responsive device contains a narrow energy band gap (<<1eV) layer (e.g., PbSnTe or HgCdTe).

Layer is a group III-V semiconductor compound:
This subclass is indented under subclass 188. Subject matter wherein the narrow energy band gap layer is a semiconductor compound made of one element taken from periodic table group III elements and another element taken from periodic table group V elements.

With lattice constant mismatch (e.g., with buffer layer to accommodate mismatch):
This subclass is indented under subclass 183. Subject matter wherein at least one of the materials that form the heterojunction has a crystalline lattice constant which is made to differ from the lattice constant of the other material which forms the heterojunction.
(1) Note. Typically, lattice mismatches are sought to be avoided. However, sometimes they are desired, as for example, when the resulting strain favorably affects the properties of the strained semiconductor.
(2) Note. A buffer layer may be provided to accommodate a lattice mismatch, i.e., a layer of material which mechanically separates the layers which have different lattice constants.

SEE OR SEARCH THIS CLASS, SUBCLASS:
18 for strained layer heterojunctions in a superlattice.

Having graded composition:
This subclass is indented under subclass 183. Subject matter wherein the chemical composition of the semiconductor forming the heterojunction varies continuously in a direction either perpendicular or parallel to the junction.

Field effect transistor:
This subclass is indented under subclass 183. Subject matter wherein the heterojunction is part of a field effect transistor, i.e., wherein the current through the active heterojunction is controlled by a voltage applied between gate and source terminals of the device.

Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT)):
This subclass is indented under subclass 192. Subject matter wherein the heterojunction field effect transistor has impurity dopant on the side of the heterojunction with lower affinity for the charge carriers (holes or electrons) supplied by the dopant, so that the charge carriers spill over the heterojunction into the side with higher carrier affinity.
(1) Note. Typically, the spilled over charge carriers constitute the conductive channel connecting the source and drain electrodes.
(2) Note. Such devices may be provided with a channel layer of semiconductor material other than group III-V compound semiconductor (e.g., IV-VI compound semiconductor, germanium semiconductor, etc.).

SEE OR SEARCH THIS CLASS, SUBCLASS:
12 through 27, for other closely related quantum well and ballistic transport field effect devices.

Combined with diverse type device:
This subclass is indented under subclass 194. Subject matter wherein the heterojunction field effect transistor with impurity dopant on the side of the heterojunction with lower affinity for the charge carriers supplied by the dopant is combined with another electronic device.
(1) Note. Typical diverse devises include complementary field effect transistors, i.e., a field effect transistor of opposite conductivity type to the heterojunction field effect transistor; and field effect transistors of different threshold voltages (e.g., enhancement and depletion HEMTs in same integrated circuit).

Both semiconductors of the heterojunction are the same conductivity type (i.e., either n or p):
This subclass is indented under subclass 183. Subject matter
wherein the semiconductor materials which define the heterojunction are of the same conductivity type (e.g., both p or both n).

Bipolar transistor:
This subclass is indented under subclass 183. Subject matter wherein the heterojunction is part of a bipolar transistor, i.e., a transistor structure whose working current passes through semiconductor material of both polarities (p and n) which form a heterojunction portion of the transistor.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 312 for methods of forming a heterojunction bipolar transistor.

Wide band gap emitter:
This subclass is indented under subclass 197. Subject matter wherein the bipolar transistor with an active heterojunction region involves a charge carrier emitter region made of a semiconductor material having an energy gap between its conduction and valence bands which is greater than the energy gap of the base region forming a heterojunction therewith.

Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts, including heterojunction IMPATT type microwave diodes):
This subclass is indented under subclass 183. Subject matter wherein the heterojunction device is a diode in which conduction under reverse bias conditions is caused by avalanche breakdown at an applied voltage greater than 6 volts.
(1) Note. One example of such a device is a microwave transit time device (e.g., IMPATT diode).

SEE OR SEARCH THIS CLASS, SUBCLASS:
481 for a Schottky barrier avalanche diode.
551 for an avalanche diode used as a voltage reference
element combined with pn junction isolation means in an integrated circuit.
603 through 606, for avalanche diodes not classified above those subclasses in this schedule, i.e., not involving a heterojunction in a non-charge transfer device, or a Schottky barrier, or one used as a voltage reference element with pn junction isolation means in an integrated circuit.

SEE OR SEARCH CLASS:
331, Oscillators, 107 for solid-state active element oscillators.

Heterojunction formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., Ge (group IV) - GaAs (group III-V) or InP (group III-V) - CdTe (group II-VI)):
This subclass is indented under subclass 183. Subject matter wherein the heterojunction is formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., Ge (group IV) - GaAs (group III-V) or InP (group III-V) - CdTe (group II-VI)).

Between different group IV-VI or II-VI or III-V compounds other than GaAs/GaAlAs:
This subclass is indented under subclass 183. Subject matter wherein the heterojunction forms a boundary between different group IV-VI or group II-VI or group III-V compounds other than GaAs/GaAlAs.

GATE ARRAYS:
This subclass is indented under the class definition. Subject matter comprising a repeating geometric arrangement of individual structural units of solid-state devices, the solid-state devices of each individual structural unit being connectable into various different types of logic circuits in one integrated, monolithic chip.
(1) Note. The significant distinction between a "gate array" and other arrays of active solid state devices, such as read-only memories (ROMs), and programmable logic arrays
(PLAs), is that the solid-state devices of each individual structural of a "gate array" can be connected into various different types of logic circuits, whereas in a ROM or PLA, each of the individual structural units is configured so that they must be connected into the same type of logic circuit (e.g., wherein all individual structural units are connected as NOR gates).

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 128 for methods of forming an array of devices upon a semiconductor substrate and selectively interconnecting the same.

With particular chip input/output means:
This subclass is indented under subclass 202. Subject matter wherein the gate array integrated circuit is provided with specific means to input and output electrical signals to operate the device.
(1) Note. Examples of particular chip input/output means include (a) interface circuits, i.e., circuits that connect the chip to another device or to a circuit and which produces necessary current and voltage characteristics for the interconnected devices and circuits to function properly, with particular active solid-state devices used in the interface circuits; (b) structure permitting electrical interconnection to either receive an input signal or to output an output signal; or (c) specific bonding pad or electrode configurations (i.e., wherein the input/output means includes a particular electrically conductive surface to which electrical interconnecting element (e.g., electrical leads) can be connected, or has a specified electrode configuration such as a power supply bus for the input/output means separate from those used to power the gate array devices.

Having specific type of active device (e.g., CMOS):
This subclass is indented under subclass 202. Subject matter wherein the gate array is adapted to use a particular type of solid-state electronic device, e.g., complementary metal oxide semiconductor device (CMOS).

With bipolar transistors or with FETs of only one channel conductivity type (e.g., enhancement-depletion FETs):
This subclass is indented under subclass 202. Subject matter wherein the specific type of active device comprises bipolar transistors or FETs of only one channel conductivity type (i.e, field effect transistors that can be used in the enhancement or depletion mode of operation, e.g., IGFETS).

Particular layout of complementary FETs with regard to each other:
This subclass is indented under subclass 204. Subject matter wherein the CMOS device includes a plurality of CMOS field effect transistors specifically arranged with regard to each other.

With particular power supply distribution means:
This subclass is indented under subclass 202. Subject matter wherein the gate array is provided with specific means to provide electrical power to the array.

With particular signal path connections:
This subclass is indented under subclass 202. Subject matter wherein the gate array is provided with specific signal path connections.

Programmable signal paths (e.g., with fuse elements, laser programmable, etc):
This subclass is indented under subclass 208. Subject matter wherein the gate array is provided with means (e.g., fuse elements or laser beam irradiation) to program the selection of signal paths in the array.

With wiring channel area:
This subclass is indented under subclass 208. Subject matter wherein the signal paths in the array are located in an area separate from the active devices forming the elements of the array.

Multi-level metallization:
This subclass is indented under subclass 208. Subject matter wherein the particular signal path connections include more than one layer of conductive metal deposited on a substrate.
(1) Note. The multilayer metallization may include a layer of material made up of silicon in polycrystalline form or a silicide compound.

CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE-BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR):
This subclass is indented under the class definition. Subject matter wherein the active solid-state device has a high resistivity semiconductor region of one conductivity type having a region of opposite conductivity type forming a pn junction with a central portion of the high resistivity layer, with structural means provided to forward bias the pn junction to inject minority carriers into the high resistivity region to increase its conductivity through conductivity modulation.

SEE OR SEARCH CLASS:
327, Miscellaneous Active Electrical Nonlinear Devices, Circuits, and Systems, subclass 397 and 402 for a delay controlled switch using a unijunction transistor and having a variable or fixed delay respectively; subclasses 438+ for gating circuits utilizing a unijunction transistor, and subclass 569 for a miscellaneous circuit which utilizes a unijunction transistor.
361, Electricity: Electrical Systems and Devices, subclass 91.3 for overvoltage protection with time delay, and subclass 198 for time delay with unijunction devices.
388, Electricity: Motor Control Systems, subclass 919 for unijunction transistor circuit trigger control means.

FIELD EFFECT DEVICE:
This subclass is indented under the class definition. Subject matter comprising a field effect transistor, in which the density of electrical charge (electrons or holes) in a semiconductor region is controlled by a voltage applied to an adjacent region or electrode which in operation is prevented from conducting direct electrical current to or from the semiconductor region by an insulator or barrier region.
(1) Note. The conduction of current in a field effect device is along a path called a channel.
(2) Note. See Illustration, below, for various types of field effect devices. [figure]

SEE OR SEARCH CLASS:
331, Oscillators, subclass 116 and 117 for field effect transistor oscillator active elements.
341, Coded Data Generation or Conversion, subclass 136 for analog to or from digital conversion devices with a field effect transistor.

Charge injection device:
This subclass is indented under subclass 213. Subject matter wherein the field effect device is a device in which storage sites for packets of electric charge are induced at or below the surface of the active solid-state (semiconductor) device by an electric field applied to the device and wherein carrier potential energy per unit charge minima are established at a given storage site and such charge packets are injected into the device substrate or into a data bus.
(1) Note. This type device differs from a charge transfer device in that, in the latter, charge is transferred to adjacent charge storage sites in a serial manner whereas in the former, the charge is injected in a non-serial manner to the device substrate or a data bus.

Charge transfer device:
This subclass is indented under subclass 213. Subject matter in which storage sites for packets of electric charge are
induced at or below the surface of the active solid-state (semiconductor) device by an electric field applied to the device and wherein carrier potential energy per unit charge minima are established at a given storage site and such minima are transferred to one or more adjacent storage sites in a serial manner.

SEE OR SEARCH THIS CLASS, SUBCLASS:
193 for heterojunction type charge transfer devices.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, subclass 60 for methods of making a photo-responsive semiconductor integrated circuit having a charge transfer device combined with another electrical device, subclasses 75+ for methods of making a photoresponsive charge transfer device, and subclasses 144+ for methods of making a charge transfer device.

Majority signal carrier (e.g., buried or bulk channel, or peristaltic):
This subclass is indented under subclass 215. Subject matter wherein the transfer is by majority carriers of the semiconductor material, i.e., by electrons in n-type semiconductor material, and is by holes in p-type semiconductor material.

Having a conductive means in direct contact with channel (e.g., non-insulated gate):
This subclass is indented under subclass 216. Subject matter wherein an electrical conductor (e.g., electrode) directly contacts the channel region of the charge transfer device (e.g., a non-insulated gate (control) electrode).
(1) Note. The conductive means in direct contact with the channel may be directly connected to the substrate.
(2) Note. The conductive means in direct contact with the channel may be made of metal, forming a Schottky contact with the semiconductor channel material, i.e., a metal-semiconductor junction.

High resistivity channel (e.g., accumulation mode) or surface channel (e.g., transfer of signal charge occurs at the surface of the semiconductor) or minority carriers at input (i.e., surface channel input):
This subclass is indented under subclass 216. Subject matter wherein the majority signal carrier charge transfer device has a channel made of relatively high electrical resistivity material, or where the transfer of signal charge takes place at the surface of the semiconductor, or where minority charge carriers are input into a surface channel, but majority carriers are input into the bulk or buried channel portion of the device.

Impurity concentration variation:
This subclass is indented under subclass 216. Subject matter wherein the majority signal carrier charge transfer device contains impurity dopant ions which vary in terms of concentration in all or part of the channel of the device.
(1) Note. The impurity dopant ion concentration may vary across the channel and channel substrate interface.

Vertically within channel (e.g., profiled):
This subclass is indented under subclass 219. Subject matter wherein the impurity dopant ion concentration in the channel of the device varies across the channel in a direction perpendicular to a main surface of the device, regardless of the orientation of the channel (e.g., parallel or perpendicular to a main surface of the device).

Along the length of the channel (e.g., doping variations for transfer directionality):
This subclass is indented under subclass 219. Subject matter wherein the impurity dopant ion concentration in the channel of the device varies along the length of the channel, whether the channel is horizontally or vertically oriented.

Responsive to non-electrical external signal (e.g., imager):
This subclass is indented under subclass 216. Subject matter wherein the majority signal carrier charge transfer device transfers charge from one charge storage device to another in response to a non-electric signal (e.g., light, pressure, etc.).

Having structure to improve output signal (e.g., antiblooming drain):
This subclass is indented under subclass 222. Subject matter wherein the non-external signal responsive device includes structural means, e.g., a drain element which reduces or eliminates optical blooming to improve the signal generated by the device in response to the non-electrical input signal.

Channel confinement:
This subclass is indented under subclass 216. Subject matter wherein the majority carrier charge transfer device has means to restrict the dimensions of the thin semiconductor conductive path region (charge transfer channel) between the source and drain of the device.

Non-electrical input responsive (e.g., light responsive imager, input programmed by size of storage sites for use as a read-only memory, etc.):
This subclass is indented under subclass 215. Subject matter wherein the means that creates charge to be transferred is non-electrical (e.g., light).

Sensor element and charge transfer device are of different materials or on different substrates (e.g., "hybrid "):
This subclass is indented under subclass 225. Subject matter wherein charge carriers generated in response to the non-electrical input are generated in material which is
different than, or is located on a different substrate than, the semiconductor material that contains the charge carrier storage sites.

With specified dopant (e.g., photoionizable, "extrinsic" detectors for infrared):
This subclass is indented under subclass 225. Subject matter wherein the non-electrical responsive device contains specific impurity dopants.

Light responsive, back illuminated:
This subclass is indented under subclass 225. Subject matter wherein the non-electrical input responsive device has two major opposed surfaces, the channel containing the charge carrier storage sites being at or below one surface, and wherein the device is responsive to light which is incident on the other major surface.

Having structure to improve output signal (e.g., exposure control structure):
This subclass is indented under subclass 225. Subject matter wherein the non-electrical input responsive device contains structural means to improve the electrical signal it generates in response to the non-electrical input signal.
(1) Note. The structural means to improve the output signal may control the amount of charge generated by light incident on the device which is transferred as output signal charge.

With blooming suppression structure:
This subclass is indented under subclass 229. Subject matter wherein the structural means to improve the output signal prevents spill over of a large amount of signal charge generated at a storage site which receives a non-electrical input signal of very high intensity to adjacent storage sites.
(1) Note. The antiblooming suppression structure may include a drain structure for removing charge from storage sites.
(2) Note. The antiblooming drain structure may be located in the device beneath storage sites rather than on its surface.

2-dimensional area architecture:
This subclass is indented under subclass 225. Subject matter wherein the device has a plurality of non-electrical input responsive means spread out over a two dimensional area, e.g., a matrix or array of such means.
(1) Note. One 2-dimensional architecture area may be provided for light imaging elements and a separate 2-dimensional architecture area may be provided for electrical signal storage elements.
(2) Note. The imaging element sites may also be charge transfer storage sites (e.g., frame transfer imaging device).

Having alternating strips of sensor structures and register structures (e.g., interline imager):
This subclass is indented under subclass 231. Subject matter wherein the 2-dimensional area architecture has alternate strips of sensor structures and charge transfer channels.

Sensors not overlaid by electrode (e.g., photodiodes):
This subclass is indented under subclass 232. Subject matter wherein the light responsive sensor elements do not have an electrode overlying them.

Single strip of sensors (e.g., linear imager):
This subclass is indented under subclass 225. Subject matter wherein the non-electrical input responsive device is in the
form of a line of individual sensors.
(1) Note. The single strip of sensors may be combined with a structure forming readout registers, i.e., short term storage devices for accumulating charge packets generated by the sensors and for transferring charge packets to an amplifier or output device, and wherein the sensors are placed adjacent to the readout register structure.
(2) Note. The device may have plural readout register structures.

Electrical input:
This subclass is indented under subclass 215. Subject matter wherein the input to the charge transfer device to create the charge to be transferred is an electrical signal.

Signal applied to field effect electrode:
This subclass is indented under subclass 235. Subject matter wherein means is provided to apply an electrical signal to an electrode which has an electrical potential barrier between the electrode and the semiconductor material of the device (e.g., a MOS dielectric or Schottky contact or reverse-biased junction), as contrasted with an ohmic electrical contact to the semiconductor.

Charge-presetting/linear input type (e.g., fill and spill):
This subclass is indented under subclass 236. Subject matter wherein means is provided for the input signal to form a potential well, overfill it, drain away the excess charge and input the preset charge in the potential well into the channel.

Input signal responsive to signal charge in charge transfer device (e.g., regeneration or feedback):
This subclass is indented under subclass 235. Subject matter wherein means is provided to take charge from the output of a
charge transfer device and put it back into the input electrode thereof or into the input electrode of a second charge transfer device.

Signal charge detection type (e.g., floating diffusion or floating gate non-destructive output):
This subclass is indented under subclass 215. Subject matter wherein means is provided to detect the amount of charge being transferred in the device.
(1) Note. The charge being transferred may be measured without destroying the charge, i.e., the charge packet remains intact.
(2) Note. The charge transfer device may have a region diffused with impurity ions not electrically connected to ground to detect the magnitude of charge being transferred in the device and to output a signal proportional to that sensed charge. This is known as a floating diffusion output device. One example of such a device is a floating diffusion amplifier (FDA).
(3) Note. The charge transfer device may have a control electrode not electrically connected to ground to detect the magnitude of charge being transferred in the device and to output a signal proportional to that sensed charge. This type device is known as a floating gate output device. One example of such a device is a floating gate amplifier (FGA). Devices with plural floating gate outputs include distributed floating gate amplifiers (DFGA).

Changing width or direction of channel (e.g., meandering channel):
This subclass is indented under subclass 215. Subject matter wherein the charge transfer path region changes its width or direction throughout all or part of the distance from source to drain electrode.

Multiple channels (e.g., converging or diverging or parallel channels):
This subclass is indented under subclass 215. Subject matter wherein the charge transfer device contains more than one
channel for charge transfer path.
(1) Note. The channels may converge or diverge, i.e., they are not parallel to each other, but change direction either toward or away from each other along their length.
(2) Note. In such devices, the charge transfer path may lie in two different (e.g., orthogonal) directions.
(3) Note. The device may include two or more parallel channels (e.g., serial- parallel-serial) wherein the charge transfer takes place in different directions, but the device includes charge transfer paths that are parallel to each other.

Vertical charge transfer:
This subclass is indented under subclass 215. Subject matter wherein the charge transfer device is provided with structure for vertical charge transfer perpendicular to a main device surface.

Channel confinement:
This subclass is indented under subclass 215. Subject matter containing means (e.g., pn junctions or dielectric layers) to restrict the boundaries of the charge transfer path through the device.
(1) Note. Typical channel confinement means include use of (a) an electrically insulating medium; (b) a layer of silicon polymer material (polysilicon) used to reduce electric field interaction with charge to be transferred via the channel; or (c) an impurity ion located in the device substrate, i.e., in the material on which the device is fabricated (e.g., an implanted channel stop).

Comprising a groove:
This subclass is indented under subclass 215. Subject matter wherein a surface of the device includes an elongated indentation.
(1) Note. The location of the groove relative to the charge storage sites of the device is deliberately not specified in
this definition.

Structure for applying electric field into device (e.g., resistive electrode, acoustic traveling wave in channel):
This subclass is indented under subclass 215. Subject matter including structure (e.g., electrodes) for applying electrical energy into the device.
(1) Note. Structure for applying electrical energy into the device is typically an electrode with a relatively high electrical resistance value.

Phase structure (e.g., doping variations to provide asymmetry for 2-phase operation; more than four phases or "electrode per bit"):
This subclass is indented under subclass 245. Subject matter including a plurality of gate regions or doping variation regions to permit unidirectional charge packet transfer by symmetrical or unsymmetrically phased electrical control signals applied to the device gate or gates.
(1) Note. The phase structure may be multiphase (e.g., 3-phase or 4-phase), i.e., with three sets or four sets of electrodes, respectively.
(2) Note. Search subclass 249, below, for 2-phase structure devices.
(3) Note. Means may also be provided to generate a traveling wave of non-electrical energy (e.g., acoustic energy) in the device.

Uniphase or virtual phase structure:
This subclass is indented under subclass 246. Subject matter wherein the device has one set of gates (control electrodes) or virtual phase structure.

2-phase:
This subclass is indented under subclass 246. Subject matter wherein the device has two sets of gate electrodes.

Electrode structures or materials:
This subclass is indented under subclass 245. Subject matter wherein the charge transfer device is provided with specified electrode structures or materials to apply electric field into the device.

Plural gate levels:
This subclass is indented under subclass 249. Subject matter wherein the electrode structures include more than one level of gate electrodes relative to a main surface of the device.

Substantially incomplete signal charge transfer (e.g., bucket brigade):
This subclass is indented under subclass 215. Subject matter wherein the charge transferred is less than the entire charge stored in the storage site from which it originates.

Responsive to non-optical, non-electrical signal:
This subclass is indented under subclass 213. Subject matter which produces an electrical output in response to an input which is other than optical or electrical.

Chemical (e.g., ISFET, CHEMFET):
This subclass is indented under subclass 252. Subject matter wherein the input is a chemical reaction or the presence of a particular chemical in close proximity to the field effect device.

Physical deformation (e.g., strain sensor, acoustic wave detector):
This subclass is indented under subclass 252. Subject matter wherein the input is a physical deformation.

SEE OR SEARCH THIS CLASS, SUBCLASS:
416 for acoustic wave responsive devices, generally.

With current flow along specified crystal axis (e.g., axis of maximum carrier mobility):
This subclass is indented under subclass 213. Subject matter wherein the field effect device employs current flow along a specified crystal axis, such as a (100) axis or a (311) axis.

Junction field effect transistor (unipolar transistor):
This subclass is indented under subclass 213. Subject matter wherein the field effect device is a junction field effect transistor, i.e., in which current flow through a thin channel of semiconductor material is controlled by an electric field applied to a control region or electrode in rectifying contact (i.e., a pn junction or Schottky barrier junction) with the semiconductor material of the channel, so that the depletion region extending into the channel from the rectifying contact reduces the thickness of the undepleted portion of the channel to reduce the current flow through the channel.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 167 for methods of forming a Schottky gate field effect device and subclasses 186+ for methods of forming a junction gate field effect device.

Light responsive or combined with light responsive device:
This subclass is indented under subclass 256. Subject matter wherein the JFET generates an electrical signal when light energy is incident upon it or is combined with a light responsive device.

In imaging array:
This subclass is indented under subclass 257. Subject matter wherein a plurality of light responsive JFETs or JFETs combined with a light responsive device are in the form of a one or two dimensional array (e.g., line or area array) for forming an image of an object, light from which is incident upon the array.

Elongated active region acts as transmission line or distributed active element (e.g., "transmission line" field effect transistor):
This subclass is indented under subclass 256. Subject matter including at least one elongated active region (source, gate, or drain) which transmits or distributes charge carriers.
(1) Note. When the impedance of an element at the operating frequency is due primarily to the parameters of the element itself, and in considering the inductance, capacitance, and resistance of the element they must be considered as mixed together and spread out along the element rather than being considered as separate discrete lumps or components as in the case of simple series and parallel circuits, the element may be said to have distributed parameters.

SEE OR SEARCH CLASS:
333, Wave Transmission Lines and Networks, appropriate subclasses for transmission lines or distributed elements, per se.
438, Semiconductor Device Manufacturing: Process, particularly 167 for methods of forming a Schottky gate field effect device and subclasses 186+ for methods of forming a junction gate field effect device.

Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell):
This subclass is indented under subclass 256. Subject matter including plural gate electrodes or regions, at least one of which is isolated from the channel by a rectifying junction and at least another of which is isolated from the channel by an insulating layer therebetween, or wherein one rectifying junction may be a metal-to-semiconductor (Schottky) type and the other a pn junction.
(1) Note. In such devices, the junction gate region may be free of direct electrical connection (e.g., "taper isolated" memory cell), i.e., wherein the JFET has at least one gate electrode region which is isolated from the channel by a rectifying junction and is not directly provided with an electrical connection or terminal.

Junction gate region free of direct electrical connection (e.g., floating junction gate memory cell structure):
This subclass is indented under subclass 256. Subject matter including at least one gate electrode region which is isolated from the channel by a rectifying junction and is not directly provided with an electrical connection or terminal.
(1) Note. This type of gate is a floating junction gate, as contrasted with a floating insulated gate.
(2) Note. See this class, subclass 315, for floating insulated gate field effect devices.
(3) Note. The floating gate region may capacitively store electrical charge and be used as a memory element.

Combined with insulated gate field effect transistor (IGFET):
This subclass is indented under subclass 256. Subject matter including a field effect transistor having a gate (control) electrode which is electrically insulated from the channel and other electrodes of the transistor.
(1) Note. The combined JFET and IGFET may be electrically connected so that the source or drain electrode of one FET is connected to the gate electrode of the other FET.

Vertical controlled current path:
This subclass is indented under subclass 256. Subject matter wherein the operating current of the JFET has a path perpendicular to a main surface of the JFET and is controlled by the gate electrode of the device.

Enhancement mode or with high resistivity channel (e.g., doping of 10[supscrpt]15[end supscrpt]cm[supscrpt]-3[end supscrpt] or less):
This subclass is indented under subclass 263. Subject matter wherein an increase in the magnitude of the gate bias voltage increases the operating current, only leakage current flows when the gate voltage is zero, and conduction does not begin until the gate voltage reaches a threshold value; or the JFET has a channel made of relatively high electrical resistivity, e.g., due to doping with impurity ions of 10[supscrpt]15[end supscrpt] cm[supscrpt]-3 [end supscrpt]or less.

In integrated circuit:
This subclass is indented under subclass 263. Subject matter in a single monolithic semiconductor chip with other active and/or passive devices.

With multiple parallel current paths (e.g., grid gate):
This subclass is indented under subclass 263. Subject matter having plural paths for operating current flow, each of which is parallel with the other paths (e.g., having a gate electrode in the form of a matrix or grid).

With Schottky barrier gate:
This subclass is indented under subclass 266. Subject matter including a gate which is formed by a metal to semiconductor rectifying junction.

Enhancement mode:
This subclass is indented under subclass 256. Subject matter wherein an increase in the magnitude of the gate bias voltage increases the operating current, only leakage current flows when the gate voltage is zero, and conduction does not begin until the gate voltage reaches a threshold value.

With means to adjust barrier height (e.g., doping profile):
This subclass is indented under subclass 268. Subject matter including means to adjust the electronic height of the Schottky barrier gate junction, e.g., a profiled impurity dopant concentration.

Plural, separately connected, gates control same channel region:
This subclass is indented under subclass 256. Subject matter including more than one gate region or portion to control the same channel region, the regions being provided with separate electrical connections.

Load element or constant current source (e.g., with source to gate connection):
This subclass is indented under subclass 256. Subject matter structured to function as an electrical load element or a source of constant current, e.g., with a source to gate electrical connection.

Junction field effect transistor in integrated circuit:
This subclass is indented under subclass 256. Subject matter located in a single monolithic semiconductor chip with other active and/or passive devices.

With bipolar device:
This subclass is indented under subclass 272. Subject matter located in an integrated circuit with a device which operates using both positive and negative charge carriers.
(1) Note. An active solid-state electronic device that contains both bipolar and field effect transistors may be referred to as a BI-FET device.

Complementary junction field effect transistors:
This subclass is indented under subclass 272. Subject matter which is located in and integrated with an opposite conductivity type JFET, i.e., an N channel JFET together with a P channel JFET.

Microwave integrated circuit (e.g., microstrip type):
This subclass is indented under subclass 272. Subject matter structured to operate at microwave frequencies in an integrated circuit containing microwave components (e.g., microstrip transmission lines).

With contact or heat sink extending through hole in semiconductor substrate, or with electrode suspended over substrate (e.g., air bridge):
This subclass is indented under subclass 275. Subject matter containing a hole in the semiconductor substrate and an electrical contact or a heat dissipation means extending through the hole.

SEE OR SEARCH THIS CLASS, SUBCLASS:
522 for integrated circuit devices employing air isolation.

With capacitive or inductive elements:
This subclass is indented under subclass 275. Subject matter having passive elements with electrical inductance or capacitance.

With devices vertically spaced in different layers of semiconductor material (e.g., "3-dimensional" integrated circuit):
Subject matter under 272 wherein the JFET and other active and/or passive devices in that chip are located in mutually perpendicular planes in different layers of semiconductor device material.

Pn junction gate in compound semiconductor material (e.g., GaAs):
This subclass is indented under subclass 256. Subject matter including a pn junction gate formed in a semiconductor material that is a compound, e.g., GaAs, as contrasted to an elemental semiconductor such as silicon or germanium.

With Schottky gate:
This subclass is indented under subclass 256. Subject matter including a metal to semiconductor rectifying (i.e., Schottky barrier) gate electrode.
(1) Note. A Schottky barrier gate JFET is referred to commonly as a MESFET (MEtal-Semiconductor field effect transistor).

Schottky gate to silicon semiconductor:
This subclass is indented under subclass 280. Subject matter wherein the semiconductor material contacting the gate electrode material is made of silicon.

Gate closely aligned to source region:
This subclass is indented under subclass 280. Subject matter wherein the gate region is closely aligned with the source region.

SEE OR SEARCH THIS CLASS, SUBCLASS:
332 346, 387, and 797, for other self-aligned gate devices.

With groove or overhang for alignment:
This subclass is indented under subclass 282. Subject matter wherein the device has a groove or overhang for alignment of the gate and source regions.

Schottky gate in groove:
This subclass is indented under subclass 280. Subject matter wherein the MESFET has a groove in at least one of its surfaces and the Schottky gate is located therein.

With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface):
This subclass is indented under subclass 256. Subject matter wherein the JFET has a variable impurity atom dopant concentration in the channel or gate region, e.g., wherein the maximum dopant concentration is located below the surface of the device, in either the channel or gate region.

With non-uniform channel thickness or width:
This subclass is indented under subclass 256. Subject matter wherein the channel has a non-uniform width or thickness (which lies in a plane perpendicular to both the channel length and width).
(1) Note. Channel length is measured along a line connecting the source and drain, while channel width is
measured perpendicular to the length. Both length and width lie in a plane, parallel to the device surface. See the illustration, below. [figure]

With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET):
This subclass is indented under subclass 256. Subject matter including more than one channel or channel segments/portions which are electrically connected in parallel, or wherein the device has a channel whose width is much wider than the channel length, the channel length being the distance between the source and drain of the JFET.

SEE OR SEARCH THIS CLASS, SUBCLASS:
134 for JFET devices, in general.
504 for JFET type isolation.

Having insulated electrode (e.g., MOSFET, MOS diode):
This subclass is indented under subclass 213. Subject matter including an electrode which is electrically insulated from the active semiconductor region of the device (e.g., a metal oxide semiconductor insulated electrode).
(1) Note. Typically the insulated electrode is the control or gate electrode.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 197 for methods of forming an insulated gate field effect device.

Significant semiconductor chemical compound in bulk crystal (e.g., GaAs):
This subclass is indented under subclass 288. Subject matter wherein the insulated electrode field effect device contains a significant semiconductor chemical compound in a bulk (as contrasted with thin film) crystal (e.g., GaAs).

SEE OR SEARCH THIS CLASS, SUBCLASS:
1 for bulk effect devices.

Light responsive or combined with light responsive device:
This subclass is indented under subclass 288. Subject matter which generates an electrical signal when light is incident on it or is combined with a light responsive device.

Imaging array:
This subclass is indented under subclass 290. Subject matter comprising a one or more dimensional array of light responsive devices which generate an electronic image of light from an object incident thereupon.

Photodiodes accessed by FETs:
This subclass is indented under subclass 291. Subject matter comprising light responsive diodes electrically coupled to field effect transistors.

Photoresistors accessed by FETs, or photodetectors separate from FET chip:
This subclass is indented under subclass 291. Subject matter comprising light responsive resistors coupled to field effect transistors.

With shield, filter, or lens:
This subclass is indented under subclass 291. Subject matter including means to shield the array from unwanted light, to filter light incident on the array, or to refract light incident on the array (e.g., to focus an image of an object on the array).

With ferroelectric material layer:
This subclass is indented under subclass 288. Subject matter including a layer of material which exhibits a spontaneous dipole moment.

Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell):
This subclass is indented under subclass 288. Subject matter wherein the device gate acts as a capacitor (i.e., wherein a positive potential placed on the gate electrode creates a negative charge on the other side of the insulator in the semiconductor material of the device, and vice versa) or the device is a transistor and it is combined with a capacitor.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 239 for methods of forming an insulated gate field effect transistor combined with a capacitor and subclasses 386 through 399 for manufacture of a capacitors, per se, utilizing a semiconductor substrate.

With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection):
This subclass is indented under subclass 296. Subject matter wherein the device further includes means (1) to prevent electrical charge in the capacitor or capacitive type insulated gate region of the transistor to leak therefrom, or (2) to prevent excess leakage currents across pn junctions due to generation of minority carriers in the device for example (a) alpha particles incident on the device or (b) thermal generation of electron-hole pairs, or (c) minority carriers injected into the semiconductor substrate by other devices in the same substrate.
(1) Note. Junctions across which excess leakage is sought to be prevented typically include (a) the source or drain junction of an insulated gate field effect transistor or (b) a connecting BIT line of a memory array which is isolated by a pn junction from a semiconductor substrate.

Capacitor for signal storage in combination with non-volatile storage means:
This subclass is indented under subclass 296. Subject matter including a capacitor to store an electrical signal in combination with charge storage means that can retain the charge even in the absence of operating power.

Structure configured for voltage converter (e.g., charge pump, substrate bias generator):
This subclass is indented under subclass 296. Subject matter including structure for use as a voltage converter (e.g., a device for changing AC to DC or vice versa, or for producing a negative DC voltage relative to a reference potential from a positive DC voltage relative to that reference potential).

Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., non-destructive readout dynamic memory cell structure):
This subclass is indented under subclass 296. Subject matter wherein the capacitor is electrically connected to or forms the gate of an insulated gate field effect transistor (IGFET), e.g., a non-destructive readout dynamic memory cell structure in which the charge state of the capacitor may be read out or determined by the conduction state of the field effect transistor, without discharging the capacitor in the readout process.

Capacitor in trench:
This subclass is indented under subclass 296. Subject matter wherein the capacitor is located in a recess in the semiconductor substrate.

Vertical transistor:
This subclass is indented under subclass 301. Subject matter combined with a vertical transistor (i.e., one in which the operating current flow is perpendicular to a main surface of the device).

Stacked capacitor:
This subclass is indented under subclass 301. Subject matter wherein the trench capacitor device contains a number of capacitor electrode regions stacked vertically above each other or wherein the capacitor and the transistor are located such that one overlies the other.

Storage node isolated by dielectric from semiconductor substrate:
This subclass is indented under subclass 301. Subject matter including an electrode upon which the charge varies as an indication of the memory state of the device (e.g., memory cell), and wherein the electrode is electrically isolated by a dielectric material from the semiconductor substrate of the device.

With means to insulate adjacent storage nodes (e.g., channel stops or field oxide):
This subclass is indented under subclass 301. Subject matter including means for electrically insulating an electrode upon which the charge varies as an indication of the memory state of the device (e.g., a memory cell).
(1) Note. The insulating means may, for example, comprise a channel stop or a field oxide.

Stacked capacitor:
This subclass is indented under subclass 296. Subject matter wherein the capacitor device contains a number of capacitor electrode regions overlying each other or where the capacitor
and the transistor are located such that one overlies the other.

Parallel interleaved capacitor electrode pairs (e.g., interdigitized):
This subclass is indented under subclass 306. Subject matter wherein the number of overlying capacitor electrodes is more than one and the overlapping region of each capacitor electrode pair is made up of electrodes from one capacitor interleaved with the electrodes of another capacitor.

With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post):
This subclass is indented under subclass 307. Subject matter wherein the capacitor electrodes are connected together at a centrally located portion thereof, e.g., by a center post.

With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes):
This subclass is indented under subclass 306. Subject matter wherein a capacitor electrode has an increased effective surface relative to a flat capacitor plate, because of twists, turns, curves, corrugations, windings or other surface area increasing features of a capacitor electrode.

With high dielectric constant insulator (e.g., Ta[subscrpt]2[end subscrpt]O[subscrpt]5[end subscrpt]):
This subclass is indented under subclass 296. Subject matter wherein the capacitor device includes an insulating element which has a dielectric constant (e.g., Ta[subscrpt]2[end subscrpt]O[subscrpt]5[end subscrpt]) greater than 7.5, the dielectric constant of Si[subscrpt]3[end subscrpt]N[subscrpt]4[end subscrpt].

Storage Node isolated by dielectric from semiconductor substrate:
This subclass is indented under subclass 296. Subject matter wherein the device has an electrode upon which the charge varies as an indication of the memory state of the device (e.g., memory cell) which electrode is electrically isolated by a dielectric material from the semiconductor substrate of the device.

Voltage variable capacitor (i. e., capacitance varies with applied voltage):
This subclass is indented under subclass 296. Subject matter wherein the device changes its capacitance depending on the amount of voltage applied thereto.

Inversion layer capacitor:
This subclass is indented under subclass 296. Subject matter wherein one plate of the capacitor device is a layer of minority carriers opposite in conductivity type to the doping of the semiconductor which are induced by applied voltage.

Variable threshold (e.g., floating gate memory device):
This subclass is indented under subclass 288. Subject matter wherein the device has a threshold voltage for current conduction which may be varied (e.g., by storage of charge in an insulator layer adjacent the channel in response to an electrical "write" signal).

SEE OR SEARCH THIS CLASS, SUBCLASS:
239 for a floating gate signal charge detection type charge transfer device.
261 for a floating gate JFET.

SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, appropriate subclass for read/write static storage systems, and 185.01 for predominate structure of floating gate memory storage
(e.g., flash memory), particularly subclass 185.24 for threshold setting (e.g., conditioning).

With floating gate electrode:
This subclass is indented under subclass 314. Subject matter including a gate electrode which is free of direct electrical connection.

SEE OR SEARCH CLASS:
365, Static Information Storage and Retrieval, appropriate subclass for read/write static storage systems, and 185.01 for predominate structure of floating gate memory storage (e.g., flash memory), particularly subclass 185.24 for threshold setting (e.g., conditioning).

With additional contacted control electrode:
This subclass is indented under subclass 315. Subject matter including an additional control (gate) electrode that has a direct electrical contact thereto.

With irregularities on electrode to facilitate charging or discharging of floating electrode:
This subclass is indented under subclass 316. Subject matter wherein the floating or additional control (gate) electrode has physical surface irregularities to facilitate charging or discharging of the floating gate electrode.

Additional control electrode is doped region in semiconductor substrate:
This subclass is indented under subclass 316. Subject matter wherein the additional control (gate) electrode is a specific region in the semiconductor substrate which is doped with impurity ions.

Plural additional contacted control electrodes:
This subclass is indented under subclass 316. Subject matter including more than one additional control (gate) electrode.

Separate control electrodes for charging and for discharging floating electrode:
This subclass is indented under subclass 319. Subject matter wherein the device has separate control (gate) electrodes for charging and discharging a floating electrode.

With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling:
This subclass is indented under subclass 316. Subject matter including a thin insulator region for charging of discharging a floating electrode by means of quantum mechanical tunneling of charge carriers.

SEE OR SEARCH THIS CLASS, SUBCLASS:
9 through 25, 28, and 30 through 39, for active solid-state devices involving this discrete layer type of quantum mechanical tunneling.

With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction):
This subclass is indented under subclass 316. Subject matter wherein the variable threshold device is structured to charge or discharge a floating gate electrode by a control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction).

With means to facilitate light erasure:
This subclass is indented under subclass 315. Subject matter
including means to make erasure of the electrical charge content of the device by light easier (e.g., by providing an ultraviolet light window layer over the floating gate electrode to reduce absorption of erasing light).

Multiple insulator layers (e.g., MNOS structure):
This subclass is indented under subclass 314. Subject matter including more than one layer of electrically insulating material (e.g., metal-nitride-oxide (MNOS) semiconductor).

Non-homogeneous composition insulator layer (e.g., graded composition layer or layer with inclusions):
This subclass is indented under subclass 324. Subject matter wherein at least one layer has a non-homogeneous composition (e.g., a layer which varies in composition along at least one dimension thereof, or has inclusions of foreign material therein).

With additional, non-memory control electrode or channel portion (e.g., accessing field effect transistor structure):
This subclass is indented under subclass 324. Subject matter wherein the multiple insulator layer device has an additional, non-memory control electrode or channel portion, for example, for forming an accessing field effect transistor structure.

Short channel insulated gate field effect transistor:
This subclass is indented under subclass 288. Subject matter wherein the field effect device is an insulated gate field effect transistor with a short channel (i.e., one wherein the length of the channel is sufficiently short that the threshold voltage of the transistor depends on the length of the channel, or where the channel is specified to be less than 2 micrometers in length).

Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode):
This subclass is indented under subclass 327. Subject matter wherein the short channel IGFET has a vertical current channel structure or the short channel IGFETs active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused, DMOS transistor) and wherein means are provided to protect the short channel against overvoltages (e.g., a gate insulator protection diode).
(1) Note. Gate protection diodes in IGFETs in general may be found in this class, subclass 355, and indented subclasses.

Gate controls vertical charge flow portion of channel (e.g., VMOS device):
This subclass is indented under subclass 327. Subject matter wherein the short channel IGFET has a channel portion in which charge flows in a substantially vertical direction and wherein the charge flowing therein is controlled by the gate electrode.
(1) Note. An IGFET's short channel may have horizontal as well as vertical charge flow portions. This subclass provides for those devices in which the vertical charge flow portion, i.e., the portion of the channel in which charge is flowing substantially in a vertical direction, of the channel is controlled by the gate.

Gate electrode in groove:
This subclass is indented under subclass 329. Subject matter wherein the gate controlled vertical channel device has a groove located therein and a gate electrode located in the groove.

Plural gate electrodes or grid shaped gate electrode:
This subclass is indented under subclass 330. Subject matter
wherein there is more than one gate electrode located in a groove or wherein the gate electrode has a grid or mesh type shape.

Gate electrode self-aligned with groove:
This subclass is indented under subclass 330. Subject matter wherein the gate electrode is self-aligned with the groove.

SEE OR SEARCH THIS CLASS, SUBCLASS:
282 283, 346, 387, and 797, for other self-aligned gate devices.

With thick insulator to reduce gate capacitance in non-channel areas (e.g., thick oxide over source or drain region):
This subclass is indented under subclass 330. Subject matter wherein the device with a gate electrode in a groove is provided with a thick insulator material layer to reduce gate capacitance in non-channel areas, e.g., a thick layer of oxide located over the source or drain region.

In integrated circuit structure:
This subclass is indented under subclass 330. Subject matter wherein the device is located in an integrated circuit structure.

Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor):
This subclass is indented under subclass 327. Subject matter wherein the short channel IGFET's active channel region has a graded dopant concentration decreasing with distance from source region, e.g., double diffused device or a DMOS transistor.

With lightly doped portion of drain region adjacent channel (e.g., LDD structure):
This subclass is indented under subclass 335. Subject matter wherein the graded channel doping short channel IGFET has a relatively light concentration of dopant in the portion of the drain region which lies adjacent to the current conducting channel.

In integrated circuit structure:
This subclass is indented under subclass 335. Subject matter wherein the graded channel doping short channel IGFET is contained in a single monolithic chip with other active or passive solid-state electronic devices.

With complementary field effect transistor:
This subclass is indented under subclass 337. Subject matter wherein the graded channel doping short channel IGFET is contained in a single monolithic chip with a field effect transistor with a polarity type opposite to that of the graded channel doping short channel IGFET.

With means to increase breakdown voltage:
This subclass is indented under subclass 335. Subject matter wherein the graded channel doping short channel IGFET includes means to increase the voltage that may be applied to the device without electrical breakdown of the device occurring.

With means (other than self-alignment of the gate electrode) to decrease gate capacitance (e.g., shield electrode):
This subclass is indented under subclass 335. Subject matter wherein the graded channel doping short channel IGFET has means (other than self-alignment of the gate electrode)
(e.g., an shielding electrode) to decrease the capacitance of the gate electrode.

Plural sections connected in parallel (e.g., power MOSFET):
This subclass is indented under subclass 335. Subject matter wherein the graded channel doping short channel IGFET has more than one section and a plurality of those sections are connected electrically in parallel (e.g., to form a power MOSFET).

With means to reduce ON resistance:
This subclass is indented under subclass 341. Subject matter wherein the device further contains means to reduce the resistance of the device when it is conducting electricity, i.e., in the ON condition.

All contacts on same surface (e.g., lateral structure):
This subclass is indented under subclass 335. Subject matter wherein all electrical contacts of the device are located on the same external surface of the device, e.g., a lateral structure device.

With lightly doped portion of drain region adjacent channel (e.g., LDD structure):
This subclass is indented under subclass 327. Subject matter wherein the short channel IGFET has a lightly doped portion of the drain region adjacent channel (e.g., a lightly doped drain structure).

With means to prevent sub-surface currents, or with non-uniform channel doping:
This subclass is indented under subclass 327. Subject matter
wherein the short channel IGFET contains means to prevent current from flowing below the surface of the device.

Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate):
This subclass is indented under subclass 327. Subject matter wherein the short channel IGFET has a gate electrode which overlaps the source or drain or both by no more than the thickness of the depth of the source or drain (e.g., a self-aligned gate).
(1) Note. A self-aligned gate is one which is aligned between the source and drain via a masking process which uses the gate material itself to achieve the alignment.

SEE OR SEARCH THIS CLASS, SUBCLASS:
282 283, 332, 387, and 797, for other self-aligned gate devices.

Single crystal semiconductor layer on insulating substrate (SOI):
This subclass is indented under subclass 288. Subject matter wherein the field effect device has a single crystal semiconductor layer located on a substrate made of electrically insulating material.
(1) Note. See this class, subclass 49, for active solid-state devices in non-single crystalline layers which may be on insulating substrates. See this class, subclass 506, for active devices in single crystal layers which are dielectrically isolated, but do not include field effect devices.
(2) Note. Material deposited as polycrystalline or amorphous and then recrystallized, as by a scanning laser beam, is considered to be non-single crystalline for purposes of determining classification between this subclass and subclass 49, since such recrystallization typically leaves residual grain boundaries and is thus large grained polycrystalline material, rather than true single crystal material.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 149 for methods of forming a field effect
transistor on an insulating substrate or layer (e.g., SOS, SOI, etc.).

Depletion mode field effect transistor:
This subclass is indented under subclass 347. Subject matter wherein the SOI device is a field effect transistor which operates in the depletion mode, i.e., a FET which passes maximum operating current with the gate to source biased to zero volts.

With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate:
This subclass is indented under subclass 347. Subject matter wherein the SOI device includes means to prevent undesirable stray current to flow along the interface between the semiconductor layer and the insulating substrate.
(1) Note. The means to prevent this stray current may be, for example, a thin layer of doped semiconductor material for trapping charge /which would otherwise flow through a channel in the device.

Insulated electrode device is combined with diverse type device (e.g., complementary MOSFETs, FET with resistor, etc.):
This subclass is indented under subclass 347. Subject matter wherein the SOI device is combined with a different solid-state active or passive device, e.g., to form complementary MOSFETs or a FET combined with a resistor, etc.

Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components):
This subclass is indented under subclass 350. Subject matter wherein the field effect transistor and the diverse type
device are field effect transistors which are complementary in conductivity type to each other (e.g., provide a CMOS structure).

Substrate is single crystal insulator (e.g., sapphire or spinel):
This subclass is indented under subclass 347. Subject matter wherein the SOI substrate is a single crystal insulator (e.g., sapphire or spinel).

Single crystal islands of semiconductor layer containing only one active device:
This subclass is indented under subclass 352. Subject matter wherein the single crystal insulator SOI substrate contains single crystal islands of semiconductor material, each island containing only one active solid-state device.

Including means to eliminate island edge effects (e.g., insulating filling between islands, or ions in island edges):
This subclass is indented under subclass 353. Subject matter wherein means are provided to eliminate deleterious effects caused by the edges of each island, such means including, for example, electrically insulating filling between islands, or channel stop regions located in the edges of islands.

With overvoltage protective means:
This subclass is indented under subclass 288. Subject matter wherein the device has means to protect it against applied voltage which exceeds that which the device can tolerate before being damaged.

For protecting against gate insulator breakdown:
This subclass is indented under subclass 355. Subject matter wherein the overvoltage protection means is structured to protect against electrical breakdown (shorting) of the gate insulator.

In complementary field effect transistor integrated circuit:
This subclass is indented under subclass 356. Subject matter wherein the device includes complementary field effect transistors located in a single monolithic chip.

Including resistor element:
This subclass is indented under subclass 357. Subject matter wherein the device includes an electrical resistor.

As thin film structure (e.g., polysilicon resistor):
This subclass is indented under subclass 358. Subject matter wherein the resistor is in the form of a thin film resistor (e.g., a polysilicon resistor).

Protection device includes insulated gate transistor structure (e.g., combined with resistor element):
This subclass is indented under subclass 356. Subject matter wherein the means for protecting against insulator breakdown is an insulated gate transistor structure.

For operation as bipolar or punchthrough element:
This subclass is indented under subclass 360. Subject matter wherein the insulated gate transistor structure protection device is configured to operate as a bipolar transistor or to conduct by punchthrough of a depletion region from one pn junction to another pn junction upon application of an
overvoltage.

Punchthrough or bipolar element:
This subclass is indented under subclass 356. Subject matter wherein the means for protecting against insulator breakdown is a bipolar device or is configured to conduct by punchthrough of a depletion region from one pn junction to another pn junction upon application of an overvoltage.

Including resistor element:
This subclass is indented under subclass 356. Subject matter including an electrical resistive element.

With resistive gate electrode:
This subclass is indented under subclass 288. Subject matter including a gate (control) electrode which has high electrical resistivity.

With plural, separately connected, gate electrodes in same device:
This subclass is indented under subclass 288. Subject matter wherein the device has more than one gate (control) electrode, in the same device, with separate electrical connections to the plural gate (control) electrodes.

Overlapping gate electrodes:
This subclass is indented under subclass 365. Subject matter wherein at least one of the plural gate electrodes overlaps another gate electrode.

Insulated gate controlled breakdown of pn junction (e.g., field plate diode):
Subject matter under 288 including an electrically insulated gate electrode which is used to control the voltage applied to the device to cause breakdown of the pn junction.

Insulated gate field effect transistor in integrated circuit:
This subclass is indented under subclass 288. Subject matter wherein the device is an insulated gate field effect transistor located in a single monolithic semiconductor chip circuit.

Complementary insulated gate field effect transistors:
This subclass is indented under subclass 368. Subject matter wherein the device is made up of IGFETs that have opposite conductivity channels (p-type and n-type).

Combined with bipolar transistor:
This subclass is indented under subclass 369. Subject matter including at least one bipolar transistor.
(1) Note. An active solid-state electronic device that contains both bipolar and field effect transistors may be referred to as a BI-FET device.

Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells:
This subclass is indented under subclass 369. Subject matter wherein the complementary IGFETs are located in wells of semiconductor material with electrical conductivity opposite to that of the respective transistors and wherein the wells contain a higher concentration of dopant ions than the
semiconductor substrate in which they are located (e.g., twin wells).

With means to prevent latchup or parasitic conduction channels:
This subclass is indented under subclass 369. Subject matter including means to prevent conduction between regions of complementary IGFETs which form a (parasitic) regenerative structure which remains ON in the absence of a triggering signal.
(1) Note. For a definition of the regenerative structure of this subclass type, see subclass 107.

With pn junction to collect injected minority carriers to prevent parasitic bipolar transistor action:
This subclass is indented under subclass 372. Subject matter wherein the means for preventing latchup includes a pn junction for collecting minority carriers injected into the device to prevent operation of parasitic bipolar transistors which are otherwise capable of forming part of a parasitic regenerative switching structure.

Dielectric isolation means (e.g., dielectric layer in vertical grooves):
This subclass is indented under subclass 372. Subject matter wherein the means to prevent latchup includes means to dielectrically isolate the individual IGFETs from each other.

With means to reduce substrate spreading resistance (e.g., heavily doped substrate):
This subclass is indented under subclass 372. Subject matter wherein the means to prevent latchup includes means to reduce the electrical resistance of the substrate to reduce voltage differences between different parts of the substrate due to currents flowing therethrough.

With barrier region of reduced minority carrier lifetime (e.g., heavily doped P+ region to reduce electron minority carrier lifetime, or containing deep level impurity or crystal damage), or with region of high threshold voltage (e.g., heavily doped channel stop region):
This subclass is indented under subclass 372. Subject matter wherein the means to prevent latchup includes an electrical barrier region whose minority carrier lifetime is reduced from its normal value (e.g., by employing heavily doped P+ region to reduce electron minority carrier lifetime, or contains a deep level impurity or crystal damage) or has a region of high threshold voltage (e.g., a heavily doped channel stop region).

With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide):
This subclass is indented under subclass 369. Subject matter wherein the device contains electrical interconnections to the source and/or drain regions of the IGFETs which are made of polycrystalline silicon (e.g., polysilicon laminated with a silicide).

Combined with bipolar transistor:
This subclass is indented under subclass 368. Subject matter wherein the IGFET is combined with a bipolar transistor in a single semiconductor chip.
(1) Note. An active solid-state electronic device that contains both bipolar and field effect transistors may be referred to as a BI-FET device.

Combined with passive components (e.g., resistors):
This subclass is indented under subclass 368. Subject matter wherein the IGFET is combined with passive electronic solid-state devices (e.g., resistors, inductors, transmission lines, etc.) in the integrated circuit.

Polysilicon resistor:
This subclass is indented under subclass 379. Subject matter wherein the device is combined with a resistor made of a polycrystalline form of silicon.

With multiple levels of polycrystalline silicon:
This subclass is indented under subclass 380. Subject matter wherein the integrated circuit has more than one layer of polycrystalline silicon.

With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide):
This subclass is indented under subclass 368. Subject matter wherein the device has an electrical contact to its source region or drain region wherein the contact is made of a refractory or platinum group metal, or of other material which has a melting point above that of the iron group of metals and which is resistant to heat (e.g., of polysilicon, tungsten or silicide).
(1) Note. Refractory materials include refractory metals and platinum group metals which include metals found in groups IVA, VA, VIA, or VIIIA (other than iron (Fe), nickel (Ni) or cobalt (Co)) of the periodic table of the elements.

Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium):
This subclass is indented under subclass 382. Subject matter wherein the contact to the source or drain region is made of a refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium).

Including silicide:
This subclass is indented under subclass 382. Subject matter wherein the contacts are made of a silicide.

Multiple polysilicon layers:
This subclass is indented under subclass 382. Subject matter wherein the refractory material contact to source or drain region includes more than one layer of polysilicon.

With means to reduce parasitic capacitance:
This subclass is indented under subclass 368. Subject matter wherein the device contains means to reduce unwanted capacitance between elements of the field effect transistor.

Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate):
This subclass is indented under subclass 386. Subject matter wherein the gate electrode overlaps at least one source or drain by no more than the depth of the source or the drain (e.g., self-aligned gate).

SEE OR SEARCH THIS CLASS, SUBCLASS:
282 283, 328, 342, and 794, for other self-aligned gate devices.

Gate electrode consists of refractory or platinum group metal or silicide:
This subclass is indented under subclass 387. Subject matter wherein the gate electrode contains only refractory or platinum group metal (e.g., molybdenum, titanium or tungsten, or a silicide).

With thick insulator over source or drain region:
This subclass is indented under subclass 386. Subject matter wherein the means to reduce the parasitic capacitance is a thick insulating material layer located over the source or drain region.

Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM)):
This subclass is indented under subclass 368. Subject matter wherein the integrated circuit contains a two dimensional array of IGFETs, only some of which are completed devices, or the integrated circuit contains structure for a mask programmed read-only memory device.

Selected groups of complete field effect devices having different threshold voltages (e.g., different channel dopant concentrations):
This subclass is indented under subclass 390. Subject matter wherein selected groups of complete IGFETs have different threshold voltages above which the IGFETs will operate (e.g., different IGFETs have different current carrying channel impurity dopant concentrations).

Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode):
This subclass is indented under subclass 368. Subject matter wherein the IGFETs have different threshold voltages in the same integrated circuit (e.g., both enhancement and depletion mode IGFETs in the same integrated circuit).

Insulated gate field effect transistor adapted to function as load element for switching insulated gate field effect transistor:
This subclass is indented under subclass 368. Subject matter wherein the device is configured to function as a load element for another IGFET which is switched OFF and ON by signals applied thereto.

With means to prevent parasitic conduction channels:
This subclass is indented under subclass 368. Subject matter wherein the device includes means to prevent the formation of unwanted parasitic field effect transistor elements.

Thick insulator portion:
This subclass is indented under subclass 394. Subject matter wherein the means to prevent parasitic conduction channels from forming includes a thick insulator portion.

Recessed into semiconductor surface:
This subclass is indented under subclass 395. Subject matter wherein the thick insulator portion is recessed into the semiconductor device surface.

In vertical-walled groove:
This subclass is indented under subclass 396. Subject matter wherein the recessed thick isolator portion is in a groove in the surface of the overall device which extends perpendicular to the surface of the overall device.

Combined with heavily doped channel stop portion:
This subclass is indented under subclass 396. Subject matter wherein the device is combined with regions of heavy doping concentration.

Combined with heavily doped channel stop portion:
This subclass is indented under subclass 395. Subject matter wherein the device is combined with regions of heavy doping concentration.

With heavily doped channel stop portion:
This subclass is indented under subclass 394. Subject matter wherein the means to prevent parasitic conduction channels from forming comprises a region of heavy doping concentration.

With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET):
This subclass is indented under subclass 368. Subject matter wherein the device has a specific physical configuration or layout (e.g., ring gate).

With permanent threshold adjustment (e.g., depletion mode):
This subclass is indented under subclass 288. Subject matter wherein the device includes means for permanently adjusting the threshold voltage at which the device conducts (e.g., depletion mode IGFETs).

With channel conductivity dopant same type as that of source and drain:
This subclass is indented under subclass 402. Subject matter wherein the device has a channel which is doped with impurity dopant to be the same conductivity type (n or p) as the source and drain.

Non-uniform channel doping:
This subclass is indented under subclass 403. Subject matter wherein the dopant concentration varies along at least one dimension of the channel.

With gate insulator containing specified permanent charge:
This subclass is indented under subclass 402. Subject matter wherein the device has a gate insulator with a specified permanent electrostatic charge therein.

Plural gate insulator layers:
This subclass is indented under subclass 405. Subject matter wherein the gate insulator is made up of a plurality of gate insulator layers.

With gate electrode of controlled workfunction material (e.g., low workfunction gate material):
This subclass is indented under subclass 402. Subject matter wherein the device has a gate electrode selected to have a controlled amount of minimum energy needed to be applied thereto to liberate an electron from its Fermi-level and send it into free space.

SEE OR SEARCH THIS CLASS, SUBCLASS:
10 and 11, for low workfunction material layer used for electron emission.

Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device):
This subclass is indented under subclass 288. Subject matter wherein the device includes a drain portion adjacent the current channel which is lightly doped with impurities.

With means to increase breakdown voltage (e.g., field shield electrode, guard ring, etc.):
This subclass is indented under subclass 288. Subject matter wherein the device has means to increase the voltage that can be applied to the device without causing electrical breakdown of the device.

Gate insulator includes material (including air or vacuum) other than SiO[subscrpt]2[end subscrpt]:
This subclass is indented under subclass 288. Subject matter wherein the gate electrode insulator includes material other than silicon dioxide.

Composite or layered gate insulator (e.g., mixture such as silicon oxynitride):
This subclass is indented under subclass 410. Subject matter wherein the gate insulator is made of a composite material or layers of different materials.

Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal):
This subclass is indented under subclass 288. Subject matter wherein the device has a gate electrode which is made of a refractory material (e.g., polysilicon or a silicide of a metal found in groups IVA, VA, VIA, or VIIIA (other than iron (Fe), nickel (Ni) or cobalt (Co)) of the periodic table of the elements.

Polysilicon laminated with silicide:
This subclass is indented under subclass 412. Subject matter wherein the refractory material is a laminate comprising at
least one layer of polysilicon and one layer of a silicide.

RESPONSIVE TO NON-ELECTRICAL SIGNAL (E.G., CHEMICAL, STRESS, LIGHT, OR MAGNETIC FIELD SENSORS):
This subclass is indented under the class definition. Subject matter wherein the device generates an electrical signal in response to a non-electrical signal (e.g., light, heat, pressure) incident thereon.

Physical deformation:
This subclass is indented under subclass 414. Subject matter wherein the non-electrical signal incident upon the active solid-state device is a force which physically deforms the device.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 50 for methods of forming semiconductor devices which are responsive to physical deformation.

Acoustic wave:
This subclass is indented under subclass 415. Subject matter wherein the physically deforming force is in the form of a traveling vibration made up of sound energy.

SEE OR SEARCH THIS CLASS, SUBCLASS:
254 for field effect acoustic wave responsive devices.

Strain sensors:
This subclass is indented under subclass 415. Subject matter wherein the physically deforming force is that of an applied stress.

SEE OR SEARCH THIS CLASS, SUBCLASS:
254 for field effect strain sensor devices.

With means to concentrate stress:
This subclass is indented under subclass 417. Subject matter wherein the active solid-state device has means to concentrate the physically deforming stress.

With thinned central active portion of semiconductor surrounded by thick insensitive portion (e.g. diaphragm type strain gauge):
This subclass is indented under subclass 418. Subject matter wherein the means to concentrate the physically deforming stress is a thinned central active portion of semiconductor surrounded by a thick insensitive portion (e.g., a diaphragm type strain gauge).

Means to reduce sensitivity to physical deformation:
This subclass is indented under subclass 415. Subject matter wherein the device contains means to reduce the change in electrical output signal in response to physical deformation of the active junction.

Magnetic field:
This subclass is indented under subclass 414. Subject matter wherein the non-electrical signal to which the active solid-state device responds, is a magnetic field.

SEE OR SEARCH THIS CLASS, SUBCLASS:
108 for regenerative type magnetic field responsive devices

With magnetic field directing means (e.g., shield, pole piece, etc.):
This subclass is indented under subclass 421. Subject matter wherein means is provided for directing a magnetic field to the active solid-state device.

Bipolar transistor magnetic field sensor (e.g., lateral bipolar transistor):
This subclass is indented under subclass 421. Subject matter wherein the active solid-state device includes a bipolar transistor as the magnetic field sensor.

Sensor with region of high carrier recombination (e.g., magnetodiode with carriers deflected to recombination region by magnetic field):
This subclass is indented under subclass 421. Subject matter wherein the device has a region of high carrier recombination, e.g., a magnetodiode with carriers deflected to the recombination region by the magnetic field.

Magnetic field detector using compound semiconductor material (e.g., GaAs, InSb, etc.):
This subclass is indented under subclass 421. Subject matter wherein the device is made of a compound semiconductor material (e.g., GaAs, InSb, etc.).

Differential output (e.g., with offset adjustment means or with means to reduce temperature sensitivity):
This subclass is indented under subclass 421. Subject matter wherein the device has two output terminals and the electrical signal generated by the active solid-state device is the electrical signal difference between the outputs.

Magnetic field sensor in integrated circuit (e.g., in bipolar
transistor integrated circuit):
This subclass is indented under subclass 421. Subject matter wherein the device is located in an integrated circuit (i.e., a solid monolithic semiconductor chip).

Electromagnetic or particle radiation:
This subclass is indented under subclass 414. Subject matter wherein the electrical signal is generated by the device in response to radiant energy in the electromagnetic energy spectrum or in the form of neutral or charged particles (e.g., alpha or beta particles).

Charged or elementary particles:
This subclass is indented under subclass 428. Subject matter wherein the particle energy is in the form of electrically charged or elementary particles (e.g., alpha or beta particles).

With active region having effective impurity concentration less than 10[supscrpt]12[end supscrpt] atoms/cm[supscrpt]3[end supscrpt]:
This subclass is indented under subclass 429. Subject matter wherein the active region of the device has an effective impurity ion dopant concentration less than 10[supscrpt]12[end supscrpt] atoms/cm[supscrpt]3[end supscrpt].

Light:
This subclass is indented under subclass 428. Subject matter wherein the non-electrical signal to which the device responds is electromagnetic energy in the light frequency/wavelength range (i.e., from infrared (except where the response is mainly due to thermal heating due to the infrared radiation) to visible and ultraviolet).

SEE OR SEARCH THIS CLASS, SUBCLASS:
21 for light responsive superlattice quantum well heterojunction tunneling devices.
53 through 56, for amorphous semiconductor junction material devices which are responsive to non-electrical (e.g., light) signals.
80 through 85, for light emitters combined with or also constituting a light responsive device.
113 through 118, for light activated regenerative type devices.
184 through 189, for light responsive heterojunction devices in non-charge transfer devices.
225 through 234, for charge transfer devices with non-electrical (e.g., light) input.
257 through 258, for light responsive JFET devices.
290 through 294, for light responsive insulated electrode field effect devices.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 54 for methods of making a temperature responsive semiconductor device.

With optical element:
This subclass is indented under subclass 431. Subject matter wherein the light incident upon the active region passes through an optical element (e.g., a fiber, lens, filter, etc.).

With housing or encapsulation:
This subclass is indented under subclass 431. Subject matter wherein means is provided to physically protect the device in the form of a housing or medium which embeds the device.

With window means:
This subclass is indented under subclass 433. Subject matter with means to optically couple the light to the device through a transparent window.

With optical shield or mask means:
This subclass is indented under subclass 431. Subject matter with means to spatially or temporally block all or part of the light incident on the portions of the device receptor region, other than the intended region.

With means for increasing light absorption (e.g., redirection of unabsorbed light):
This subclass is indented under subclass 431. Subject matter with means for increasing the amount of light absorbed by the device (e.g., antireflection coatings applied to the device, doping with energy converters, providing reflectors to redirect initially unabsorbed light onto the receptor, etc.).

Antireflection coating:
This subclass is indented under subclass 436. Subject matter wherein the means for increasing light absorption by the junction is a coating applied to the device which reduces reflection of the incident light (e.g., by use of interference films).

Avalanche junction:
This subclass is indented under subclass 431. Subject matter wherein the device has a junction which is operated in the avalanche portion of its operating curve to utilize the avalanche multiplication of photocurrent by means of hole-electron pairs created by absorbed photons.
(1) Note. When the reverse bias voltage applied to the device approaches breakdown level, the holes or electrons collide with substrate atoms to produce an avalanche of
hole-electron pairs.

Containing dopant adapted for photoionization:
This subclass is indented under subclass 431. Subject matter wherein the junction region is provided with impurity dopant atoms which are only ionized to produce free carriers by the incident light.

With different sensor portions responsive to different wavelengths (e.g., color imager):
This subclass is indented under subclass 431. Subject matter wherein the device has different portions, some of which respond to different wavelengths of light than do others.

Narrow band gap semiconductor (<<1eV) (e.g., PbSnTe):
This subclass is indented under subclass 431. Subject matter wherein the device contains a semiconductor material which has a gap between its conduction and valence bands which is less than one electron volt.

II-VI compound semiconductor (e.g., HgCdTe):
This subclass is indented under subclass 441. Subject matter wherein the narrow band gap semiconductor is a compound semiconductor taken from columns II and VI of the periodic table.

Matrix or array (e.g., single line arrays):
This subclass is indented under subclass 431. Subject matter wherein the device is in the form of regularly spaced individual light responsive elements.

Light sensor elements overlie active switching elements in integrated circuit (e.g., where the sensor elements are deposited on an integrated circuit):
This subclass is indented under subclass 443. Subject matter wherein the active switching elements are in a monolithic chip which is combined with an array of light responsive elements which overlie the former.

With antiblooming means:
This subclass is indented under subclass 443. Subject matter with means to prevent more than one individual light responsive element from being activated by a very bright spot of light incident on a point of the matrix or array.
(1) Note. The anti-blooming means may drain charge from adjacent individual array elements to some other area, e.g., the substrate. This is known as an overflow drain.

With specific isolation means in integrated circuit:
This subclass is indented under subclass 443. Subject matter wherein the matrix or array of devices is provided with means to electrically isolate the device from other devices and the overall device is contained in a monolithic semiconductor chip.

With backside illumination (e.g., having a thinned central area or a non-absorbing substrate):
This subclass is indented under subclass 443. Subject matter wherein the matrix or array device is structured to permit incident light to reach the receptor region from the backside of the device.

With particular electrode configuration:
This subclass is indented under subclass 443. Subject matter wherein the matrix or array device has a particular electrode arrangement.

Schottky barrier (e.g., a transparent Schottky metallic layer or a Schottky barrier containing at least one of indium or tin (e.g., SnO[subscrpt]2[end subscrpt], indium tin oxide)):
This subclass is indented under subclass 431. Subject matter wherein the device has a rectifying junction which is formed between a metal and a semiconductor material (i.e., a Schottky barrier).
(1) Note. The Schottky barrier may, for example, be transparent or contain indium or tin (e.g., SnO[subscrpt]2[end subscrpt], indium tin oxide).

With doping profile to adjust barrier height:
This subclass is indented under subclass 449. Subject matter wherein the height of the Schottky barrier is changed by varying the concentration of the impurity dopant in the semiconductor portion of the active junction region of the device.

Responsive to light having lower energy (i.e., longer wavelength) than forbidden band gap energy of semiconductor (e.g., by excitation of carriers from metal into semiconductor):
This subclass is indented under subclass 449. Subject matter wherein the device responds to light having lower energy than the energy difference between the bottom of the conduction band and the top of the valance band of the semiconductor material that forms a junction with the metal.
(1) Note. One way to achieve this result is to photoelectrically excite electrons from the metal adjacent the semiconductor into the semiconductor.

With edge protection, e.g., doped guard ring or mesa
structure:
This subclass is indented under subclass 449. Subject matter wherein means is provided to reduce electric field concentration or breakdown at edges of the metal and semiconductor.

With specified Schottky metallic layer:
This subclass is indented under subclass 449. Subject matter wherein the device includes a layer of metal which has a specified chemical composition.

Schottky metallic layer is a silicide:
This subclass is indented under subclass 453. Subject matter wherein the specified Schottky material layer is a compound of metal and silicon.

Silicide of Platinum group metal:
This subclass is indented under subclass 454. Subject matter wherein the Schottky layer is a silicide of a metal found in the period table listed as a platinum group metal (i.e., ruthenium, rhodium, palladium, osmium, iridium, and platinum).

Silicide of refractory metal:
This subclass is indented under subclass 454. Subject matter wherein the Schottky layer comprises a silicide of the refractory metals (i.e., W, Ti, Ta, Hf, Zr, V, Nb, Mo, and Cr).

With particular contact geometry (e.g., ring or grid):
This subclass is indented under subclass 449. Subject matter
wherein the device has a specific geometrical arrangement of electrical contacts.

PIN detector, including combinations with non-light responsive active devices:
This subclass is indented under subclass 431. Subject matter wherein the device has a pn junction with an intrinsic semiconductor material region (i.e., one with no deliberate impurity dopants) portion between the p- and n-impurity doped regions.

With particular contact geometry (e.g., ring or grid, or bonding pad arrangement):
This subclass is indented under subclass 431. Subject matter wherein the device has a specified electrical contact geometry.

With backside illumination (e.g., with a thinned central area or non-absorbing substrate):
This subclass is indented under subclass 431. Subject matter wherein the device is structured to permit incident light to reach the receptor portion from the backside of the device.

Light responsive pn junction:
This subclass is indented under subclass 431. Subject matter wherein the device has a junction between p-type and n-type material which responds to light incident upon it by generating a signal proportional thereto.

Phototransistor:
This subclass is indented under subclass 461. Subject matter wherein the pn junction device is a transistor wherein the
device generates an electrical signal in response to light incident on the transistor.

With particular doping concentration:
This subclass is indented under subclass 461. Subject matter wherein the pn junction has a particular impurity dopant concentration or spatial distribution.

With particular layer thickness (e.g., layer less than light absorption depth):
This subclass is indented under subclass 461. Subject matter wherein the thickness of the junction region is of a specified thickness (e.g., less than the thickness in which light is absorbed).

Geometric configuration of junction (e.g., fingers):
This subclass is indented under subclass 461. Subject matter wherein the junction has a specified geometrical configuration (e. g., finger shaped).

External physical configuration of semiconductor (e.g., mesas, grooves):
This subclass is indented under subclass 431. Subject matter wherein the device has a specified external configuration (e.g., with mesas).

Temperature:
This subclass is indented under subclass 414. Subject matter wherein the non-electrical signal to which the device responds is thermal energy.
(1) Note. Infrared energy incident on the active junction
which does not cause significant thermal heating of the device is classified in subclass 431.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 54 for methods of making a temperature responsive semiconductor device.

Semiconductor device operated at cryogenic temperature:
This subclass is indented under subclass 467. Subject matter wherein means are provided to cool the device for operation at cryogenic levels (e.g., below 100 degrees Kelvin).

With means to reduce temperature sensitivity (e.g., reduction of temperature sensitivity of junction breakdown voltage by using a compensating element):
This subclass is indented under subclass 467. Subject matter wherein means are provided to reduce the sensitivity of the electrical output of the device to changes in temperature of the device.

Pn junction adapted as temperature sensor:
This subclass is indented under subclass 467. Subject matter wherein the active junction is a pn junction (i.e., forms a boundary between p-type and n-type carrier materials) and generates an electrical signal in response to thermal energy incident upon the active junction.

SCHOTTKY BARRIER:
This subclass is indented under the class definition. Subject matter wherein the device contains a Schottky barrier (i.e., a rectifying interface between a semiconductor material and a metal).

SEE OR SEARCH THIS CLASS, SUBCLASS:
54 for Schottky barrier to amorphous semiconductor material device.
73 for Schottky barrier to polycrystalline semiconductor material device.
155 for a regenerative type switching device with switching speed enhancement means (e.g., a Schottky contact).
260 for JFET having the same channel controlled by, for example, Schottky barrier and PN junction gates.
280 through 284, for JFETs with a Schottky gate electrode.
449 through 457, for a light responsive device with a Schottky barrier.
928 for a shorted pn or Schottky junction device.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 570 for methods of forming a rectifying (Schottky) contact to a semiconductor.

To compound semiconductor:
This subclass is indented under subclass 471. Subject matter wherein the Schottky metal is interfaced with a compound semiconductor.

With specified Schottky metal:
This subclass is indented under subclass 472. Subject matter wherein the Schottky metal interfaced with the compound semiconductor is specifically claimed.

As active junction in bipolar transistor (e.g., Schottky collector):
This subclass is indented under subclass 471. Subject matter wherein the Schottky barrier junction is used as an active bipolar transistor junction (e.g., a Schottky collector).

With doping profile to adjust barrier height:
This subclass is indented under subclass 471. Subject matter wherein the difference in electrical potential from one side of an active junction to the other has been adjusted by a distribution of impurity dopant in the semiconductor adjacent the Schottky junction.

In integrated structure:
This subclass is indented under subclass 471. Subject matter wherein the Schottky barrier device is located in a single monolithic integrated semiconductor chip.

With bipolar transistor:
This subclass is indented under subclass 476. Subject matter wherein the Schottky barrier device is located in a single integrated monolithic semiconductor chip with a bipolar transistor.

Plural Schottky barriers with different barrier heights:
This subclass is indented under subclass 477. Subject matter wherein the integrated circuit containing a Schottky barrier device contains more than one Schottky barrier with different potential differences existing across the different barriers.

Connected across base-collector junction of transistor (e.g., Baker clamp):
This subclass is indented under subclass 477. Subject matter wherein a Schottky barrier device is electrically connected across the base-collector junction of a bipolar transistor.

In voltage variable capacitance diode:
This subclass is indented under subclass 471. Subject matter wherein the Schottky barrier is used in a variable capacitance diode (e.g., "varactor").

Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts):
This subclass is indented under subclass 471. Subject matter wherein the Schottky barrier is in a device designed to operate in avalanche breakdown.

SEE OR SEARCH THIS CLASS, SUBCLASS:
199 for an avalanche diode in a non-charge transfer device having a heterojunction.
551 for an avalanche diode used as a voltage reference element combined with pn junction isolation means in an integrated circuit.
603 through 606, for avalanche diodes not classified above those subclasses in this schedule, i.e., not involving a heterojunction in a non-charge transfer device, or a Schottky barrier, or one used as a voltage reference element with pn junction isolation means in an integrated circuit.

Microwave transit time device (e.g., IMPATT diode):
This subclass is indented under subclass 481. Subject matter wherein the avalanche breakdown provides a power oscillation in the microwave region.

With means to prevent edge breakdown:
This subclass is indented under subclass 471. Subject matter wherein the Schottky barrier device has means which help to reduce the electrical field around the edge of the device.

Guard ring:
This subclass is indented under subclass 483. Subject matter wherein the means to prevent edge breakdown is a guard ring (e.g., a pn junction surrounding the periphery of the Schottky metal).

Specified materials:
This subclass is indented under subclass 471. Subject matter wherein the Schottky barrier device uses a material of specified composition.

Layered (e.g., a diffusion barrier material layer or a silicide layer or a precious metal layer):
This subclass is indented under subclass 485. Subject matter wherein the material, e.g., metal, which forms the Schottky barrier is comprised of layers, for example, a diffusion barrier material layer or a silicide layer or a precious metal layer.

WITH MEANS TO INCREASE BREAKDOWN VOLTAGE THRESHOLD:
This subclass is indented under the class definition. Subject matter wherein the device is provided with means to increase the voltage that may be applied thereto without causing electrical breakdown.

Field relief electrode:
This subclass is indented under subclass 487. Subject matter wherein the means to increase breakdown voltage comprises an electrode insulated from the semiconductor material of the active solid-state device, and configured so as to reduce the electric field strength at a given voltage applied to the device.

Resistive:
This subclass is indented under subclass 488. Subject matter wherein the field relief electrode is a high resistance layer adapted to have a current flow therethrough and a corresponding voltage variation therein.

Combined with floating pn junction guard region:
This subclass is indented under subclass 488. Subject matter wherein the means for increasing breakdown voltage includes, in addition to a field relief electrode, a floating pn junction guard region, i.e., a region free of direct electrical connection located in the material forming one side of an active pn, or other rectifying semiconductor junction, which region forms a pn junction with the material of the one side of the active junction, the guard region being spaced from the active junction, but sufficiently close thereto that the reverse bias depletion region from the active junction can reach the guard junction, whereby the guard junction modifies the shape of the depletion region from the active junction thus lowering the electric field intensity at a given applied reverse voltage across the active junction.

In integrated circuit:
This subclass is indented under subclass 487. Subject matter wherein the device with means to increase breakdown voltage is combined in a unitary monolithic semiconductor chip with other active or passive electronic devices.
(1) Note. The means for increasing breakdown voltage in the integrated circuit active device may include a floating pn junction guard region, that is, a region, free of direct electrical connection, located in the material forming one side of an active pn or other rectifying semiconductor junction, which region forms a pn junction with the material of the one side of the active junction, the guard region being spaced from the active junction but sufficiently close thereto that the reverse bias depletion region from the active junction can reach the guard junction, whereby the guard junction modifies the shape of the depletion region from the active junction thus lowering the electric field intensity at a given applied reverse voltage across the active junction.
(2) Note. The means for increasing the breakdown voltage of the integrated circuit device may include a semiconductor surface portion having a physical configuration, such as a bevel or mesa, to reduce electric field strength at a given applied voltage. Typically, the physical configuration will be such that the depletion region from a reverse biased junction in the active device reaches the physically configured surface and is forced by the shape of the surface to spread wider at a given applied reverse voltage than it would otherwise, thus reducing the electric field strength in the depletion layer.

With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices):
This subclass is indented under subclass 491. Subject matter wherein the means to increase breakdown voltage of the device includes a layer of semiconductor material having a sufficiently low doping concentration that it may be fully depleted by the depletion region of a reverse biased junction of the active device prior to avalanche breakdown of the active device, so that upon depletion of the layer of semiconductor material, the effective width of the depletion layer of the reverse biased junction of the active device is greatly expanded, thus resulting in smaller increases in electric field intensity with further increases of reverse voltage.
(1) Note. Devices provided with such a layer are sometimes called "RESURF" (Reduced SURFace Field) devices.
(2) Note. In silicon, to be fully depleted without avalanche breakdown, a layer must typically have an integrated doping density (the line integral of doping density along a path through the thickness of the layer) of less than 2x10[supscrpt]12[end supscrpt] dopant atoms/cm[supscrpt]2[end supscrpt]. The critical integrated doping density varies depending on the properties of the particular semiconductor material.

With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices):
This subclass is indented under subclass 487. Subject matter wherein the means to increase breakdown voltage of the device
includes a layer of semiconductor material having a sufficiently low doping concentration that it may be fully depleted by the depletion region of a reverse biased junction of the active device prior to avalanche breakdown of the active device, so that upon depletion of the layer of semiconductor material, the effective width of the depletion layer of the reverse biased junction of the active device is greatly expanded, thus resulting in smaller increases in electric field intensity with further increases of reverse voltage.

Reverse-biased pn junction guard region:
This subclass is indented under subclass 487. Subject matter wherein the means for increasing breakdown voltage in the device includes a reverse biased pn junction guard region, that is, a region located in the material forming one side of an active pn or other rectifying semiconductor junction, which region forms a pn junction with the material of the one side of the active junction, the guard region being adapted to be reverse biased with respect to the material forming one side of the active junction, and being spaced from the active junction, but sufficiently close thereto that the reverse bias depletion region from the active junction can reach the depletion region from the reverse biased guard junction, whereby the depletion region of the guard junction modifies the shape of the depletion region from the active junction thus lowering the electric field intensity at a given applied reverse voltage across the active junction.

Floating pn junction guard region:
This subclass is indented under subclass 487. Subject matter wherein the means for increasing breakdown voltage in the device includes a floating pn junction guard region, that is, a region, free of direct electrical connection, located in the material forming one side of an active pn or other rectifying semiconductor junction, which region forms a pn junction with the material of the one side of the active junction, the guard region being spaced from the active junction, but sufficiently close thereto that the reverse bias depletion region from the active junction can reach the guard junction, whereby the guard junction modifies the shape of the depletion region from the active junction thus lowering the electric field intensity at a given applied reverse voltage across the active junction.

With physical configuration of semiconductor surface to reduce electric field (e.g., reverse bevels, double bevels, stepped mesas, etc.):
This subclass is indented under subclass 487. Subject matter wherein the means to increase breakdown voltage includes a semiconductor surface portion having a physical configuration, such as a bevel or mesa, to reduce electric field strength at a given applied voltage. Typically, the physical configuration will be such that the depletion region from a reverse biased junction in the active device reaches the physically configured surface and is forced by the shape of the surface to spread wider at a given applied reverse voltage than it would otherwise, thus reducing the electric field strength in the depletion layer.

PUNCHTHROUGH STRUCTURE DEVICE (E.G., PUNCHTHROUGH TRANSISTOR, CAMEL BARRIER DIODE):
This subclass is indented under the class definition. Subject matter having at least one active pn, Schottky barrier, or other rectifying junction which can be reverse biased to produce a depletion layer, the active junction being spaced from a second junction by a layer of semiconductor material in which the depletion region extending from the active junction is produced, the second junction being one capable of supplying minority carriers to the layer of semiconductor material upon forward bias of the second junction, and in which the second junction is located sufficiently close to the active junction that the depletion region from the active junction can reach the second junction, thereby forward biasing the second junction and causing the injection of minority carriers therefrom which traverse the depletion layer and reach the active junction.

SEE OR SEARCH THIS CLASS, SUBCLASS:
361 for punchthrough structure elements used to protect against overvoltage gate insulator breakdown of insulated gate devices.

Punchthrough region fully depleted at zero external applied bias voltage (e.g., camel barrier or planar doped barrier devices, or so-called "Bipolar SIT" devices):
This subclass is indented under subclass 497. Subject matter wherein the active junction and the second junction are
sufficiently closely spaced that the depletion region from the active junction due to the built-in potential of the active junction reaches the second junction even in the absence of a reverse bias voltage across the active junction.

INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS:
This subclass is indented under the class definition. Subject matter wherein at least one active solid-state device is provided in a single, monolithic semiconductor chip along with other active or passive elements in the chip, and means are provided to electrically isolate different devices in the monolithic chip from each other.

SEE OR SEARCH THIS CLASS, SUBCLASS:
7 for intervalley transfer bulk effect devices (e.g., Gunn effect devices) in a monolithic integrated circuit.
93 for plural light emitting devices with electrical isolation means in integrated circuit structure.
265 for JFET devices having vertical current path in integrated circuit.
272 through 278, for JFET devices in integrated circuits.
334 for short channel IGFET devices having a gate electrode controlling the vertical portion of the channel and being in a groove in an integrated circuit.
337 and 338, for graded channel short channel IGFET devices in integrated circuit structure.
357 through 359, for insulated electrode field effect devices with gate insulator overvoltage protection means in complementary field effect transistor integrated circuit devices.
368 through 401, for IGFET devices in integrated circuit.
427 for a magnetic field sensor in an integrated circuit.
446 for matrix or array type photodetectors with specific isolation means in an integrated circuit.
491 and 492, for devices with means to increase breakdown voltage in an integrated circuit, including, for example, RESURF devices.
663 for a superconductive contact or lead on an integrated
circuit.
713 for cooling means for an integrated circuit device.
758 through 760, for multi-level metallization in, e.g., an integrated circuit device.
922 for a device with means to prevent inspection of or tampering with an integrated circuit.
929 for pn junction isolated integrated circuits with isolation walls having minimum dopant concentration at intermediate depth in epitaxial layer.

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly 294 for methods of making laterally spaced, electrically isolated semiconductor regions in combination with insulated gate field effect transistors; subclasses 353+ for methods of making laterally spaced, electrically isolated semiconductor regions in combination with bipolar transistors; and subclasses 400+ for methods of making laterally spaced, electrically isolated semiconductor regions or various

Including high voltage or high power devices isolated from low voltage or low power devices in the same integrated circuit:
This subclass is indented under subclass 499. Subject matter wherein the monolithic chip includes both electronic components specifically configured for operation at high voltages or high power levels, along with other electronic components which are configured for operation only at low voltages or power levels.
(1) Note. See this class, subclass 491 for monolithic chips which include active components with specific means provided to increase the breakdown voltage of those active components. The combination of high voltage and low voltage active solid-state devices on the same monolithic chip will only be classified in this subclass (500), if no particular structure is provided to increase the breakdown voltage of the high voltage components.

Including dielectric isolation means:
This subclass is indented under subclass 500. Subject matter
wherein the means to electrically isolate different devices in the same monolithic chip, containing both high voltage or power and low voltage or power devices, from each other includes a region of electrical insulator material.

High power or high voltage device extends completely through semiconductor substrate (e.g., backside collector contact):
This subclass is indented under subclass 500. Subject matter wherein at least one high voltage or high power device extends completely through the monolithic chip from the top surface to the bottom surface of the chip.

With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit):
This subclass is indented under subclass 499. Subject matter wherein the chip includes contacts or electrical interconnections, such as metal strips deposited on the surface of the chip, which contacts or interconnections are configured in such a manner as to reduce or eliminate unwanted parasitic coupling of electrical signals from one part or component of the integrated circuit to another.
(1) Note. Such configuration might be, for example, a shielding conductive layer connected to fixed potential, or large area metal pads for connection to external supply voltages with plural separate pads provided to connect different parts or components of the same integrated circuit to the same external voltage, to prevent voltage drops from electrical current flowing between a pad and one component from producing a parasitic varying voltage applied to another component.

SEE OR SEARCH THIS CLASS, SUBCLASS:
659 for electrical shielding, in general, in active solid-state devices.
664 for transmission line connections, in general, in active solid-state devices.

Including means for establishing a depletion region throughout a semiconductor layer for isolating devices in
different portions of the layer (e.g., "JFET" isolation):
This subclass is indented under subclass 499. Subject matter wherein means are provided for producing a region in a layer which is fully depleted of charge carriers and thereby non-conductive as part of the means for electrically isolating different devices in the chip from each other.

With polycrystalline semiconductor isolation region in direct contact with single crystal active semiconductor material:
This subclass is indented under subclass 499. Subject matter wherein the means for electrically isolating different devices in the chip from each other includes at least one region of polycrystalline (i.e., made up of many small crystals) semiconductor material, which polycrystalline isolation region is in direct contact with at least one region of single crystal semiconductor material which forms part of an active solid-state device in the chip.
(1) Note. The polycrystalline isolation region may be either undoped or doped with recombination center doping, in order to make it high resistivity and thus, effectively, an electrical insulator, or may be doped with a p or n dopant in order to form a pn junction with the single crystal material of the active solid-state device so that the rectifying junction between the doped isolation region and the single crystal active portion, when reverse biased, electrically isolates the devices in the chip from each other.

Including dielectric isolation means:
This subclass is indented under subclass 499. Subject matter wherein the means to electrically isolate different devices in the same monolithic chip from each other includes a region of electrical insulator material.

With single crystal insulating substrate (e.g., sapphire):
This subclass is indented under subclass 506. Subject matter wherein the means to electrically isolate different devices from each other includes a substrate of single crystal insulating material, upon which the semiconductor material of the active devices is grown in heteroepitaxial relationship therewith.
(1) Note. The substrate may typically be the alpha crystalline phase of aluminum oxide, commonly called sapphire or single crystalline beryllium oxide or single crystal magnesium aluminate known as spinel.

With metallic conductor within isolating dielectric or between semiconductor and isolating dielectric (e.g., metal shield layer or internal connection layer):
This subclass is indented under subclass 506. Subject matter wherein a metallic (metal or metal-like) conductor is located within the region of electrical insulator material which isolates the components on the chip from each other or is provided between the single crystal semiconductor material of the semiconductor components and the electrical insulator material forming the dielectric isolation.
(1) Note. The metallic conductor may be used to provide interconnections between components on the chip or as an electrical shielding layer.

Combined with pn junction isolation (e.g., isoplanar, LOCOS):
This subclass is indented under subclass 506. Subject matter wherein the means for electrically isolating components in the chip from each other includes, in addition to portions of electrical insulator material, pn junctions separating regions of active devices from each other and/or from a supporting semiconductor substrate.
(1) Note. There are several names in common use for isolation of this type, particularly where the pn junctions provide isolation between active devices and the supporting semiconductor substrate with the dielectric material recessed into the semiconductor between active devices and extending down to the isolating pn junctions to separate devices laterally from each other. Such common names include LOCOS (Local Oxidation of Silicon), ROI (Recessed Oxide Isolation), Isoplanar, and Planox. These terms do not represent different isolation structures, but are merely alternative names for the same type of isolation.

Dielectric in groove:
This subclass is indented under subclass 509. Subject matter wherein the electrical insulator material forming part of the isolation means is located in grooves in the semiconductor surface (e.g., LOCOS)

SEE OR SEARCH THIS CLASS, SUBCLASS:
374 for CMOS FET dielectric isolation means (e.g., dielectric layer in vertical groove.)

With complementary (npn and pnp) bipolar transistor structures:
This subclass is indented under subclass 509. Subject matter wherein the device includes, on the same monolithic chip, both pnp bipolar transistors and npn bipolar transistor structures.

Complementary devices share common active region (e.g., integrated injection logic, I[supscrpt]2[end supscrpt]L):
This subclass is indented under subclass 511. Subject matter wherein the device includes structures wherein a pnp transistor shares a semiconductor region with an npn transistor, e.g., where the base region of the pnp transistor serves also as the emitter of the npn transistor and the collector of the pnp transistor serves as the base region of the npn transistor.
(1) Note. Search this class, subclass 107 for regenerative switching devices, which typically are in the form of a pnp transistor and an npn transistor, the collector and base of the pnp transistor forming the base and collector, respectively, of the npn transistor.
(2) Note. A typical structure in which pnp transistors and npn transistors share regions in common is that called Integrated injection logic, I[supscrpt]2[end supscrpt]L (formerly alternatively called merged transistor logic, MTL), in which a pnp transistor serves to supply base region current to a multicollector npn transistor, with the base region of the npn being the logic circuit input and the multiple collectors providing logic fan out to plural further logic gates.

Vertical walled groove:
This subclass is indented under subclass 510. Subject matter wherein the dielectric isolation is located in grooves in the surface of the overall device which extend perpendicular to the surface of the overall device.

With active junction abutting groove (e.g., "walled emitter"):
This subclass is indented under subclass 513. Subject matter wherein at least one pn junction forming a part of an active solid-state device terminates against the dielectric filling in the vertical walled isolation groove.
(1) Note. If the emitter-base junction terminates against a dielectric isolation sidewall, this is termed a "walled emitter" transistor structure.

With active junction abutting groove (e.g., "walled emitter"):
This subclass is indented under subclass 510. Subject matter wherein at least one pn junction forming a part of an active solid-state device terminates against the dielectric filling in the isolation groove.

With passive component (e.g., resistor, capacitor, etc.):
This subclass is indented under subclass 510. Subject matter wherein the device contains, in addition to at least one active solid-state device, at least one passive component, such as a resistor or capacitor.

With bipolar transistor structure:
This subclass is indented under subclass 510. Subject matter wherein the device contains at least one bipolar transistor structure.

With polycrystalline connecting region (e.g., polysilicon base contact):
This subclass is indented under subclass 517. Subject matter wherein the device has portions of polycrystalline (i.e., made up of many small crystals) semiconductor material serving as electrical contacts or connections.

Including heavily doped channel stop region adjacent groove:
This subclass is indented under subclass 510. Subject matter wherein the device has at least one heavily doped semiconductor region adjacent a dielectric filled groove to prevent formation of parasitic inversion channels in the semiconductor material.

Conductive filling in dielectric-lined groove (e.g., polysilicon backfill):
This subclass is indented under subclass 510. Subject matter wherein the device has the grooves filled with a lining of dielectric material together with a conductive filling in the groove, the conductive filling being separated from the semiconductor material by the dielectric lining of the groove.

Sides of grooves along major crystal planes (e.g., (111), (100) planes, etc.):
This subclass is indented under subclass 510. Subject matter wherein the device has grooves for the isolation whose sides are oriented along one or more major crystal planes of the semiconductor material in which the grooves are formed.
(1) Note. Major crystal planes are considered to be the (111), (110), and (100) planes in a crystal with cubic symmetry.
(2) Note. See illustration, below. [figure]

Air isolation (e.g., beam lead supported semiconductor islands):
This subclass is indented under subclass 506. Subject matter wherein the isolation means is air (e.g., islands of semiconductor material supported by beam leads and separated by air).

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly subclass 411 for methods of forming electrically isolated semiconductor islands held in place by beam lead metallization; subclass 461 for methods of forming beam leads on a semiconductor substrate combined with dicing of the substrate into plural separate bodies; and subclass 611 for methods of forming beam lead metallization on a semiconductor substrate.

Isolation by region of intrinsic (undoped) semiconductor material (e.g., including region physically damaged by proton bombardment):
This subclass is indented under subclass 506. Subject matter wherein the electrical insulator material which provides the dielectric isolation includes a region of intrinsic (undoped) semiconductor material, with resulting high resistivity.
(1) Note. The isolation region may contain a region which has been physically damaged by proton bombardment or by other means.

Full dielectric isolation with polycrystalline semiconductor substrate:
This subclass is indented under subclass 506. Subject matter wherein the integrated circuit substrate is made of polycrystalline semiconductor material and the isolation means is a dielectric material which surrounds each active solid-state semiconductor device, resulting is those devices becoming islands in a sea of dielectric material.

With complementary (npn and pnp) bipolar transistor structures:
This subclass is indented under subclass 524. Subject matter wherein the device includes complementary bipolar transistors (i.e., includes both pnp and npn bipolar transistors).
(1) Note. The device may include complementary lateral bipolar transistor structures.

With bipolar transistor structure:
This subclass is indented under subclass 524. Subject matter wherein the device includes at least one bipolar transistor structure.

Sides of isolated semiconductor islands along major crystal planes (e.g., (111), (100) planes, etc.):
This subclass is indented under subclass 524. Subject matter wherein the device has sides of the isolated single crystal semiconductor islands which are oriented along one or more major crystal planes of the semiconductor material of the islands.

Passive components in ICs:
This subclass is indented under subclass 499. Subject matter wherein the device is contained in a single, monolithic chip with electrical components which are passive, i.e., which do not have gain, for example, pure capacitors, inductors, or resistors.

SEE OR SEARCH THIS CLASS, SUBCLASS:
379 for a passive component combined with an IGFET device in an integrated circuit.
516 for passive components in an integrated circuit with dielectric in groove and pn junction isolation.
904 for a FET combined with passive components adapted for use as a static memory cell.

Including programmable passive component (e.g., fuse):
This subclass is indented under subclass 528. Subject matter wherein a passive component is programmable, i.e., may be permanently altered (e.g., a fuse - a protective device designed to open a circuit in response to an excessive current).

SEE OR SEARCH CLASS:
438, Semiconductor Device Manufacturing: Process, particularly subclass 467, 600, and 601 for methods of forming or modifying electrically alterable structures for selectively interconnecting electrical devices on a semiconductor substrate.

Anti-fuse:
This subclass is indented under subclass 529. Subject matter wherein an element which is normally non-conductive is made conductive (e.g., a capacitor) that is, that can be selectively electrically shorted.

Including inductive element:
This subclass is indented under subclass 528. Subject matter wherein the device includes an electrical inductor, i.e., an element that tends to oppose any change of current applied thereto because of a magnetic field generated by the inductor itself.

Including capacitor component:
This subclass is indented under subclass 528. Subject matter wherein the device includes an electrical capacitor, i.e., a passive element with electrical conductors separated by a dielectric material which stores electrical charge when potential differences exist between the conductive elements of the capacitor.

Combined with resistor to form RC filter structure:
This subclass is indented under subclass 532. Subject matter wherein the capacitor element is combined with an electrical resistance element to form an electrical filter in the form of an integrated RC filter circuit.

With means to increase surface area (e.g., grooves, ridges, etc.):
This subclass is indented under subclass 532. Subject matter wherein the device includes means to increase the surface area of the device by, for example, grooves or ridges in the surface of the device.

Both terminals of capacitor isolated from substrate:
This subclass is indented under subclass 532. Subject matter wherein the device includes a capacitor, both terminals of which are electrically isolated from the integrated circuit chip substrate.

Including resistive element:
This subclass is indented under subclass 528. Subject matter wherein the device includes an electrical resistance element.

Using specific resistive material:
This subclass is indented under subclass 536. Subject matter wherein the passive resistive element is a specific chemical element, compound, or composition.

Polycrystalline silicon (doped or undoped):
This subclass is indented under subclass 537. Subject matter wherein the specific resistive material is a silicon material made up of many single crystals having a random orientation.

Combined with bipolar transistor:
This subclass is indented under subclass 536. Subject matter wherein the device includes at least one bipolar transistor structure along with the resistive element.

With compensation for non-linearity (e.g., dynamic isolation pocket bias):
This subclass is indented under subclass 539. Subject matter wherein means are provided to compensate for non-linearity of the resistor, such as by provision of varying bias voltage to a semiconductor pocket which forms a pn junction with the resistive element and provides electrical isolation therefor.

Pinch resistor:
This subclass is indented under subclass 539. Subject matter wherein the resistor element has a structure in the form of a layer of one conductivity type sandwiched between a pair of regions of opposite conductivity type, so that the upper region of opposite conductivity type restricts the thickness of the resistive layer and thus increases its resistivity.
(1) Note. Typically, the resistor will have the same doping profile as the base region of the bipolar transistor, while the lower opposite conductivity type region will have the same doping profile as the bipolar transistor collector, and the upper, or "pinching" region, will have the same doping profile as the bipolar transistor emitter.

Resistor has same doping as emitter or collector of bipolar transistor:
This subclass is indented under subclass 539. Subject matter
wherein the resistor region has the same doping concentration and profile (e.g., is formed in the same step as) either the emitter or the collector region of the bipolar transistor with which the resistor is combined in the same integrated circuit.
(1) Note. Most resistors in bipolar integrated circuits are formed with the same doping step as the bipolar transistor base regions. Resistors that are instead formed at the same doping step as the emitter or collector, rather than the base, go in this subclass.

Lightly doped junction isolated resistor (e.g., ion implanted resistor):
This subclass is indented under subclass 539. Subject matter wherein the resistive element is of the form of a lightly doped layer of one conductivity type located in a region of opposite conductivity type, such that the pn junction between the resistor region and its containing opposite conductivity type region serves to isolate the resistor.
(1) Note. A resistor region is considered to be lightly doped if it is substantially less heavily doped than the base region of the bipolar transistors in the same integrated circuit, or if it is has a doping density not greater than 100 times that of the opposite conductivity type region in which it is contained.
(2) Note. Such lightly doped resistors are typically formed by the process of ion implantation, wherein desired dopant atoms are placed in the semiconductor body by ionizing the dopant material and accelerating the resulting ions through a carefully controlled voltage to impinge on the surface of the semiconductor material, so that the depth of the resulting dopant atoms is determined by the accelerating voltage and the doping density is determined by the flux of the ion beam.

With pn junction isolation:
This subclass is indented under subclass 499. Subject matter wherein the means for electrically isolating different devices from each other includes a pn junction located between the devices to be isolated.

With means to control isolation junction capacitance (e.g., lightly doped layer at isolation junction to increase depletion layer width):
This subclass is indented under subclass 544. Subject matter wherein the device is provided with means, such as a lightly doped semiconductor layer at the isolation junction, to control (e.g., increase or decrease) the capacitance of the isolation junction.

With structural means to protect against excess or reversed polarity voltage:
This subclass is indented under subclass 544. Subject matter wherein means is provided to protect the circuit or its components from application of an excessive or reversed polarity voltage.

With structural means to control parasitic transistor action or leakage current:
This subclass is indented under subclass 544. Subject matter including means to control or reduce parasitic bipolar transistor action, i.e., bipolar transistor action in which the substrate and isolation junctions of the integrated circuit act as active junctions of an unintended bipolar transistor, or to control or reduce leakage currents associated with the pn isolation junctions.

At least three regions of alternating conductivity types with dopant concentration gradients decreasing from surface of semiconductor (e.g., "triple-diffused" integrated circuit):
This subclass is indented under subclass 544. Subject matter including at least three regions of alternating conductivity type (p or n), with each successive region contained within the previous region, and each of the regions having a doping concentration which decreases with distance from the same external surface of the semiconductor body.
(1) Note. Junction isolated integrated circuits of this type are typically manufactured by starting with an uniformly doped p-type semiconductor body to serve as the substrate, then diffusing spaced n-type regions into the P substrate to
form collectors of npn transistors, and then successively diffusing p-type base and n-type emitters into the spaced n-type regions. Junction isolated integrated circuits of this type are simple to manufacture, due to the reduced number of processing steps involved, but suffer from non-optimum doping concentration profiles, particularly in the collector regions.