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Class   716COMPUTER-AIDED DESIGN AND ANALYSIS OF CIRCUITS AND SEMICONDUCTOR MASKS
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 [List of Pre Grant Publications for class 716 subclass 30][List of Patents for class 716 subclass 30]30 NANOTECHNOLOGY RELATED INTEGRATED CIRCUIT DESIGN
[List of Pre Grant Publications for class 716 subclass 50][List of Patents for class 716 subclass 50]50 DESIGN OF SEMICONDUCTOR MASK OR RETICLE
[List of Pre Grant Publications for class 716 subclass 51][List of Patents for class 716 subclass 51]51 Subclass 51 indent level is 1 Analysis and verification (process flow, inspection)
 [List of Pre Grant Publications for class 716 subclass 52][List of Patents for class 716 subclass 52]52 Subclass 52 indent level is 2 Defect (including design rule checking)
 [List of Pre Grant Publications for class 716 subclass 53][List of Patents for class 716 subclass 53]53 Subclass 53 indent level is 2 Optical proximity correction (including RET)
 [List of Pre Grant Publications for class 716 subclass 54][List of Patents for class 716 subclass 54]54 Subclass 54 indent level is 1 Manufacturing optimizations
 [List of Pre Grant Publications for class 716 subclass 55][List of Patents for class 716 subclass 55]55 Subclass 55 indent level is 1 Layout generation (polygon, pattern feature)
 [List of Pre Grant Publications for class 716 subclass 56][List of Patents for class 716 subclass 56]56 Subclass 56 indent level is 1 Yield
[List of Pre Grant Publications for class 716 subclass 100][List of Patents for class 716 subclass 100]100 INTEGRATED CIRCUIT DESIGN PROCESSING
[List of Pre Grant Publications for class 716 subclass 101][List of Patents for class 716 subclass 101]101 Subclass 101 indent level is 1 Logic design processing
 [List of Pre Grant Publications for class 716 subclass 102][List of Patents for class 716 subclass 102]102 Subclass 102 indent level is 2 Design entry
 [List of Pre Grant Publications for class 716 subclass 103][List of Patents for class 716 subclass 103]103 Subclass 103 indent level is 2 Translation (logic-to-logic, logic-to-netlist, netlist processing)
[List of Pre Grant Publications for class 716 subclass 104][List of Patents for class 716 subclass 104]104 Subclass 104 indent level is 2 Logic circuit synthesis (mapping logic)
[List of Pre Grant Publications for class 716 subclass 106][List of Patents for class 716 subclass 106]106 Subclass 106 indent level is 2 Design verification (functional simulation, model checking)
[List of Pre Grant Publications for class 716 subclass 110][List of Patents for class 716 subclass 110]110 Subclass 110 indent level is 1 Physical design processing
[List of Pre Grant Publications for class 716 subclass 111][List of Patents for class 716 subclass 111]111 Subclass 111 indent level is 2 Verification
[List of Pre Grant Publications for class 716 subclass 116][List of Patents for class 716 subclass 116]116 Subclass 116 indent level is 2 Mapping circuit design to programmable logic devices (PLDs)
[List of Pre Grant Publications for class 716 subclass 118][List of Patents for class 716 subclass 118]118 Subclass 118 indent level is 2 Floorplanning
[List of Pre Grant Publications for class 716 subclass 126][List of Patents for class 716 subclass 126]126 Subclass 126 indent level is 2 Routing
[List of Pre Grant Publications for class 716 subclass 132][List of Patents for class 716 subclass 132]132 Subclass 132 indent level is 1 Optimization
 [List of Pre Grant Publications for class 716 subclass 133][List of Patents for class 716 subclass 133]133 Subclass 133 indent level is 2 For power
 [List of Pre Grant Publications for class 716 subclass 134][List of Patents for class 716 subclass 134]134 Subclass 134 indent level is 2 For timing
 [List of Pre Grant Publications for class 716 subclass 135][List of Patents for class 716 subclass 135]135 Subclass 135 indent level is 2 For area
 [List of Pre Grant Publications for class 716 subclass 136][List of Patents for class 716 subclass 136]136 Subclass 136 indent level is 1 Testing or Evaluating
 [List of Pre Grant Publications for class 716 subclass 137][List of Patents for class 716 subclass 137]137 Subclass 137 indent level is 1 PCB, MCM Design
 [List of Pre Grant Publications for class 716 subclass 138][List of Patents for class 716 subclass 138]138 Subclass 138 indent level is 1 System-on-chip design
 [List of Pre Grant Publications for class 716 subclass 139][List of Patents for class 716 subclass 139]139 Subclass 139 indent level is 1 Layout editor (with ECO, reuse, GUI)
 
FOREIGN ART COLLECTIONS
 
      FOR000          CLASS-RELATED FOREIGN DOCUMENTS
Any foreign patents or non-patent literature from subclasses that have been reclassified have been transferred directly to FOR Collections listed below. These Collections contain ONLY foreign patents or non-patent literature. The parenthetical references in the Collection titles refer to the abolished subclasses from which these Collections were derived.
  FOR100          CIRCUIT DESIGN (716/1)
      FOR101          Subclass FOR101 indent level is 1 Optimization (e.g., redundancy, compaction) (716/2)
      FOR102          Subclass FOR102 indent level is 1 Translation (e.g., conversion, equivalence) (716/3)
  FOR103          Subclass FOR103 indent level is 1 Testing or evaluating (716/4)
  FOR104          Subclass FOR104 indent level is 2 Design verification (e.g., wiring line capacitance, fanout checking, minimum path width) (716/5)
      FOR106          Subclass FOR106 indent level is 1 Partitioning (e.g., function block, ordering constraint) (716/7)
  FOR107          Subclass FOR107 indent level is 1 Floorplanning (716/8)
      FOR108          Subclass FOR108 indent level is 2 Detailed placement (i.e., iterative improvement) (716/9)
      FOR109          Subclass FOR109 indent level is 2 Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance) (716/10)
      FOR110          Subclass FOR110 indent level is 2 Layout editor (e.g., updating) (716/11)
  FOR111          Subclass FOR111 indent level is 1 Routing (e.g., routing map, netlisting) (716/12)
      FOR112          Subclass FOR112 indent level is 2 Global routing (e.g., shortest path, dead space, or duplicate trace elimination) (716/13)
      FOR113          Subclass FOR113 indent level is 2 Detailed routing (e.g., channel routing, switch box routing( (716/14)
      FOR114          Subclass FOR114 indent level is 2 PCB wiring (716/15)
      FOR115          Subclass FOR115 indent level is 2 PLA, PLD, FPGA, OR MCM (716/16)
      FOR116          Subclass FOR116 indent level is 1 Programmable integrated circuit (e.g., basic cell, standard cell, macrocell) (716/17)
      FOR117          Subclass FOR117 indent level is 1 Logical circuit synthesizer (716/18)
  FOR118          DESIGN OF SEMICONDUCTOR MASK (716/19)
      FOR119          Subclass FOR119 indent level is 1 Mesh generation (716/20)
      FOR120          Subclass FOR120 indent level is 1 Pattern exposure (716/21)
     APPLICATIONS (364/400)
  FOR489          Subclass FOR489 indent level is 1 Circuit design and analysis (364/489)
  FOR490          Subclass FOR490 indent level is 2 Integrated (364/490)
      FOR491          Subclass FOR491 indent level is 3 Layout (364/491)

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