Class   716	DATA PROCESSING: DESIGN AND ANALYSIS OF CIRCUIT OR SEMICONDUCTOR MASK
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CIRCUIT DESIGN

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. (1 indent ) Optimization (e.g., redundancy, compaction)

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. (1 indent ) Translation (e.g., conversion, equivalence)

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. (1 indent ) Testing or evaluating

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.. (2 indent ) Design verification (e.g., wiring line capacitance, fan-out checking, minimum path width)

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... (3 indent ) Timing analysis (e.g., delay time, path delay, latch timing)

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. (1 indent ) Partitioning (e.g., function block, ordering constraint)

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. (1 indent ) Floorplanning

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.. (2 indent ) Detailed placement (i.e., iterative improvement)

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.. (2 indent ) Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance)

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.. (2 indent ) Layout editor (e.g., updating)

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. (1 indent ) Routing (e.g., routing map, netlisting)

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.. (2 indent ) Global routing (e.g., shortest path, dead space, or duplicate trace elimination)

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.. (2 indent ) Detailed routing (e.g., channel routing, switch box routing)

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.. (2 indent ) PCB wiring

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.. (2 indent ) PLA, PLD, FPGA, OR MCM

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. (1 indent ) Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)

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. (1 indent ) Logical circuit synthesizer

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DESIGN OF SEMICONDUCTOR MASK

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. (1 indent ) Mesh generation

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. (1 indent ) Pattern exposure

	FOREIGN ART COLLECTIONS

FOR000

CLASS-RELATED FOREIGN DOCUMENTS

Any foreign patents or non-patent literature from subclasses that have been reclassified have been transferred directly to FOR Collections listed below. These Collections contain ONLY foreign patents or non-patent literature. The parenthetical references in the Collection titles refer to the abolished subclasses from which these Collections were derived.

APPLICATIONS (364/400)

FOR489

. (1 indent ) Circuit design and analysis (364/489)

FOR490

.. (2 indent ) Integrated (364/490)

FOR491

... (3 indent ) Layout (364/491)

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