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 Class   712ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTRUCTION PROCESSING (E.G., PROCESSORS)
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  1           PROCESSING ARCHITECTURE
  2           . (1 indent ) Vector processor
  3           .. (2 indent ) Scalar/vector processor interface
  4           .. (2 indent ) Distributing of vector data to vector registers
  5           ... (3 indent ) Masking to control an access to data in vector register
  6           .. (2 indent ) Controlling access to external vector data
  7           .. (2 indent ) Vector processor operation
  8           ... (3 indent ) Sequential
  9           ... (3 indent ) Concurrent
  10           . (1 indent ) Array processor
  11           .. (2 indent ) Array processor element interconnection
  12           ... (3 indent ) Cube or hypercube
  13           ... (3 indent ) Partitioning
  14           ... (3 indent ) Processing element memory
  15           ... (3 indent ) Reconfiguring
  16           .. (2 indent ) Array processor operation
  17           ... (3 indent ) Application specific
  18           ... (3 indent ) Data flow array processor
  19           ... (3 indent ) Systolic array processor
  20           ... (3 indent ) Multimode (e.g., MIMD to SIMD, etc.)
  21           ... (3 indent ) Multiple instruction, Multiple data (MIMD)
  22           ... (3 indent ) Single instruction, multiple data (SIMD)
  23           . (1 indent ) Superscalar
  24           . (1 indent ) Long instruction word
  25           . (1 indent ) Data driven or demand driven processor
  26           .. (2 indent ) Detection/pairing based on destination, ID tag, or data
  27           .. (2 indent ) Particular data driven memory structure
  28           . (1 indent ) Distributed processing system
  29           .. (2 indent ) Interface
  30           .. (2 indent ) Operation
  31           ... (3 indent ) Master/slave
  32           . (1 indent ) Microprocessor or multichip or multimodule processor having sequential program control
  33           .. (2 indent ) Having multiple internal buses
  34           .. (2 indent ) Including coprocessor
  35           ... (3 indent ) Digital Signal processor
  36           .. (2 indent ) Application specific
  37           .. (2 indent ) Programmable (e.g., EPROM)
  38           .. (2 indent ) Offchip interface
  39           ... (3 indent ) Externally controlled internal mode switching via pin
  40           ... (3 indent ) External sync or interrupt signal
  41           .. (2 indent ) RISC
  42           .. (2 indent ) Operation
  43           ... (3 indent ) Mode switching
  200           ARCHITECTURE BASED INSTRUCTION PROCESSING
  201           . (1 indent ) Data flow based system
  202           . (1 indent ) Stack based computer
  203           . (1 indent ) Multiprocessor instruction
  204           INSTRUCTION ALIGNMENT
  205           INSTRUCTION FETCHING
  206           . (1 indent ) Of multiple instructions simultaneously
  207           . (1 indent ) Prefetching
  208           INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED)
  209           . (1 indent ) Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)
  210           . (1 indent ) Decoding instruction to accommodate variable length instruction or operand
  211           . (1 indent ) Decoding instruction to generate an address of a microroutine
  212           . (1 indent ) Decoding by plural parallel decoders
  213           . (1 indent ) Predecoding of instruction component
  214           INSTRUCTION ISSUING
  215           . (1 indent ) Simultaneous issuance of multiple instructions
  216           DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION
  217           . (1 indent ) Scoreboarding, reservation station, or aliasing
  218           . (1 indent ) Commitment control or register bypass
  219           . (1 indent ) Reducing an impact of a stall or pipeline bubble
  220           PROCESSING CONTROL
  221           . (1 indent ) Arithmetic operation instruction processing
  222           .. (2 indent ) Floating point or vector
  223           . (1 indent ) Logic operation instruction processing
  224           .. (2 indent ) Masking
  225           . (1 indent ) Processing control for data transfer
  226           . (1 indent ) Instruction modification based on condition
  227           . (1 indent ) Specialized instruction processing in support of testing, debugging, emulation
  228           . (1 indent ) Context preserving (e.g., context swapping, checkpointing, register windowing
  229           . (1 indent ) Mode switch or change
  230           . (1 indent ) Generating next microinstruction address
  231           . (1 indent ) Detecting end or completion of microprogram
  232           . (1 indent ) Hardwired controller
  233           . (1 indent ) Branching (e.g., delayed branch, loop control, branch predict, interrupt)
  234           .. (2 indent ) Conditional branching
  235           ... (3 indent ) Simultaneous parallel fetching or executing of both branch and fall-through path
  236           ... (3 indent ) Evaluation of multiple conditions or multiway branching
  237           ... (3 indent ) Prefetching a branch target (i.e., look ahead)
  238           .... (4 indent ) Branch target buffer
  239           ... (3 indent ) Branch prediction
  240           .... (4 indent ) History table
  241           .. (2 indent ) Loop execution
  242           .. (2 indent ) To macro-instruction routine
  243           .. (2 indent ) To microinstruction subroutine
  244           .. (2 indent ) Exeception processing (e.g., interrupts and traps)
  245           . (1 indent ) Processing sequence control (i.e., microsequencing)
  246           .. (2 indent ) Plural microsequencers (e.g., dual microsequencers)
  247           .. (2 indent ) Multilevel microcontroller (e.g., dual-level control store)
  248           .. (2 indent ) Writable/changeable control store architecture
  300           BYTE-WORD REARRANGING, BIT-FIELD INSERTION OR EXTRACTION, STRING LENGTH DETECTING, OR SEQUENCE DETECTING
 
 E-SUBCLASSES
 
 The following subclasses beginning with the letter E are E-subclasses. Each E-subclass corresponds in scope to a classification in a foreign classification system, for example, the European Classification system (ECLA). The foreign classification equivalent to an E-subclass is identified in the subclass definition. In addition to US documents classified in E-subclasses by US examiners, documents are regularly classified in E-subclasses according to the classification practices of any foreign Offices identified in parentheses at the end of the title. For example, "(EPO)" at the end of a title indicates both European and US patent documents, as classified by the EPO, are regularly added to the subclass. E-subclasses may contain subject matter outside the scope of this class.Consult their definitions, or the documents themselves to clarify or interpret titles.
  E9.001           ARRANGEMENTS FOR PROGRAM CONTROL, E.G., CONTROL UNIT (EPO)
  E9.002           . (1 indent ) Using wired connections, e.g., plugboard (EPO)
  E9.003           . (1 indent ) Using stored program, i.e., using internal store of processing (EPO)
  E9.004           .. (2 indent ) Micro-control or micro-program arrangements (EPO)
  E9.005           ... (3 indent ) Execution means for micro-instructions irrespective of the micro-instruction function, e.g., decoding of micro-instructions and nano-instructions; timing of micro instructions; programmable logic arrays; delays and fan-out problems (EPO)
  E9.006           ... (3 indent ) Micro instruction function e.g., input/output micro-instruction; diagnostic micro-instruction; micro-instruction format (EPO)
  E9.007           ... (3 indent ) Loading of the micro-program (EPO)
  E9.008           ... (3 indent ) Enhancement of operational speed, e.g., by using several micro-control devices operating in parallel (EPO)
  E9.009           ... (3 indent ) Address formation of the next micro-instruction (EPO)
  E9.01           .... (4 indent ) Micro-instruction address formation(EPO)
  E9.011           .... (4 indent ) Arrangements for next micro-instruction selection (EPO)
  E9.012           .... (5 indent ) Micro-instruction selection based on results of processing (EPO)
  E9.013           ..... (6 indent ) By address selection on input of storage (EPO)
  E9.014           ..... (6 indent ) By instruction selection on output of storage (EPO)
  E9.015           .... (5 indent ) Micro-instruction selection not based on processing results, e.g., interrupt, patch, first cycle store, diagnostic programs (EPO)
  E9.016           .. (2 indent ) Arrangements for executing machine-instructions, e.g., instruction decode (EPO)
  E9.017           ... (3 indent ) Controlling the executing of arithmetic operations (EPO)
  E9.018           ... (3 indent ) Controlling the executing of logical operations (EPO)
  E9.019           ... (3 indent ) Controlling single bit operations (EPO)
  E9.02           ... (3 indent ) For comparing (EPO)
  E9.021           ... (3 indent ) For format conversion (EPO)
  E9.022           ... (3 indent ) Using storage based on relative movement between record carrier and transducer (EPO)
  E9.023           ... (3 indent ) Register arrangements, e.g., register files, special registers (EPO)
  E9.024           .... (4 indent ) Special purpose registers, e.g., segment register, profile register (EPO)
  E9.025           .... (4 indent ) Register structure, e.g., multigauged registers (EPO)
  E9.026           .... (5 indent ) Implementation provisions thereof, e.g., ports, bypass paths (EPO)
  E9.027           .... (5 indent ) Organization of register space, e.g., distributed register files, register banks (EPO)
  E9.028           ... (3 indent ) Instruction analysis, e.g., decoding, instruction word fields (EPO)
  E9.029           .... (4 indent ) Variable length instructions or constant length instructions whereby the relative length of operation and operand part is variable (EPO)
  E9.03           .... (4 indent ) Decoding the operand specifier, e.g., specifier format (EPO)Speech classification or search (EPO)
  E9.031           .... (4 indent ) With implied specifier, e.g., top of stack (EPO)
  E9.032           ... (3 indent ) For specific instructions not covered by the preceding groups, e.g., halt, synchronize (EPO)
  E9.033           ... (3 indent ) Controlling loading, storing, or clearing operations (EPO)
  E9.034           ... (3 indent ) Controlling moving, shifting, or rotation operations (EPO)
  E9.035           ... (3 indent ) With operation extension or modification (EPO)
  E9.036           .... (4 indent ) Using data descriptors, e.g., dynamic data typing (EPO)
  E9.037           .... (4 indent ) Using run time instruction translation (EPO)
  E9.038           ... (3 indent ) Addressing or accessing the instruction operand or the result (EPO)
  E9.039           .... (4 indent ) Of multiple operands or results(EPO)
  E9.04           .... (4 indent ) Indirect addressing (EPO)
  E9.041           .... (4 indent ) Indexed addressing (EPO)
  E9.042           .... (5 indent ) Using index register, e.g., adding index to base address (EPO)
  E9.043           ..... (6 indent ) Using wraparound, e.g., modulo or circular addressing (EPO)
  E9.044           ..... (6 indent ) Using scaling, e.g., multiplication of index (EPO)
  E9.045           ... (3 indent ) Concurrent instruction execution, e.g., pipeline, look ahead (EPO)
  E9.046           .... (4 indent ) Data or operand accessing, e.g., operand prefetch, operand bypass (EPO)
  E9.047           .... (5 indent ) Operand prefetch, e.g., prefetch instruction, address prediction (EPO)
  E9.048           .... (5 indent ) Maintaining memory consistency (EPO)
  E9.049           .... (4 indent ) Instruction issuing, e.g., dynamic instruction scheduling, out of order instruction execution (EPO)
  E9.05           .... (5 indent ) Speculative instruction execution, e.g., conditional execution, procedural dependencies, instruction invalidation (EPO)
  E9.051           ..... (6 indent ) Using dynamic prediction, e.g., branch history table (EPO)
  E9.052           ..... (6 indent ) Using static prediction, e.g., branch taken strategy (EPO)
  E9.053           .... (5 indent ) From multiple instruction streams, e.g., multistreaming (EPO)
  E9.054           .... (5 indent ) Of compound instructions (EPO)
  E9.055           .... (4 indent ) Instruction prefetch, e.g., instruction buffer (EPO)
  E9.056           .... (5 indent ) For branches, e.g., hedging branch folding (EPO)
  E9.057           ..... (6 indent ) Using address buffers, e.g., return stack (EPO)
  E9.058           .... (5 indent ) For loops, e.g., loop buffer (EPO)
  E9.059           .... (5 indent ) With instruction modification, e.g. store into instruction stream (EPO)
  E9.06           .... (4 indent ) Recovery, e.g., branch miss-prediction, exception handling (EPO)
  E9.061           .... (5 indent ) Using multiple copies of the architectural state, e.g., shadow registers (EPO)
  E9.062           .... (4 indent ) Using instruction pipelines (EPO)
  E9.063           .... (5 indent ) Synchronization, e.g., clock skew (EPO)
  E9.064           .... (5 indent ) Technology-related problems thereof, e.g., GaAs pipelines (EPO)
  E9.065           .... (5 indent ) Pipelining a single stage, e.g., superpipelining (EPO)
  E9.066           .... (4 indent ) Using a slave processor, e.g., coprocessor (EPO)
  E9.067           .... (5 indent ) Which is not visible to the instruction set architecture, e.g., using memory mapping, illegal opcodes (EPO)
  E9.068           ..... (6 indent ) For non-native instruction set architecture (EPO)
  E9.069           .... (5 indent ) Which is visible to the instruction set architecture (EPO)
  E9.07           ..... (6 indent ) Having access to instruction memory (EPO)
  E9.071           .... (4 indent ) Using a plurality of independent parallel functional units (EPO)
  E9.072           .... (5 indent ) Decoding (EPO)
  E9.073           ... (3 indent ) Address formation of the next instruction, e.g., incrementing the instruction counter, jump (EPO)
  E9.074           .... (4 indent ) Program or instruction counter, e.g., incrementing (EPO)
  E9.075           .... (4 indent ) Branch or jump to non-sequential address (EPO)
  E9.076           .... (5 indent ) Unconditional, e.g., indirect jump (EPO)
  E9.077           .... (5 indent ) Conditional (EPO)
  E9.078           .... (5 indent ) For cyclically repeating instructions, e.g., iterative operation, loop counter (EPO)
  E9.079           .... (4 indent ) Condition code generation, e.g., status register (EPO)
  E9.08           .... (4 indent ) Selective instruction skip or conditional execution, e.g., dummy cycle (EPO)
  E9.081           .... (4 indent ) Sequential commutation, e.g., ring counter, cyclical pulse distribution (EPO)
  E9.082           .. (2 indent ) Arrangements for executing sub-programs, i.e., combinations of several instructions (EPO)
  E9.083           ... (3 indent ) Formation of sub-program jump address or of return address (EPO)
  E9.084           .... (4 indent ) Object Oriented Method Invocation (EPO)
  E9.085           .... (5 indent ) Optimizing for Receiver Type (EPO)
  E9.086           . (1 indent ) Using record carriers containing only program instructions (EPO)
 
 FOREIGN ART COLLECTIONS
 
  FOR000           CLASS-RELATED FOREIGN DOCUMENTS


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