Class   711	ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MEMORY
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ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION OR SYSTEM

2

. (1 indent ) Addressing extended or expanded memory

3

. (1 indent ) Addressing cache memories

4

. (1 indent ) Dynamic-type storage device (e.g., disk, tape, drum)

5

. (1 indent ) For multiple memory modules (e.g., banks, interleaved memory)

6

. (1 indent ) Virtual machine memory addressing

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STORAGE ACCESSING AND CONTROL

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. (1 indent ) Specific memory composition

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.. (2 indent ) Solid-state read only memory (ROM)

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... (3 indent ) Programmable read only memory (PROM, EEPROM, etc.)

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.. (2 indent ) Solid-state random access memory (RAM)

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... (3 indent ) Dynamic random access memory

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.... (4 indent ) Refresh scheduling

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.. (2 indent ) Ferrite core

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.. (2 indent ) Content addressable memory (CAM)

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.. (2 indent ) Shift register memory

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... (3 indent ) Circulating memory

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.. (2 indent ) Accessing dynamic storage device

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... (3 indent ) Direct access storage device (DASD)

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.... (4 indent ) Caching

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.... (4 indent ) Arrayed (e.g., RAIDs)

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.. (2 indent ) Detachable memory

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.. (2 indent ) Bubble memory

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. (1 indent ) Hierarchical memories

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.. (2 indent ) Caching

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... (3 indent ) Multiple caches

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.... (4 indent ) Parallel caches

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.... (4 indent ) Private caches

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.... (4 indent ) Hierarchical caches

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.... (4 indent ) User data cache and instruction data cache

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.... (4 indent ) Cross-interrogating

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... (3 indent ) Instruction data cache

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... (3 indent ) User data cache

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... (3 indent ) Interleaved

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... (3 indent ) Associative

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... (3 indent ) Partitioned cache

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... (3 indent ) Shared cache

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... (3 indent ) Multiport cache

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... (3 indent ) Stack cache

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... (3 indent ) Entry replacement strategy

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.... (4 indent ) Combined replacement modes

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.... (4 indent ) Cache flushing

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.... (4 indent ) Least recently used

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... (3 indent ) Look-ahead

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... (3 indent ) Cache bypassing

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.... (4 indent ) No-cache flags

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... (3 indent ) Cache pipelining

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... (3 indent ) Coherency

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.... (4 indent ) Write-through

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.... (4 indent ) Write-back

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.... (4 indent ) Cache status data bit

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.... (4 indent ) Access control bit

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.... (4 indent ) Snooping

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. (1 indent ) Shared memory area

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.. (2 indent ) Plural shared memories

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.. (2 indent ) Multiport memory

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.. (2 indent ) Simultaneous access regulation

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.. (2 indent ) Prioritized access regulation

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.. (2 indent ) Memory access blocking

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.. (2 indent ) Shared memory partitioning

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. (1 indent ) Control technique

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.. (2 indent ) Read-modify-write (RMW)

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.. (2 indent ) Status storage

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.. (2 indent ) Interleaving

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.. (2 indent ) Prioritizing

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.. (2 indent ) Entry replacement strategy

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... (3 indent ) Least recently used (LRU)

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.. (2 indent ) Archiving

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... (3 indent ) Backup

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.. (2 indent ) Access limiting

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... (3 indent ) With password or key

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.. (2 indent ) Internal relocation

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.. (2 indent ) Resetting

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. (1 indent ) Access timing

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.. (2 indent ) Concurrent accessing

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.. (2 indent ) Memory access pipelining

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. (1 indent ) Memory configuring

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.. (2 indent ) Based on data size

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.. (2 indent ) Based on component size

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.. (2 indent ) Memory partitioning

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ADDRESS FORMATION

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. (1 indent ) Slip control, misaligning, boundary alignment

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. (1 indent ) Address mapping (e.g., conversion, translation)

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.. (2 indent ) Virtual addressing

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... (3 indent ) Predicting, look-ahead

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.... (4 indent ) Directories and tables (e.g., DLAT, TLB)

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... (3 indent ) Translation tables (e.g., segment and page table or map)

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.... (4 indent ) Directory tables (e.g., DLAT, TLB)

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.... (4 indent ) Segment or page table descriptor

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... (3 indent ) Including plural logical address spaces, pages, segments, blocks

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.. (2 indent ) Resolving conflict, coherency, or synonym problem

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. (1 indent ) Address multiplexing or address bus manipulation

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. (1 indent ) Varying address bit-length or size

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. (1 indent ) Generating prefetch, look-ahead, jump, or predictive address

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. (1 indent ) Operand address generation

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. (1 indent ) In response to microinstruction

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. (1 indent ) Hashing

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. (1 indent ) Generating a particular pattern/sequence of addresses

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.. (2 indent ) Sequential addresses generation

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. (1 indent ) Incrementing, decrementing, or shifting circuitry

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. (1 indent ) Combining two or more values to create address

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. (1 indent ) Using table

	E-SUBCLASSES

The following subclasses beginning with the letter E are E-subclasses. Each E-subclass corresponds in scope to a classification in a foreign classification system, for example, the European Classification system (ECLA). The foreign classification equivalent to an E-subclass is identified in the subclass definition. In addition to US documents classified in E-subclasses by US examiners, documents are regularly classified in E-subclasses according to the classification practices of any foreign Offices identified in parentheses at the end of the title. For example, "(EPO)" at the end of a title indicates both European and US patent documents, as classified by the EPO, are regularly added to the subclass. E-subclasses may contain subject matter outside the scope of this class.Consult their definitions, or the documents themselves to clarify or interpret titles.

E12.001

ACCESSING, ADDRESSING OR ALLOCATING WITHIN MEMORY SYSTEMS OR ARCHITECTURES (EPO)

E12.002

. (1 indent ) Addressing or allocation; relocation (EPO)

E12.003

.. (2 indent ) With multidimensional access, e.g., row/column, matrix, etc. (EPO)

E12.004

.. (2 indent ) With look-ahead addressing means (EPO)

E12.005

.. (2 indent ) User address space allocation, e.g., contiguous or noncontiguous base addressing, etc. (EPO)

E12.006

... (3 indent ) Free address space management (EPO)

E12.007

.... (4 indent ) In block-addressed memory (EPO)

E12.008

....• (5 indent ) In block-erasable memory, e.g., flash memory, etc. (EPO)

E12.009

.... (4 indent ) Garbage collection, i.e., reclamation of unreferenced memory (EPO)

E12.01

....• (5 indent ) Using reference counting (EPO)

E12.011

....• (5 indent ) Incremental or concurrent garbage collection, e.g., in real-time systems, etc. (EPO)

E12.012

....•. (6 indent ) Generational garbage collection (EPO)

E12.013

... (3 indent ) Multiple users address space allocation, e.g., using different base addresses, etc. (EPO)

E12.014

... (3 indent ) Using tables or multilevel address translation means (EPO)

E12.015

.. (2 indent ) Addressing variable-length words or parts of words (EPO)

E12.016

.. (2 indent ) In hierarchically structured memory systems, e.g., virtual memory systems, etc. (EPO)

E12.017

... (3 indent ) Addressing of memory level in which access to desired data or data block requires associative addressing means, e.g., cache, etc. (EPO)

E12.018

.... (4 indent ) Using pseudo-associative means, e.g., set-associative, hashing, etc. (EPO)

E12.019

.... (4 indent ) For peripheral storage systems, e.g., disc cache, etc. (EPO)

E12.02

.... (4 indent ) With dedicated cache, e.g., instruction or stack, etc. (EPO)

E12.021

.... (4 indent ) Using selective caching, e.g., bypass, partial write, etc. (EPO)

E12.022

.... (4 indent ) Using clearing, invalidating, or resetting means (EPO)

E12.023

.... (4 indent ) Multi-user, multiprocessor, multiprocessing cache systems (EPO)

E12.024

....• (5 indent ) With multilevel cache hierarchies (EPO)

E12.025

....• (5 indent ) With a network or matrix configuration (EPO)

E12.026

....• (5 indent ) Cache consistency protocols (EPO)

E12.027

....•. (6 indent ) Using directory methods (EPO)

E12.028

....•.. (7 indent ) Copy directories (EPO)

E12.029

....•.. (7 indent ) Associative directories (EPO)

E12.03

....•.. (7 indent ) Distributed directories, e.g., linked lists of caches, etc. (EPO)

E12.031

....•.. (7 indent ) Limited pointers directories; state-only directories without pointers (EPO)

E12.032

....•.. (7 indent ) With concurrent directory accessing, i.e., handling multiple concurrent coherency transactions (EPO)

E12.033

....•. (6 indent ) Using a bus scheme, e.g., with bus monitoring or watching means, etc. (EPO)

E12.034

....•.. (7 indent ) In combination with broadcast means, e.g., for invalidation or updating, etc. (EPO)

E12.035

....•.. (7 indent ) For main memory peripheral accesses, e.g., I/O or DMA, etc. (EPO)

E12.036

....•. (6 indent ) With software control, e.g., non-cacheable data, etc. (EPO)

E12.037

....• (5 indent ) With cache invalidating means (EPO)

E12.038

....• (5 indent ) With shared cache (EPO)

E12.039

....• (5 indent ) For multiprocessing or multitasking (EPO)

E12.04

.... (4 indent ) With main memory updating (EPO)

E12.041

.... (4 indent ) Organization and technology of caches (EPO)

E12.042

....• (5 indent ) Of parts of caches, e.g., directory or tag array, etc. (EPO)

E12.043

....• (5 indent ) With plurality of cache hierarchy levels (EPO)

E12.044

.... (4 indent ) Multiple simultaneous or quasi-simultaneous cache accessing (EPO)

E12.045

....• (5 indent ) Cache with multiple tag or data arrays being simultaneously accessible (EPO)

E12.046

....•. (6 indent ) Partitioned cache, e.g., separate instruction and operand caches, etc. (EPO)

E12.047

....•. (6 indent ) Cache with interleaved addressing (EPO)

E12.048

....• (5 indent ) Cache with multi-port tag or data arrays (EPO)

E12.049

....• (5 indent ) Overlapped cache accessing, e.g., pipeline, etc. (EPO)

E12.05

....•. (6 indent ) By multiple requestors (EPO)

E12.051

....•. (6 indent ) With reload from main memory (EPO)

E12.052

.... (4 indent ) Cache access modes (EPO)

E12.053

....• (5 indent ) Burst mode (EPO)

E12.054

....• (5 indent ) Page mode (EPO)

E12.055

....• (5 indent ) Parallel mode, e.g., in parallel with main memory or CPU, etc. (EPO)

E12.056

....• (5 indent ) Variable-length word access (EPO)

E12.057

.... (4 indent ) With pre-fetch (EPO)

E12.058

... (3 indent ) Address translation (EPO)

E12.059

.... (4 indent ) Using page tables, e.g., page table structures, etc. (EPO)

E12.06

....• (5 indent ) Involving hashing techniques, e.g., inverted page tables, etc. (EPO)

E12.061

.... (4 indent ) Using associative or pseudo-associative address translation means, e.g., translation look-aside buffer (TLB), address translation buffer (ATB), address cache, etc. (EPO)

E12.062

....• (5 indent ) Associated with data cache (EPO)

E12.063

....•. (6 indent ) Data cache being concurrently physically addressed (EPO)

E12.064

....•. (6 indent ) Data cache being concurrently virtually addressed (EPO)

E12.065

....• (5 indent ) For multiple virtual address spaces, e.g., segmentation, etc. (EPO)

E12.066

.... (4 indent ) Decentralized address translation, e.g., in distributed shared memory systems, etc. (EPO)

E12.067

.... (4 indent ) For peripheral accesses to main memory, e.g., DMA, etc. (EPO)

E12.068

.... (4 indent ) For multiple virtual address spaces, e.g., segmentation, etc. (EPO)

E12.069

... (3 indent ) Replacement control (EPO)

E12.07

.... (4 indent ) Using a replacement algorithm (EPO)

E12.071

....• (5 indent ) Of the least frequently used type, e.g., with individual count value, etc. (EPO)

E12.072

....• (5 indent ) With age list, e.g., queue, MRU-LRU list, etc. (EPO)

E12.073

....•. (6 indent ) Being minimized, e.g., nonMRU, etc. (EPO)

E12.074

....•. (6 indent ) Being generated by decoding array or storage (EPO)

E12.075

....• (5 indent ) With special data handling, e.g., priority of data or instructions, pinning, errors, etc. (EPO)

E12.076

....•. (6 indent ) Using additional replacement algorithm (EPO)

E12.077

....• (5 indent ) Adapted to multidimensional cache systems, e.g., set-associative, multi-cache, multi-set, or multilevel, etc. (EPO)

E12.078

.. (2 indent ) Addressing physical block of locations, e.g., base addressing, module addressing, memory dedication, etc. (EPO)

E12.079

... (3 indent ) Interleaved addressing (EPO)

E12.08

... (3 indent ) Address space extension (EPO)

E12.081

.... (4 indent ) For memory modules (EPO)

E12.082

.... (4 indent ) For I/O modules, e.g., memory mapped I/O, etc. (EPO)

E12.083

... (3 indent ) Combination of memories, e.g., ROM and RAM, etc., to permit replacement or supplementing of words in one module by words in another module (EPO)

E12.084

... (3 indent ) Configuration or reconfiguration (EPO)

E12.085

.... (4 indent ) With centralized address assignment (EPO)

E12.086

....• (5 indent ) And decentralized selection (EPO)

E12.087

.... (4 indent ) With decentralized address assignment (EPO)

E12.088

....• (5 indent ) Address being position dependent (EPO)

E12.089

.... (4 indent ) With feedback, e.g., presence or absence of unit detected by addressing, overflow detection, etc. (EPO)

E12.09

.... (4 indent ) Multi-configuration, e.g., local and global addressing, etc. (EPO)

E12.091

. (1 indent ) Protection against unauthorized use of memory (EPO)

E12.092

.. (2 indent ) By using cryptography (EPO)

E12.093

.. (2 indent ) By checking subject access rights (EPO)

E12.094

... (3 indent ) Key-lock mechanism (EPO)

E12.095

.... (4 indent ) In virtual system, e.g., with translation means, etc. (EPO)

E12.096

... (3 indent ) Using access table, e.g., matrix or list, etc. (EPO)

E12.097

... (3 indent ) In hierarchical protection system, e.g., privilege levels, memory rings, etc. (EPO)

E12.098

.. (2 indent ) By checking object accessibility, e.g., type of access defined by the memory independently of subject rights, etc. (EPO)

E12.099

... (3 indent ) Protection being physical, e.g., cell, word, block, etc. (EPO)

E12.1

.... (4 indent ) For module or part of module (EPO)

E12.101

.... (4 indent ) For range (EPO)

E12.102

... (3 indent ) Protection being virtual, e.g., for virtual blocks or segments before translation mechanism, etc. (EPO)

E12.103

. (1 indent ) Protection against loss of memory contents (EPO)

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FOR000

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