Class   710	ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT
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INPUT/OUTPUT DATA PROCESSING

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. (1 indent ) Input/Output expansion

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. (1 indent ) Input/Output addressing

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.. (2 indent ) Address data transfer

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. (1 indent ) Input/Output command process

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.. (2 indent ) Operation scheduling

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.. (2 indent ) Concurrently performing Input/Output operation and other operation unrelated to Input/Output

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. (1 indent ) Peripheral configuration

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.. (2 indent ) Address assignment

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.. (2 indent ) Configuration initialization

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.. (2 indent ) Protocol selection

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.. (2 indent ) As input or output

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.. (2 indent ) By detachable memory

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.. (2 indent ) Mode selection

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. (1 indent ) Peripheral monitoring

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.. (2 indent ) Characteristic discrimination

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.. (2 indent ) Availability monitoring

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.. (2 indent ) Activity monitoring

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.. (2 indent ) Status updating

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. (1 indent ) Concurrent Input/Output processing and data transfer

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.. (2 indent ) Concurrent data transferring

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. (1 indent ) Direct Memory Accessing (DMA)

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.. (2 indent ) Programmed control memory accessing

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.. (2 indent ) By command chaining

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.. (2 indent ) Timing

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.. (2 indent ) Using addressing

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.. (2 indent ) Via separate bus

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.. (2 indent ) With access regulating

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. (1 indent ) Flow controlling

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. (1 indent ) Frame forming

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. (1 indent ) Transfer direction selection

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. (1 indent ) Transfer termination

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. (1 indent ) Data transfer specifying

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.. (2 indent ) Transferred data counting

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.. (2 indent ) Burst data transfer

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. (1 indent ) Input/Output access regulation

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.. (2 indent ) Access dedication

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.. (2 indent ) Path selection

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.. (2 indent ) Access request queuing

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.. (2 indent ) Access prioritization

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... (3 indent ) Dynamic

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... (3 indent ) Group

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... (3 indent ) Physical position

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... (3 indent ) Prioritized polling

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... (3 indent ) Time-slot accessing

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.. (2 indent ) Input/Output polling

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... (3 indent ) Polled interrupt

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.. (2 indent ) Input/Output interrupting

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... (3 indent ) Masking

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... (3 indent ) Vectored

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.. (2 indent ) Accessing via a multiplexer

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. (1 indent ) Input/Output data buffering

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.. (2 indent ) Alternately filling or emptying buffers

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.. (2 indent ) Queue content modification

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.. (2 indent ) Contents validation

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.. (2 indent ) Buffer space allocation or deallocation

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.. (2 indent ) Fullness indication

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. (1 indent ) Input/Output process timing

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.. (2 indent ) Processing suspension

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.. (2 indent ) Transfer rate regulation

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.. (2 indent ) Synchronous data transfer

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. (1 indent ) Peripheral adapting

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.. (2 indent ) Universal

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.. (2 indent ) Via common units and peripheral-specific units

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.. (2 indent ) Input/Output data modification

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... (3 indent ) Width conversion

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... (3 indent ) Keystroke interpretation

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... (3 indent ) Data compression and expansion

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... (3 indent ) Analog-to-digital or digital-to-analog

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... (3 indent ) Digital-to-digital

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... (3 indent ) Serial-to-parallel or parallel-to-serial

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.. (2 indent ) Application-specific peripheral adapting

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... (3 indent ) For user input device

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... (3 indent ) For data storage device

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INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)

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. (1 indent ) Bus expansion or extension

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.. (2 indent ) Card insertion

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... (3 indent ) Hot insertion

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.. (2 indent ) Docking station

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... (3 indent ) Hot docking

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. (1 indent ) System configuring

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. (1 indent ) Protocol

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.. (2 indent ) Using transmitter and receiver

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. (1 indent ) Bus access regulation

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.. (2 indent ) Bus locking

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.. (2 indent ) Bus polling

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.. (2 indent ) Bus master/slave controlling

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.. (2 indent ) Rotational prioritizing (i.e., round robin)

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.. (2 indent ) Bus request queuing

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.. (2 indent ) Centralized bus arbitration

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... (3 indent ) Static bus prioritization

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.... (4 indent ) Physical position bus prioritization

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... (3 indent ) Dynamic bus prioritization

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... (3 indent ) Time-slotted bus accessing

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... (3 indent ) Delay reduction

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.. (2 indent ) Decentralized bus arbitration

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... (3 indent ) Hierarchical or multilevel accessing

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... (3 indent ) Static bus prioritization

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.... (4 indent ) Physical position bus prioritization

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... (3 indent ) Dynamic bus prioritization

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... (3 indent ) Time-slotted bus accessing

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... (3 indent ) Delay reduction

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. (1 indent ) Bus interface architecture

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.. (2 indent ) Bus bridge

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... (3 indent ) Variable or multiple bus width

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... (3 indent ) Direct memory access (e.g., DMA)

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... (3 indent ) Arbitration

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... (3 indent ) Buffer or que control

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... (3 indent ) Intelligent bridge

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... (3 indent ) Multiple bridges

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... (3 indent ) Peripheral bus coupling (e.g., PCI, USB, ISA, and etc.)

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... (3 indent ) Common protocol (e.g., PCI to PCI)

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... (3 indent ) Different protocol (e.g., PCI to ISA)

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.. (2 indent ) Path selecting switch

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... (3 indent ) Crossbar

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ACCESS LOCKING

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ACCESS POLLING

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ACCESS ARBITRATING

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. (1 indent ) Centralized arbitrating

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. (1 indent ) Decentralized arbitrating

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. (1 indent ) Hierarchical or multilevel arbitrating

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. (1 indent ) Access prioritizing

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INTERRUPT PROCESSING

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. (1 indent ) Multimode interrupt processing

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. (1 indent ) Interrupt inhibiting or masking

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. (1 indent ) Interrupt queuing

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. (1 indent ) Interrupt prioritizing

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.. (2 indent ) Variable

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. (1 indent ) Programmable interrupt processing

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. (1 indent ) Processor status

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. (1 indent ) Source or destination identifier

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. (1 indent ) Handling vector

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