CLASS 710, ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS: INPUT/OUTPUT |
1 | INPUT/OUTPUT DATA PROCESSING: |
This subclass is indented under the class definition. Subject matter comprising means or steps for transferring
data from one or more peripherals to one or more computers or digital
data processing systems for the latter to process, store, or further
transfer or for transferring data from the computers or digital
data processing systems to the peripherals.
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2 | . Input/Output expansion: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for increasing the number of the peripherals that can be coupled to the digital data processing system or computer. | |
3 | . Input/Output addressing: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for employing
an identifier for the peripheral, digital data processing system
or computer in order to transfer data therebetween.
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4 | .. Address data transfer: |
This subclass is indented under subclass 3. Subject matter further comprising means or steps for transferring address data between the peripheral and digital data processing system or computer to ensure that associated user data are transferred to the intended peripheral and digital data processing system or computer. | |
5 | . Input/Output command processing: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for fetching,
buffering, decoding, or executing instruction data in order to transfer
user data between the peripheral and digital data processing system
or computer.
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6 | .. Operation scheduling: |
This subclass is indented under subclass 5. Subject matter further comprising means or steps for specifying the order in which the peripheral and digital data processing system or computer perform a function in order to transfer the user data between a peripheral and digital data processing system or computer. | |
7 | .. Concurrently performing Input/Output operation and other operation unrelated to Input/Output: |
This subclass is indented under subclass 5. Subject matter further comprising means or steps for performing a non-Input/Output function while also transferring data between the peripheral and digital data processing system or computer. | |
8 | . Peripheral configuration: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for assigning
operating characteristics to a peripheral.
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9 | .. Address assignment: |
This subclass is indented under subclass 8. Subject matter further comprising means or steps for giving
an identifier (i.e., address data) to the peripheral.
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10 | .. Configuration initialization: |
This subclass is indented under subclass 8. Subject matter further comprising means or steps for automatically assigning an operating characteristic when the peripheral, digital data processing system, or computer is started or reset. | |
11 | .. Protocol selection: |
This subclass is indented under subclass 8. Subject matter further comprising means or steps for choosing a data communications protocol to be employed in order to transfer data between the peripheral and digital data processing system or computer. | |
12 | .. As input or output: |
This subclass is indented under subclass 8. Subject matter further comprising means or steps for assigning a port or adapter, which is associated with the peripheral, to permit either transferring data from the peripheral to the digital data processing system or computer or from the digital data processing system or computer to the peripheral. | |
13 | .. By detachable memory: |
This subclass is indented under subclass 8. Subject matter further comprising means or steps for assigning the operating characteristics based on data stored in a removable memory. | |
14 | .. Mode selection: |
This subclass is indented under subclass 8. Subject matter further comprising means or steps for choosing a method of operating for the peripheral. | |
15 | . Peripheral monitoring: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for enabling
a digital data processing system or computer to detect or observe
an operating characteristic or condition of the peripheral.
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16 | .. Characteristic discrimination: |
This subclass is indented under subclass 15. Subject matter further comprising means or steps for detecting the connection, type, or configuration of the peripheral. | |
17 | .. Availability monitoring: |
This subclass is indented under subclass 15. Subject matter further comprising means or steps for detecting whether the peripheral is available to participate in transferring data with the digital data processing system or computer. | |
18 | .. Activity monitoring: |
This subclass is indented under subclass 15. Subject matter further comprising means or steps for detecting the amount or type of usage of the peripheral over a period of time. | |
19 | .. Status updating: |
This subclass is indented under subclass 15. Subject matter further comprising means or steps for detecting or reporting change in the condition of a peripheral. | |
20 | . Concurrent Input/Output processing and data transfer: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for performing
an additional I/O-related function while also
exchanging data between a peripheral and computer.
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21 | .. Concurrent data transferring: |
This subclass is indented under subclass 20. Subject matter further comprising means or steps for transferring plural groups of data between a peripheral and digital data processing system or computer at the same time. | |
22 | . Direct Memory Accessing (DMA): |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for transferring
data between a peripheral and memory of a digital data processing
system or computer with minimal or no intervention from a main processor
of the digital data processing system or computer.
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23 | .. Programmed control memory accessing: |
This subclass is indented under subclass 22. Subject matter further comprising means or steps for transferring data directly between a peripheral and memory and also for transferring data between a peripheral and the memory under control of the central or main processor(s), although not necessarily at the same time. | |
24 | .. By command chaining: |
This subclass is indented under subclass 22. Subject matter further comprising means or steps for linking individual instruction data and then executing the linked instruction data to transfer data directly between a peripheral and memory. | |
25 | .. Timing: |
This subclass is indented under subclass 22. Subject matter further comprising means or steps for determining
when to transfer data directly between a peripheral and memory.
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26 | .. Using addressing: |
This subclass is indented under subclass 22. Subject matter further comprising details of generating
or employing address data to transfer data directly between a peripheral
and the memory of the digital data processing system or computer.
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27 | .. Via separate bus: |
This subclass is indented under subclass 22. Subject matter wherein plural buses permit a processor to access memories concurrently with direct memory accesses. | |
28 | .. With access regulating: |
This subclass is indented under subclass 22. Subject matter further comprising means or steps for directing
which of the peripherals may transfer data directly with the memories.
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29 | . Flow controlling: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for controlling
a first rate at which a peripheral or the digital data processing
system and computer transmit data such that the first rate does
not exceed a second rate at which the computer or digital data processing
system and peripheral can receive data.
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30 | . Frame forming: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for arranging
data into a specified format in order to transfer the arranged data
between a peripheral and a digital data processing system or a computer.
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31 | . Transfer direction selection: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for specifying whether data are to be transmitted from the peripheral to the digital data processing system or computer or from the digital data processing system or computer to the peripheral. | |
32 | . Transfer termination: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for ceasing to exchange data between the peripheral and digital data processing system or computer. | |
33 | . Data transfer specifying: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for defining
a characteristic of a desired transfer of data between the peripheral
and digital data processing system or computer (e.g., amount
of the data to be transferred, location of the data to
be transferred).
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34 | .. Transferred data counting: |
This subclass is indented under subclass 33. Subject matter wherein the amount of the data to be transferred
is defined and the amount of data subsequently transferred is computed.
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35 | .. Burst data transfer: |
This subclass is indented under subclass 33. Subject matter wherein the characteristic is specified as to enable a plurality of data to be transferred in a single transmission. | |
36 | . Input/Output access regulation: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for controlling
which of the peripherals may transfer data with which of the digital
data processing systems or computers.
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37 | .. Access dedication: |
This subclass is indented under subclass 36. Subject matter further comprising means or steps for permitting certain of the peripherals to exchange data with only certain of the digital data processing system or computers. | |
38 | .. Path selection: |
This subclass is indented under subclass 36. Subject matter further comprising means or steps for choosing
a route via which the peripheral and digital data processing system
or computer will transfer data.
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39 | .. Access request queuing: |
This subclass is indented under subclass 36. Subject matter further comprising means or steps for storing a request to transfer data from the peripheral, or digital data processing systems or computer so that the request may be serviced later. | |
40 | .. Access prioritization: |
This subclass is indented under subclass 36. Subject matter further comprising means or steps for preferring certain of the peripherals, or digital data processing systems or computers over others in servicing requests therefrom to transfer data. | |
41 | ... Dynamic: |
This subclass is indented under subclass 40. Subject matter further comprising means or steps for changing preferences given to the peripherals, or digital data processing systems or computers. | |
42 | ... Group: |
This subclass is indented under subclass 40. Subject matter further comprising means or steps wherein the preference is based on a class to which the peripherals, or digital data processing systems or computers belong, or on functions the peripherals, or digital data processing system or computers perform. | |
43 | ... Physical position: |
This subclass is indented under subclass 40. Subject matter wherein the preference is based on the location of the peripherals, or digital data processing system or computers relative to each other. | |
44 | ... Prioritized polling: |
This subclass is indented under subclass 40. Subject matter further comprising means or steps for interrogating
the peripherals to determine readiness thereof to transfer data.
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45 | ... Time-slot accessing: |
This subclass is indented under subclass 40. Subject matter further comprising means or steps for cyclically permitting the peripherals, or digital data processing system, or computers to transfer data for fixed periods of time. | |
46 | .. Input/Output polling: |
This subclass is indented under subclass 36. Subject matter further comprising means or steps for interrogating
the peripherals to determine readiness thereof to transfer data.
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47 | ... Polled interrupt: |
This subclass is indented under subclass 46. Subject matter further comprising means or steps for enabling the computers or digital data processing systems to recognize and respond to interrupt signals from the peripherals by interrogating the peripherals. | |
48 | .. Input/Output interrupting: |
This subclass is indented under subclass 36. Subject matter further comprising means or steps for servicing
requests for access from the peripheral by suspending processing
being performed by the digital data processing system or computer
and then granting access to the requesting peripheral.
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49 | ... Masking: |
This subclass is indented under subclass 48. Subject matter further comprising means or steps for inhibiting
the servicing of the access requests.
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50 | ... Vectored: |
This subclass is indented under subclass 48. Subject matter further comprising means or steps wherein
the interrupting peripherals supply, along with the access
requests, data identifying locations of routines for servicing
the access requests.
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51 | .. Accessing via a multiplexer: |
This subclass is indented under subclass 36. Subject matter further comprising means or steps for employing a concentrator to regulate the access of a plurality of the peripherals, or digital data processing systems or computers. | |
52 | . Input/Output data buffering: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for temporarily
storing data being transferred between the peripheral, and
digital data processing systems or computer.
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53 | .. Alternately filling or emptying buffers: |
This subclass is indented under subclass 52. Subject matter further comprising means or steps for temporarily
storing the data in plural memories wherein data are stored to and retrieved
from at least one of the memories while other data are retrieved
from or stored to at least one of the other memories.
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54 | .. Queue content modification: |
This subclass is indented under subclass 52. Subject matter further comprising means or steps wherein the data are temporarily stored in a memory and the order in which the data are to be retrieved from the memory is altered. | |
55 | .. Contents validation: |
This subclass is indented under subclass 52. Subject matter further comprising means or steps for employing memories to temporarily store the data and for designating whether the memories currently contain data to be transferred therefrom. | |
56 | .. Buffer space allocation or deallocation: |
This subclass is indented under subclass 52. Subject matter further comprising means or steps for employing
a memory to temporarily store the data and for increasing or decreasing the
size of the memory.
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57 | .. Fullness indication: |
This subclass is indented under subclass 52. Subject matter further comprising means or steps for employing a memory to temporarily store the data and for detecting or reporting the amount of data stored in the memory. | |
58 | . Input/Output process timing: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for regulating
when functions are performed in order to transfer data between the peripheral
and digital data processing system or computer.
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59 | .. Processing suspension: |
This subclass is indented under subclass 58. Subject matter further comprising means or steps for temporarily halting the performance of the function (e.g., to wait for data to be transferred from the peripheral). | |
60 | .. Transfer rate regulation: |
This subclass is indented under subclass 58. Subject matter further comprising means or steps for setting
the speed at which data are exchanged between the peripheral and
digital data processing system or computer.
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61 | .. Synchronous data transfer: |
This subclass is indented under subclass 58. Subject matter further comprising means or steps for exchanging data between the peripheral and digital data processing system or computer accompanied by clock pulses. | |
62 | . Peripheral adapting: |
This subclass is indented under subclass 1. Subject matter further comprising means or steps for making
the peripheral compatible with the digital data processing system
or computer.
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63 | .. Universal: |
This subclass is indented under subclass 62. Subject matter further comprising means or steps having the capability to interface different types of peripherals to the computer or digital data processing system. | |
64 | .. Via common units and peripheral-specific units: |
This subclass is indented under subclass 62. Subject matter further comprising means or steps for employing functional units generic to different types of peripherals and functional units specific to the different types to interface the peripherals and digital data processing systems or computers. | |
65 | .. Input/Output data modification: |
This subclass is indented under subclass 62. Subject matter further comprising means or steps for changing a format of data transferred between the peripheral and digital data processing system or computer. | |
66 | ... Width conversion: |
This subclass is indented under subclass 65. Subject matter further comprising means or steps for transferring
data between a peripheral that processes data of a first size and
digital data processing system or computer that process data of
a second size, different from the first.
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67 | ... Keystroke interpretation: |
This subclass is indented under subclass 65. Subject matter further comprising means or steps for changing
a signal that is generated by a keyboard into digital data.
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68 | ... Data compression and expansion: |
This subclass is indented under subclass 65. Subject matter further comprising means or steps for compacting
data for more efficient transferring between the peripheral and
digital data processing system or computer, or for more
efficient storage in peripheral.
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69 | ... Analog-to-digital or digital-to-analog: |
This subclass is indented under subclass 65. Subject matter further comprising means or steps for changing
the format from analog signal to digital data or vice versa.
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70 | ... Digital-to-digital: |
This subclass is indented under subclass 65. Subject matter further comprising means or steps for changing
the format from one type of digital data to another.
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71 | ... Serial-to-parallel or parallel-to-serial: |
This subclass is indented under subclass 65. Subject matter further comprising means or steps for changing the format from serial to parallel or vice versa. | |
72 | .. Application-specific peripheral adapting: |
This subclass is indented under subclass 62. Subject matter further comprising means or steps for making
certain types of peripheral compatible with digital data processing
system or computer.
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73 | ... For user input device: |
This subclass is indented under subclass 72. Subject matter wherein the peripheral is a user input device
other than a keyboard, per se, or a cursor controller, per
se.
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74 | ... For data storage device: |
This subclass is indented under subclass 72. Subject matter wherein the peripheral is a data storage
device.
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100 | INTRASYSTEM CONNECTING (E.G., BUS AND BUS TRANSACTION PROCESSING): |
This subclass is indented under the class definition. Subject matter comprising means or steps for interconnecting
or communicating between two or more components connected to an
interconnection medium (e.g., a
bus) within a single computer or digital data processing
system.
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300 | . Bus expansion or extension: |
This subclass is indented under subclass 100. Subject matter including means or steps for electrically
connecting additional circuit boards to the interconnection medium.
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301 | .. Card insertion: |
This subclass is indented under subclass 300. Subject matter wherein an additional circuit board is
capable of being plugged into or removed from a motherboard, backplane, or bus.
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302 | ... Hot insertion: |
This subclass is indented under subclass 301. Subject matter including means or steps for allowing plug-in or removal of the additional circuit board into or out of a powered motherboard or backplane. | |
303 | .. Docking station: |
This subclass is indented under subclass 300. Subject matter wherein a portable computer is electrically
connected to the interconnection medium.
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304 | ... Hot docking: |
This subclass is indented under subclass 303. Subject matter including means or steps for allowing plug-in or removal of the portable computer to the interconnection medium wherein at least one of the portable computer or interconnection medium is powered. | |
104 | . System configuring: |
This subclass is indented under subclass 100. Subject matter including means or steps for utilizing a
hardware structure for providing to a processor arrangement data
of the digital data processing system including a characteristic
of the digital data processing system"s component.
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105 | . Protocol: |
This subclass is indented under subclass 100. Subject matter including means or steps for providing
an exchange of information in accordance with a set of rules or
standards designed to enable digital data processing system components
to connect with each other.
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106 | .. Using transmitter and receiver: |
This subclass is indented under subclass 105. Subject matter including means or steps using a transmitter
and receiver for exchanging the information between the digital
data processing system components.
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107 | . Bus access regulation: |
This subclass is indented under subclass 100. Subject matter including means or steps for providing control
signals and commands to digital data processing system components connected
to the bus in order to maintain information-handling or
bus activities.
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108 | .. Bus locking: |
This subclass is indented under subclass 107. Subject matter including means or steps for preventing access
by a digital data processing system component to a shared interconnecting medium
while another digital data processing system component has temporary
exclusive control of the interconnecting medium.
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109 | .. Bus polling: |
This subclass is indented under subclass 107. Subject matter including means or steps for bus access regulating
by determining the status of each digital data processing system
component in a digital data processing system by another processing
digital data processing system component which accesses each of
the digital data processing system components one at a time.
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110 | .. Bus master/slave controlling: |
This subclass is indented under subclass 107. Subject matter wherein a digital data processing system
component is provided with control over other digital data processing
system components connected to the bus.
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111 | .. Rotational prioritizing (i.e., round robin): |
This subclass is indented under subclass 107. Subject matter including means or steps for granting bus access to all contending digital data processing system components one at a time in a predetermined order before any one digital data processing system components may again obtain the bus. | |
112 | .. Bus request queuing: |
This subclass is indented under subclass 107. Subject matter including means or steps for storing requests
for access to the bus in the order in which they are received.
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113 | .. Centralized bus arbitration: |
This subclass is indented under subclass 107. Subject matter including means or steps for determining
which of plural digital data processing system components contending
for access to a shared bus shall be granted access at any one time, wherein
the determination is performed by a single digital data processing
system component common to the digital data processing system components.
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114 | ... Static bus prioritization: |
This subclass is indented under subclass 113. Subject matter including means or steps for granting the
contending plural digital data processing system components access
to the bus in accordance with a fixed ranking assigned to each digital
data processing system component.
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115 | .... Physical position bus prioritization: |
This subclass is indented under subclass 114. Subject matter including means or steps for granting the
contending digital data processing system components access to the
shared bus based on their physical location on the bus.
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116 | ... Dynamic bus prioritization: |
This subclass is indented under subclass 113. Subject matter including means or steps for changing the
ranking of the contending digital data processing system components.
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117 | ... Time-slotted bus accessing: |
This subclass is indented under subclass 113. Subject matter including means or steps for granting the
contending digital data processing system components use of the
shared bus for a predetermined time period.
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118 | ... Delay reduction: |
This subclass is indented under subclass 113. Subject matter including means or steps for decreasing the
arbitration time among the contending digital data processing system
components on the bus.
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119 | .. Decentralized bus arbitration: |
This subclass is indented under subclass 107. Subject matter including means or steps for determining
which of plural digital data processing system components contending
for access to a shared bus shall be granted access at any one time, wherein
the determination is performed by circuitry located in more than
one of the contending digital data processing system components.
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120 | ... Hierarchical or multilevel accessing: |
This subclass is indented under subclass 119. Subject matter including means or steps for performing more
than one level of bus arbitration in order to grant access to one
of the contending digital data processing system components.
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121 | ... Static bus prioritization: |
This subclass is indented under subclass 119. Subject matter including means or steps for granting the
contending plural digital data processing system components access
to the bus in accordance with a fixed ranking assigned to each digital
data processing system component.
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122 | .... Physical position bus prioritization: |
This subclass is indented under subclass 121. Subject matter including means or steps for granting the
contending digital data processing system components access to the
shared bus based on their physical location on the bus.
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123 | ... Dynamic bus prioritization: |
This subclass is indented under subclass 119. Subject matter including means or steps for changing the
ranking of the contending digital data processing system components.
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124 | ... Time-slotted bus accessing: |
This subclass is indented under subclass 119. Subject matter including means or steps for granting the
contending digital data processing system components use of the
shared bus for a predetermined time period.
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125 | ... Delay reduction: |
This subclass is indented under subclass 119. Subject matter including means or steps for decreasing the
arbitration time among the contending digital data processing system
components on the bus.
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305 | . Bus interface architecture: |
This subclass is indented under subclass 100. Subject matter including means or steps for providing an interconnection structure for data transfer between digital data processing system components and a bus. | |
306 | .. Bus bridge: |
This subclass is indented under subclass 305. Subject matter wherein the interface architecture couples two or more buses to one another. | |
307 | ... Variable or multiple bus width: |
This subclass is indented under subclass 306. Subject matter wherein the coupled buses have different
bit sizes.
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308 | ... Direct memory accessing (e.g., DMA): |
This subclass is indented under subclass 306. Subject matter further comprising means or steps for
transferring data between peripherals and memories under control
of the bus bridge with little or no intervention from a main processor.
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309 | ... Arbitration: |
This subclass is indented under subclass 306. Subject matter wherein the bus bridge includes means or steps for determining which of plural digital data processing system components contending for access to a coupled bus at any one time. | |
310 | ... Buffer or que control: |
This subclass is indented under subclass 306. Subject matter including specific means or steps for control of temporary storage of data being transferred between coupled buses | |
311 | ... Intelligent bridge: |
This subclass is indented under subclass 306. Subject matter wherein the bridge includes advanced arithmetic and logic functions for controlling bridge operations. | |
312 | ... Multiple bridges: |
This subclass is indented under subclass 306. Subject matter including two or more bridges coupling three or more buses. | |
313 | ... Peripheral bus coupling (e.g., PCI, USB, ISA, and etc.): |
This subclass is indented under subclass 306. Subject matter wherein one of the coupled buses is an input/output bus (e.g., Peripheral Component Interconnect, Universal Serial Bus, Industry Standard Architecture, and etc.). | |
314 | ... Common protocol (e.g., PCI to PCI): |
This subclass is indented under subclass 306. Subject matter wherein the coupled buses operate according to the same signaling requirements (e.g., Peripheral Component Interconnect to Peripheral Component Interconnect). | |
315 | ... Different protocol (e.g., PCI to ISA): |
This subclass is indented under subclass 306. Subject matter wherein the coupled buses operate according to signaling requirements which are not the same (e.g., Peripheral Component Interconnect to Industry Standard Architecture). | |
316 | .. Path selecting switch: |
This subclass is indented under subclass 305. Subject matter including means or steps for establishing
a temporary connection or link between two digital data processing
system components by an intermediary station that serves to provide
the connection.
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317 | ... Crossbar: |
This subclass is indented under subclass 316. Subject matter wherein the intermediary station or stations are comprised of a matrix of switch points. | |
200 | ACCESS LOCKING: |
This subclass is indented under the class definition. Subject matter comprising means or steps for preventing
access to a shared resource of a computer or digital data processing
system.
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220 | ACCESS POLLING: |
This subclass is indented under the class definition. Subject matter comprising means or steps for granting access
to a shared resource of a computer of digital data processing system
by one of a plurality of components of the computer or digital data
processing system by interrogating each of the components in a predetermined
order.
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240 | ACCESS ARBITRATING: |
This subclass is indented under the class definition. Subject matter comprising means or steps for determining
which of a plurality of components of a computer system or digital
data processing system contending for access to a shared resource
shall be granted access at any one time based upon a predetermined
criteria.
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241 | . Centralized arbitrating: |
This subclass is indented under subclass 240. Subject matter further comprising means or steps for performing
the arbitration for the contending digital data processing system
components by a single processor.
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242 | . Decentralized arbitrating: |
This subclass is indented under subclass 240. Subject matter further comprising means or steps for performing
the arbitration for the contending digital data processing system
components by circuitry resident in each of the contending digital
data processing system components.
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243 | . Hierarchical or multilevel arbitrating: |
This subclass is indented under subclass 240. Subject matter further comprising means or steps for performing
more than one level of arbitration.
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244 | . Access prioritizing: |
This subclass is indented under subclass 240. Subject matter further comprising means or steps for granting the access in accordance with a predetermined ranking. | |
260 | INTERRUPT PROCESSING: |
This subclass is indented under the class definition. Subject matter comprising means or steps for stopping, halting, or
suspending a current processing function within a computer or digital
data processing system.
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261 | . Multimode interrupt processing: |
This subclass is indented under subclass 260. Subject matter wherein the digital data processing system or computer has multiple modes of operation and further comprising means or steps for processing the interrupt differently depending on a mode of operation of the digital data processing system or computer. | |
262 | . Interrupt inhibiting or masking: |
This subclass is indented under subclass 260. Subject matter further comprising means or steps for ignoring or delaying the interrupt. | |
263 | . Interrupt queuing: |
This subclass is indented under subclass 260. Subject matter further comprising means or steps for storing interrupt signals for later execution. | |
264 | . Interrupt prioritizing: |
This subclass is indented under subclass 260. Subject matter further comprising means or steps for processing plural interrupts in accordance with a predetermined ranking. | |
265 | .. Variable: |
This subclass is indented under subclass 264. Subject matter further comprising means or steps for changing a priority level of at least one interrupt in dependence on system conditions. | |
266 | . Programmable interrupt processing: |
This subclass is indented under subclass 260. Subject matter further comprising means or steps for processing the interrupt under the influence of a user changeable or replaceable stored program. | |
267 | . Processor status: |
This subclass is indented under subclass 260. Subject matter further comprising means or steps for processing the interrupt in accordance with the current condition of the digital data processing system, processor, or computer. | |
268 | . Source or destination identifier: |
This subclass is indented under subclass 260. Subject matter wherein the interrupt signal includes data identifying the source or destination of the interrupt. | |
269 | . Handling vector: |
This subclass is indented under subclass 260. Subject matter wherein the interrupt includes branch address
data or a peripheral unit identifier data identifying the location
of an interrupt handling routine.
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FOR000 | CLASS-RELATED FOREIGN DOCUMENTS |
This subclass has no definition. | |