CLASS 326, ELECTRONIC DIGITAL LOGIC CIRCUITRY |
1 | SUPERCONDUCTOR (E.G., CRYOGENIC, ETC.): |
This subclass is indented under the class definition. Subject matter including one or more logic circuits having
at least one element whose electrical resistance becomes essentially zero
at a very low temperature (e.g., 30 degrees Kelvin, etc.).
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2 | . Tunneling device: |
This subclass is indented under subclass 1. Subject matter including an electronic device whose operation is based on an ability (i.e., quantum mechanical nature) of certain atomic particles to pass through a barrier that they cannot pass over because of a required energy level. | |
3 | .. Josephson tunneling device: |
This subclass is indented under subclass 2. Subject matter including an electronic fast-switching device,
known as a Josephson junction device, which permits conduction through a
thin dielectric insulating layer by quantum mechanical tunneling.
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4 | ... Plural devices (e.g., distributive device, etc.): |
This subclass is indented under subclass 3. Subject matter including more than one Josephson junction device. | |
5 | ... Interference device (i.e., SQUID): |
This subclass is indented under subclass 3. Subject matter including a device which controls or modulates
electrical currents based on the quantum wave properties of a current
carrying electrons in solids.
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6 | .. Function of AND, OR, NAND, NOR, or NOT: |
This subclass is indented under subclass 2. Subject matter wherein the logic operations are limited
to those defined by the Boolean algebraic operations of AND, OR,
NAND, NOR, or NOT.
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7 | . Function of AND, OR, NAND, NOR, or NOT: |
This subclass is indented under subclass 1. Subject matter wherein the logic operations are limited
to those defined by the Boolean algebraic operations of AND, OR,
NAND, NOR, or NOT.
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8 | SECURITY (E.G., ACCESS OR COPY PREVENTION, ETC.): |
This subclass is indented under the class definition. Subject matter including an intentional disabling circuit
which conceals or prevents obtaining stored data or designed integrated circuit
structure.
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9 | RELIABILITY: |
This subclass is indented under the class definition. Subject matter having a device for improving the operational
quality of a logic circuit, such that an operational procedure yields the
same results on repeated trials.
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10 | . Redundant: |
This subclass is indented under subclass 9. Subject matter wherein the logic circuit comprises at least
one duplicate logic stage which will assume operation upon failure
of an original logic stage.
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11 | .. Voter circuit (e.g., majority logic, etc.): |
This subclass is indented under subclass 10. Subject matter including a logic level switching circuit
having a plurality of inputs which actuate the duplicate logic stage
whenever one of the following conditions is obtained (a) More than
half, but less than all inputs are "fault" (i.e.,
majority); (b) More than one, but less than half of all the inputs
are "fault" (i.e., minority); or (c) Various predetermined
combinations, together or in predetermined sequence, of the inputs
are "fault" (i.e., weighted).
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12 | .. With flip-flop: |
This subclass is indented under subclass 10. Subject matter comprising a logic circuit which has two
or more distinct current-conductive stable states and which toggles
from one state to the other in response to an external stimulus.
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13 | .. With field-effect transistor: |
This subclass is indented under subclass 10. Subject matter including a unipolar transistor in which
current carriers are injected at a source terminal and pass to a
drain terminal through a channel of semiconductor material whose
conductivity depends largely on an electrical field applied to the
semiconductor from a control electrode (gate).
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14 | . Fail-safe: |
This subclass is indented under subclass 9. Subject matter including a device which prevents generating
a valid output upon an operational failure of the logic circuitry.
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15 | . Parasitic prevention in integrated circuit structure: |
This subclass is indented under subclass 9. Subject matter wherein the logic device is part of a monolithic
integrated circuit, and is intended to prevent an unwanted interaction between
circuit components in the monolithic integrated circuit.
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16 | WITH TEST FACILITATING FEATURE: |
This subclass is indented under the class definition. Subject matter wherein the logic circuit includes a specific
circuit or device to enable a testing function to be performed (e.g.,
a bypass circuit that connects a signal input directly to an output,
thus bypassing the logic circuit for a testing purpose, etc.).
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17 | ACCELERATING SWITCHING: |
This subclass is indented under the class definition. Subject matter including a circuit to minimize the time
delay at the turn-on or turn-off period of the switch, therefore
increasing the switching speed.
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18 | . Bipolar transistor: |
This subclass is indented under subclass 17. Subject matter including a semiconductor device of the type
having at least three electrodes (emitter, base, and collector),
two potential barriers and having a controlled current flow of both
majority and minority carriers (i.e., holes and electrons).
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19 | .. With Schottky device: |
This subclass is indented under subclass 18. Subject matter including a semiconductor device which operates on the principle of injecting very highly concentrated (i.e., "hot") majority carriers across a potential difference barrier which is formed by the junction of a metal layer deposited on a lightly doped semiconductor crystal. | |
20 | ... Complementary transistors: |
This subclass is indented under subclass 19. Subject matter including at least two bipolar transistors of opposite conductivity types (i.e., npn and pnp). | |
21 | SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY: |
This subclass is indented under the class definition. Subject matter including a device to improve the reception
of input signals at the logic circuit, or a device to maintain without distortion
the logic signals produced at either (a) an output for coupling
or interfacing to another stage or stages or (b) an intermediate location
of the logic circuit to preclude signal or transmission deterioration
(e.g., by power dissipation or by reflection, etc.).
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22 | . Input noise margin enhancement: |
This subclass is indented under subclass 21. Subject matter having a circuit to reduce the possibility
of switching due to noise input instead of signal input.
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23 | .. With field-effect transistor: |
This subclass is indented under subclass 22. Subject matter including a unipolar transistor in which
current carriers are injected at a source terminal and pass to a
drain terminal through a channel of semiconductor material whose
conductivity depends largely on an electrical field applied to the
semiconductor from a control electrode (gate).
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24 | ... Complementary FET"s: |
This subclass is indented under subclass 23. Subject matter including at least a unit of two field-effect transistor elements connected in series with their gate terminals tied together, each having a channel of conductivity type opposite that of the other (e.g., p-channel versus n-channel). | |
25 | ... Depletion or enhancement: |
This subclass is indented under subclass 23. Subject matter wherein the logic circuit includes a depletion type which has its channel conductivity on for a zero or a negative gate-source voltage, or an enhancement type which is normally off with a zero or a negative applied gate-source voltage. | |
26 | . Output switching noise reduction: |
This subclass is indented under subclass 21. Subject matter having a circuit to reduce noise in a power supply line which is a function of parasitic inductance and the switching current. | |
27 | .. With field-effect transistor: |
This subclass is indented under subclass 26. Subject matter including a unipolar transistor in which
current carriers are injected at a source terminal and pass to a
drain terminal through a channel of semiconductor material whose
conductivity depends largely on an electrical field applied to the
semiconductor from a control electrode (gate).
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28 | ... With clocking: |
This subclass is indented under subclass 27. Subject matter wherein the logic circuit is responsive to
a predetermined time-related signal or a periodic signal in addition
to an input logic signal.
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29 | . Pulse shaping (e.g., squaring, etc.): |
This subclass is indented under subclass 21. Subject matter including a circuit to alter the waveform
of an output pulse signal, for example, steepening the edges of
a pulse.
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30 | . Bus or line termination (e.g., clamping, impedance matching, etc.): |
This subclass is indented under subclass 21. Subject matter having a circuit to preclude signal or transmission deterioration by (a) using an impedance element to eliminate the reflective wave energy caused by impedance differences between the network and a connected circuit or (b) using a diode circuit to clamp or to clip the reflective wave riding on the top of an incident wave. | |
31 | . Signal level or switching threshold stabilization: |
This subclass is indented under subclass 21. Subject matter having a circuit to keep relatively constant the dc output signal levels, or the dc switching voltage levels. | |
32 | .. Temperature compensation: |
This subclass is indented under subclass 31. Subject matter wherein the output signal levels or the switching
threshold levels are kept relatively constant in an environment
having temperature changes.
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33 | .. Bias or power supply level stabilization: |
This subclass is indented under subclass 31. Subject matter wherein the output signal levels or the switching
threshold levels are compensated for fluctuations in voltage or
current supply.
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34 | .. With field-effect transistor: |
This subclass is indented under subclass 31. Subject matter including a unipolar transistor in which
current carriers are injected at a source terminal and pass to a
drain terminal through a channel of semiconductor material whose
conductivity depends largely on an electrical field applied to the
semiconductor from a control electrode (gate).
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35 | THRESHOLD (E.G., MAJORITY, MINORITY, OR WEIGHTED INPUTS, ETC.): |
This subclass is indented under the class definition. Subject matter including a logic level switching circuit
which has a plurality of inputs which actuate the output to switch
to one of at least two logic levels whenever one of the following
conditions is obtained: (a) More than half, but less than all of
the inputs are "on" (i.e., majority); (b) More
than one, but less than half of all the inputs are "on" (i.e.,
minority); or (c) Various predetermined combinations, together or
in predetermined sequence, of the inputs are "on" (i.e.,
weighted).
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36 | . With field-effect transistor: |
This subclass is indented under subclass 35. Subject matter including a unipolar transistor in which
current carriers are injected at a source terminal and pass to a
drain terminal through a channel of semiconductor material whose
conductivity depends largely on an electrical field applied to the
semiconductor from a control electrode (gate).
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37 | MULTIFUNCTIONAL OR PROGRAMMABLE (E.G., UNIVERSAL, ETC.): |
This subclass is indented under the class definition. Subject matter including (a) a logic circuit capable of
either producing different logic function operations from the same
logic element or providing a particular, selected (i.e., programmed)
logic operation from plural logic elements (e.g., an array, etc.)
or (b) details related to the actual setting or programming of the
desired logic functions in such a logic circuit.
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38 | . Having details of setting or programming of interconnections or logic functions: |
This subclass is indented under subclass 37. Subject matter which includes specific procedures which
establish the desired overall logic circuit operation.
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39 | . Array (e.g., PLA, PAL, PLD, etc.): |
This subclass is indented under subclass 37. Subject matter having a group of many similar logic elements
connected in series or in parallel (row or column) to
form a matrix of two or three dimensions wherein the interconnection between
rows or columns can be selectively connected to perform a logical
function.
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40 | .. With flip-flop or sequential device: |
This subclass is indented under subclass 39. Subject matter comprising a logic circuit which has two
or more distinct current-conductive stable states which
toggles from one state to the other in response to an external stimulus
or comprising a series connection of such circuits.
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41 | .. Significant integrated structure, layout, or layout interconnections: |
This subclass is indented under subclass 39. Subject matter including an arrangement of components fabricated
in a semiconductor material or integrated circuit chip with significant
design emphasis on the topological arrangement of the components
and their circuit connectors.
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42 | .. Bipolar transistor: |
This subclass is indented under subclass 39. Subject matter including a semiconductor device of the type
having at least three electrodes (emitter, base, and
collector), two potential barriers and having
a controlled current flow of both majority and minority carriers (i.e., holes
and electrons).
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43 | ... Emitter-coupled logic or emitter-follower logic: |
This subclass is indented under subclass 42. Subject matter wherein the logic function unit includes either (a) an emitter-coupled arrangement which has the emitters of plural input transistors connected to the emitter and the base of a referenced transistor and commonly grounded (biased) through a current source for performing a nonsaturated, differential logic operation or (b) an emitter-follower arrangement which has a plurality of transistors with the emitters commonly coupled as an output and which produces, as an output, a signal which is in phase with the input logic signals. | |
44 | .. Field-effect transistor: |
This subclass is indented under subclass 39. Subject matter wherein the logic circuit includes a unipolar
transistor in which current carriers are injected at a source terminal
and pass to a drain terminal through a channel of semiconductor
material whose conductivity depends largely on an electrical field
applied to the semiconductor from a control electrode (gate).
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45 | ... Complementary FET"s: |
This subclass is indented under subclass 44. Subject matter wherein the logic function unit includes at least two field-effect transistor elements connected in series with their gate terminals tied together, each having a channel of conductivity type opposite that of the other (e.g., p-channel versus n-channel, etc.). | |
46 | . Sequential (i.e., finite state machine) or with flip-flop: |
This subclass is indented under subclass 37. Subject matter comprising a logic circuit which has an output
state dependent on a previous input state or which has two or more
distinct current-conductive stable states and which toggles
from one state to the other in response to an external stimulus.
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47 | . Significant integrated structure, layout, or layout interconnections: |
This subclass is indented under subclass 37. Subject matter including an arrangement of components fabricated
in a semiconductor material or integrated circuit chip with significant
design emphasis on the topological arrangement of the components
and their circuit connectors.
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48 | . Bipolar transistor: |
This subclass is indented under subclass 37. Subject matter including a semiconductor device of the type
having at least three electrodes (emitter, base, and
collector), two potential barriers, and
having a controlled current flow of both majority and minority carriers (i.e., holes
and electrons).
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49 | . Field-effect transistor: |
This subclass is indented under subclass 37. Subject matter wherein the logic circuit includes a unipolar
transistor in which current carriers are injected at a source terminal
and pass to a drain terminal through a channel of semiconductor
material whose conductivity depends largely on an electrical field
applied to the semiconductor from a control electrode (gate).
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50 | .. Complementary FET"s: |
This subclass is indented under subclass 49. Subject matter wherein the logic function unit includes at least two field-effect transistor elements connected in series with their gate terminals tied together, each having a channel of conductivity type opposite that of the other (e.g., p-channel versus n-channel, etc.). | |
51 | INHIBITOR: |
This subclass is indented under the class definition. Subject matter wherein the logic circuit includes plural
input terminals and operates in a manner such that when a digital "on" signal is
present at a particular input (known as the inhibit input) to
the logic circuit, the logical output from the logic circuit
is blocked; and when the inhibit input signal is absent, the
logical output from the logic circuit is affected only by signals
at the remaining inputs.
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52 | EXCLUSIVE FUNCTION (E.G., EXCLUSIVE OR, ETC.): |
This subclass is indented under the class definition. Subject matter including a logic circuit which produces
an output signal which is a function of whether or not the inputs
are uniformly identical.
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53 | . Half-adder or quarter-adder: |
This subclass is indented under subclass 52. Subject matter comprising a logic circuit which has two
input and two output channels for binary signals, and which
operates to produce an output signal (i.e., sum) on
one of the output channels when one, but not both, of
the input signals is present and an output (i.e., carry) on the
other output channel when both of the input signals are present.
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54 | . Exclusive NOR: |
This subclass is indented under subclass 52. Subject matter comprising a logic circuit which produces
an output signal only if all logic input signals are identical (i.e., all
are logically true or all are logically false).
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55 | . With field-effect transistor: |
This subclass is indented under subclass 52. Subject matter including a unipolar transistor in which
current carriers are injected at a source terminal and pass to a
drain terminal through a channel of semiconductor material whose
conductivity depends largely on an electrical field applied to the
semiconductor from a control electrode (gate).
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56 | TRI-STATE (I.E., HIGH IMPEDANCE AS THIRD STATE): |
This subclass is indented under the class definition. Subject matter wherein the logic device produces any of three conditions on one line: (a) a definite high voltage (logic 1); (b) a definite low voltage (logic 0); or (c) a high impedance or open-circuit condition (i.e., a floating state or undefined state) which permits another part of the circuit to determine whether the line will be high or low. | |
57 | . With field-effect transistor: |
This subclass is indented under subclass 56. Subject matter wherein the logic circuit includes a unipolar
transistor in which current carriers are injected at a source terminal
and pass to a drain terminal through a channel of semiconductor
material whose conductivity depends largely on an electrical field
applied to the semiconductor from a control electrode (gate).
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58 | .. Complementary FET"s: |
This subclass is indented under subclass 57. Subject matter including at least a unit of two field-effect transistors connected in series with their gate terminals tied together, each having a channel of conductivity type opposite that of the other (e.g., p-channel versus n-channel, etc.). | |
59 | THREE OR MORE ACTIVE LEVELS (E.G., TERNARY, QUATENARY, ETC.): |
This subclass is indented under the class definition. Subject matter wherein the logic circuit is responsive to
three or more input logic signal states, or it produces
three or more different output logic signal states.
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60 | . With conversion (e.g., three level to two level, etc.): |
This subclass is indented under subclass 59. Subject matter wherein the logic circuit can be readily modified between varieties having a differing number of active states. | |
61 | INSULATED GATE CHARGE TRANSFER DEVICE: |
This subclass is indented under the class definition. Subject matter wherein the logic circuit includes a semiconductor
device having plural control electrodes separated from the conducting
body by an insulating layer which control the electrostatic potential
of the surface of the body in response to timely applied signals
to effect a sequential transferring of charge.
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62 | INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.): |
This subclass is indented under the class definition. Subject matter comprising an intermediate circuit or a coupling
circuit for providing an operational compatibility between noncommon logic
function devices or between a logic function device and its circuit
environment.
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63 | . Logic level shifting (i.e., interface between devices of different logic families): |
This subclass is indented under subclass 62. Subject matter comprising an intermediate circuit or a coupling
circuit for providing an operational compatibility between devices
of different logic families, wherein conversion of parameters
is required (e.g., input logic
levels, logic signal pulse widths (duty cycle), power supply
biasing levels, etc.).
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64 | .. Bi-CMOS: |
This subclass is indented under subclass 63. Subject matter wherein the interfacing circuit includes
a bipolar transistor and a complementary metal-oxide transistor
device.
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65 | ... TTL to/from CMOS: |
This subclass is indented under subclass 64. Subject matter comprising the interfacing between a transistor-transistor
logic device and a complementary metal-oxide semiconductor device.
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66 | ... ECL to/from CMOS: |
This subclass is indented under subclass 64. Subject matter comprising the interfacing between an emitter-coupled
logic device and a complementary metal-oxide semiconductor device.
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67 | ... ECL to/from TTL: |
This subclass is indented under subclass 64. Subject matter comprising the interfacing between an emitter-coupled
logic circuit and a transistor-transistor logic circuit.
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68 | .. Field-effect transistor (e.g., JFET, MOSFET, etc.): |
This subclass is indented under subclass 63. Subject matter wherein the interfacing circuit includes
a unipolar transistor in which current carriers are injected at
a source terminal and pass to a drain terminal through a channel
of semiconductor material whose conductivity depends largely on
an electrical field applied to the semiconductor from a control
electrode (gate).
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69 | ... ECL to/from GaAs FET (e.g., MESFET, etc.): |
This subclass is indented under subclass 68. Subject matter comprising the interfacing between an emitter-coupled
logic device and a logic device from a family of GaAs material semiconductor
field-effect transistor.
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70 | ... TTL to/from MOS: |
This subclass is indented under subclass 68. Subject matter comprising the interfacing between a transistor-transistor
logic device and a metal-oxide semiconductor device.
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71 | .... TTL to/from CMOS: |
This subclass is indented under subclass 70. Subject matter comprising the interfacing between a transistor-transistor
logic device and a complementary MOS device.
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72 | ..... Using depletion or enhancement transistors: |
This subclass is indented under subclass 71. Subject matter which includes either a depletion type which is normally on for zero or negative voltage bias or an enhancement type which is normally off with zero or negative voltage bias applied. | |
73 | ... ECL to/from MOS: |
This subclass is indented under subclass 68. Subject matter comprising the interfacing between an emitter-coupled
logic device and a complementary MOS device.
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74 | ... ECL to/from TTL: |
This subclass is indented under subclass 68. Subject matter comprising the interfacing between an emitter-coupled
logic device and a transistor-transistor logic device.
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75 | .. Bipolar transistor: |
This subclass is indented under subclass 63. Subject matter wherein the interfacing circuit includes a semiconductor device having at least three electrodes (emitter, base, and collector), two potential barriers, and a controlled current flow of both majority and minority carriers (i.e., holes and electrons). | |
76 | ... TTL to/from MOS: |
This subclass is indented under subclass 75. Subject matter comprising the interfacing between a transistor-transistor
logic device and a metal-oxide semiconductor device.
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77 | ... ECL to/from MOS: |
This subclass is indented under subclass 75. Subject matter comprising the interfacing between an emitter-coupled
logic device and a metal-oxide semiconductor device.
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78 | ... ECL to/from TTL: |
This subclass is indented under subclass 75. Subject matter comprising the interfacing between an emitter-coupled
logic device and a transistor-transistor logic device.
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79 | ... Integrated injection logic (I2L): |
This subclass is indented under subclass 75. Subject matter including either a complementary bipolar
transistor pair merged on the same substrate, incorporating; (a) a
vertical, inverse mode npn (conversely pnp) transistor, which can
have isolated multicollector regions, and (b) a
pnp (conversely npn) lateral transistor which
serves as a current injector to inject charge current directly
into the vertical, inverse mode transistor base; OR
a bipolar or FET transistor pair merged on the same substrate wherein; (a) the
base of an inverse mode bipolar transistor is injected with charge
current by a FET current injector, or (b) the inverse
mode transistor is a FET device (e.g., enhancement-mode
junction field-effect transistor (enhancement
JFET) with bipolar or FET charge current injection.
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80 | . Supply voltage level shifting (i.e., interface between devices of a same logic family with different operating voltage levels): |
This subclass is indented under subclass 62. Subject matter comprising a circuit for translating signal
data from one device to another device of the same logic family
but which operate at differing voltage supply levels.
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81 | .. CMOS: |
This subclass is indented under subclass 80. Subject matter including a device having a p-channel
and an n-channel enhancement type metal-oxide
field-effect transistor (MOSFET) which
are connected in series across a power supply with their gates tied
together.
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82 | . Current driving (e.g., fan in/out, off chip driving, etc.): |
This subclass is indented under subclass 62. Subject matter comprising a current converting circuit to
provide an operating compatibility between a logic function device
and its circuit environment which may be a higher current load device (off
chip driving), or a series connection of plural
small loads which result in higher current drawing (fan
in/out).
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83 | .. Field-effect transistor: |
This subclass is indented under subclass 82. Subject matter wherein the current driving circuit includes
a unipolar transistor in which current carriers are injected at
a source terminal and pass to a drain terminal through a channel of
semiconductor material whose conductivity depends largely on an
electrical field applied to the semiconductor from a control electrode (gate).
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84 | ... Bi-CMOS: |
This subclass is indented under subclass 83. Subject matter wherein the current driving circuit includes
both bipolar and complementary metal-oxide semiconductor
transistors.
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85 | .... Having plural output pull-up or pull-down transistors: |
This subclass is indented under subclass 84. Subject matter wherein multiple transistors at the circuit output help maintain the output at logic high (pull-up) or logic low (pull-down) levels as needed. | |
86 | ... Bus driving: |
This subclass is indented under subclass 83. Subject matter including a common path for connecting a
number of devices in a digital system.
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87 | ... Having plural output pull-up or pull-down transistors: |
This subclass is indented under subclass 83. Subject matter wherein multiple transistors at the circuit output help maintain the output at logic high (pull-up) or logic low (pull-down) levels as needed. | |
88 | ... With capacitive or inductive bootstrapping: |
This subclass is indented under subclass 83. Subject matter wherein the logic circuit includes discrete, capacitive
or inductive elements or uses its inherent capacitance or inductance
to enhance its operating condition, to achieve full driving
switching capabilities in response to logic input signals.
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89 | .. Bipolar transistor: |
This subclass is indented under subclass 82. Subject matter wherein the current driving circuit includes a semiconductor device having at least three electrodes (emitter, base, and collector), two potential barriers (npn or pnp), and having a controlled current flow of both majority and minority carriers (i.e., holes and electrons). | |
90 | ... Bus driving: |
This subclass is indented under subclass 89. Subject matter including a common path for connecting a
number of devices in a digital system.
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91 | ... Having plural output pull-up or pull-down transistors: |
This subclass is indented under subclass 89. Subject matter wherein multiple transistors at the circuit output help maintain the output at logic high (pull-up) or logic low (pull-down) levels as needed. | |
92 | ... With capacitive or inductive bootstrapping: |
This subclass is indented under subclass 89. Subject matter wherein the logic circuit includes discrete, capacitive, or
inductive elements or uses its inherent capacitance or inductance
to enhance its operating condition, to achieve full driving
switching capabilities in response to logic input signals.
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93 | CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES: |
This subclass is indented under the class definition. Subject matter wherein individual logic stages or gates
are responsive to predetermined time-related signals or
periodic signals in addition to an input logic signal.
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94 | . Metastable state prevention: |
This subclass is indented under subclass 93. Subject matter including a circuit to prevent the occurrence
of an undecided condition at a logic state transition.
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95 | . Field-effect transistor: |
This subclass is indented under subclass 93. Subject matter wherein the logic circuit includes a unipolar
transistor in which current carriers are injected at a source terminal
and pass to a drain terminal through a channel of semiconductor
material whose conductivity depends largely on an electrical field
applied to the semiconductor from a control electrode (gate).
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96 | .. Two or more clocks (e.g., phase clocking, etc.): |
This subclass is indented under subclass 95. Subject matter wherein the logic circuit is responsive to
two or more predetermined time-related signals or periodic
signals in addition to the input logic signal.
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97 | ... MOSFET: |
This subclass is indented under subclass 96. Subject matter includes a field-effect transistor having a metallic gate insulated from the channel by an oxide layer (e.g., SiO2, etc.). | |
98 | .. MOSFET: |
This subclass is indented under subclass 95. Subject matter includes a field-effect transistor having a metallic gate insulated from the channel by an oxide layer (e.g., SiO2, etc.). | |
99 | HAVING LOGIC LEVELS CONVEYED BY SIGNAL FREQUENCY OR PHASE: |
This subclass is indented under the class definition. Subject matter wherein the logic circuit receives or produces
digital signals which are different in the number of periodic cycles
in a unit of time (frequency), or in
the relative timing of a signal in relation to another signal (phase).
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100 | INTEGRATED INJECTION LOGIC: |
This subclass is indented under the class definition. Subject matter including either a complementary bipolar
transistor pair merged on the same substrate, incorporating (a) a
vertical, inverse mode npn (conversely pnp) transistor, which
can have isolated multicollector regions, and (b) a
pnp (conversely npn) lateral transistor which
serves as a current injector to inject charge current directly
into the vertical, inverse mode transistor base; OR
a bipolar or FET transistor pair merged on the same substrate wherein; (a) the
base of an inverse mode bipolar transistor is injected with charge
current by a FET current injector, or (b) the inverse
mode transistor is a FET device (e.g., enhancement-mode
junction field-effect transistor (enhancement
JFET, etc.) with bipolar or FET charge
current injection.
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101 | SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS: |
This subclass is indented under the class definition. Subject matter including an arrangement of components fabricated
in a semiconductor material or integrated circuit chip with significant
design emphasis on the topological arrangement of the components
and their circuit connectors.
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102 | . Field-effect transistor: |
This subclass is indented under subclass 101. Subject matter wherein the logic means includes a unipolar
transistor in which current carriers are injected at a source terminal
and pass to a drain terminal through a channel of semiconductor
material whose conductivity depends largely on an electrical field
applied to the semiconductor from a control electrode (gate).
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103 | .. Complementary FET"s: |
This subclass is indented under subclass 102. Subject matter wherein the logic function unit includes
at least two field-effect transistor elements connected
in series across a power supply with their gates linked together, each having
a channel of conductivity type opposite that of the other (e.g., p-channel
versus n-channel, etc.).
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104 | FUNCTION OF AND, OR, NAND, NOR, OR NOT: |
This subclass is indented under the class definition. Subject matter wherein the logic operations are limited
to those defined by the Boolean algebraic operations of AND, OR, NAND, NOR, or
NOT.
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105 | . Decoding: |
This subclass is indented under subclass 104. Subject matter wherein logic gates are selectively responsive
to particular binary combinations of logic signals to provide a
binary output command signal.
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106 | .. With field-effect transistor: |
This subclass is indented under subclass 105. Subject matter wherein the logic circuit includes a unipolar
transistor in which current carriers are injected at a source terminal
and pass to a drain terminal through a channel of semiconductor
material whose conductivity depends largely on an electrical field
applied to the semiconductor from a control electrode (gate).
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107 | ... Depletion or enhancement: |
This subclass is indented under subclass 106. Subject matter wherein the decoder includes either a depletion type which has channel conductivity on for zero or negative gate-source voltage or an enhancement type which is normally off with zero or negative gate source voltage bias applied. | |
108 | ... CMOS: |
This subclass is indented under subclass 106. Subject matter wherein the logic function unit includes
at least two metal-oxide field-effect transistors (MOSFET), each
having a channel of conductivity type opposite that of the other (e.g.,
p-channel versus n-channel, etc.).
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109 | . Bipolar and FET: |
This subclass is indented under subclass 104. Subject matter wherein the logic circuit includes two types
of transistors: (a) a bipolar transistor having at least three
electrodes (emitter, base, and collector), two potential barriers, and
wherein a controlled current flow comprises both majority and minority
carriers (i.e., holes and electrons) and (b) a unipolar transistor
in which current carriers are injected at a source terminal and
pass to a drain terminal through a channel of semiconductor material whose
conductivity depends largely on an electrical field applied to the
semiconductor from a control electrode (gate).
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110 | .. Bi-CMOS: |
This subclass is indented under subclass 109. Subject matter wherein the logic function circuit comprises a bipolar transistor and a unit of two enhancement type metal-oxide field-effect transistor elements connected in series with their gates tied together, each element has a channel of conductivity type opposite that of the other (e.g., p-channel versus n-channel, etc.). | |
111 | . Space discharge device (e.g., vacuum tube, etc.): |
This subclass is indented under subclass 104. Subject matter including an electronic device having an electrical current flow of charged particles (e.g., ions or electrons) in an area between two spaced electrodes and with at least part of that area being constituted by a gas, vapor, or vacuum. | |
112 | . Field-effect transistor (e.g., JFET, etc.): |
This subclass is indented under subclass 104. Subject matter wherein the logic circuit includes a unipolar
transistor in which current carriers are injected at a source terminal
and pass to a drain terminal through a channel of semiconductor
material whose conductivity depends largely on an electrical field
applied to the semiconductor from a control electrode (gate).
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113 | .. Pass transistor logic or transmission gate logic: |
This subclass is indented under subclass 112. Subject matter wherein a field-effect transistor performs
a logic function using power from two signal inputs which feed through
a gate and a source (or drain) terminals with an output taken at
the drain (or source) terminal which is an AND function of the two
signal inputs.
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114 | .. Wired logic (e.g., wired-OR, wired-AND, dotted logic, etc.): |
This subclass is indented under subclass 112. Subject matter which includes a logic family having their
output gates eliminated simply by wiring the outputs of some basic
logic circuits together, the resultant circuit is called wired-OR
or wired-AND depending on the type of logic, and the joint output
is in turn input to other logic gates for performing additional logic
functions.
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115 | .. Source-coupled logic (e.g., current mode logic (CML), differential current switch logic (DCSL), etc.): |
This subclass is indented under subclass 112. Subject matter wherein the logic function unit includes
an arrangement in which the source channel of plural input transistors
are connected to the source and the gate of a referenced transistor,
and are commonly grounded (biased) through a current source for
performing a nonsaturated, differential logic operation.
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116 | .. Schottky-gate FET (i.e., MESFET): |
This subclass is indented under subclass 112. Subject matter including a junction field-effect transistor
which operates on the principle of the injection of very highly
concentrated majority carriers across a potential difference barrier which
is formed by the junction of a lightly doped semiconductor material
and a metal layer deposited thereon.
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117 | ... Depletion or enhancement: |
This subclass is indented under subclass 116. Subject matter wherein the logic circuit includes either a depletion type which has channel conductivity on for zero or negative gate-source voltage or an enhancement type which is normally off with zero or negative gate-source voltage bias applied. | |
118 | ... Diode transistor logic: |
This subclass is indented under subclass 116. Subject matter wherein diodes are active switching elements responsive to respective input logic signals for providing logical function outputs which control output transistor elements. | |
119 | .. MOSFET (i.e., metal-oxide semiconductor field-effect transistor): |
This subclass is indented under subclass 112. Subject matter includes a field-effect transistor having a metallic gate insulated from the channel by an oxide layer (e.g., SiO2, etc.). | |
120 | ... Depletion or enhancement: |
This subclass is indented under subclass 119. Subject matter wherein the logic circuit includes either a depletion type which has channel conductivity on for zero or negative gate-source voltage, or an enhancement type which is normally off with zero or negative gate-source voltage bias applied. | |
121 | ... CMOS: |
This subclass is indented under subclass 119. Subject matter wherein the logic function unit includes two enhancement mode metal-oxide semiconductor field-effect transistor elements connected in series with gates tied together, each having a channel of conductivity type opposite that of the other (i.e., P-MOS versus N-MOS). | |
122 | .. Complementary FET"s: |
This subclass is indented under subclass 112. Subject matter wherein the logic function unit includes at least two field-effect transistor elements, each having a channel of conductivity type opposite that of the other (e.g., p-channel versus n-channel, etc.). | |
123 | .. With semiconductor diode or negative resistance device: |
This subclass is indented under subclass 112. Subject matter wherein the logic function unit includes (a) a semiconductor device having two electrodes (anode and cathode) and a single junction (pn) that allows current to flow in only one direction; or (b) a semiconductor device characterized by an operating current-voltage plot having a portion with a negative slope. | |
124 | . Bipolar transistor (e.g., RTL, DCTL, etc.): |
This subclass is indented under subclass 104. Subject matter including a semiconductor device of the type
having at least three electrodes (emitter, base, and collector),
two potential barriers, and wherein a controlled current flow comprises
both majority and minority carriers (i.e., holes and electrons).
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125 | .. Wired logic or open collector logic (e.g., wired-OR, wired-AND, dotted logic, etc.): |
This subclass is indented under subclass 124. Subject matter which includes a logic family having their
output gates eliminated simply by wiring the outputs of some basic
logic circuits together, the resultant circuit is called wired-OR
or wired-AND depending on the type of logic, and the joint output
is in turn input to other logic gates for performing additional logic
functions.
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126 | .. Emitter-coupled or emitter-follower logic: |
This subclass is indented under subclass 124. Subject matter wherein the logic function unit includes either: (a) an emitter-coupled arrangement which has the emitters of plural input transistors connected to the emitter and the base of a referenced transistor and commonly grounded (biased) through a current source for performing a nonsaturated, differential logic operation; or (b) an emitter-follower arrangement which has a plurality of transistors with the emitters commonly coupled as an output and which produces, as an output, a signal which is in phase with the input logic signals. | |
127 | ... Current mode logic (CML): |
This subclass is indented under subclass 126. Subject matter wherein the logic utilizes an emitter-coupled arrangement which provides complementary collector outputs and functions as a NOR/OR circuit. | |
128 | .. Transistor-transistor logic (TTL): |
This subclass is indented under subclass 124. Subject matter wherein the logic function unit includes
a forward-biased input transistor which is responsive to an input
logic signal at each of its one or more emitters and with its collector
being directly coupled to the base of an output transistor.
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129 | ... Complementary transistor logic (CTL): |
This subclass is indented under subclass 128. Subject matter wherein the logic function unit includes transistors of opposite conductivity type (e.g., npn and pnp type, etc.). | |
130 | .. Diode-transistor logic (DTL): |
This subclass is indented under subclass 124. Subject matter wherein diodes are active switching elements responsive to respective input logic signals for providing logical function outputs which control output transistor elements. | |
131 | ... With metal semiconductor junction diode (e.g., Schottky barrier, etc.): |
This subclass is indented under subclass 130. Subject matter wherein the diode transistor logic device includes diodes of the type which operate on the principle of the injection of very highly concentrated (i.e., "hot") majority carriers across a potential difference barrier which is formed by the junction of a lightly doped semiconductor crystal and a metal layer deposited thereon. | |
132 | .. With negative resistance device (e.g., tunnel diode, thyristor, etc.): |
This subclass is indented under subclass 124. Subject matter wherein the bipolar transistor logic circuit
includes a semiconductor device characterized by an operating current-voltage plot
having a portion with a negative slope.
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133 | . Diode: |
This subclass is indented under subclass 104. Subject matter including a two electrode (anode and cathode), single junction (pn) semiconductor device used as an active switching element responsive to respective input logic signals to perform the logic function. | |
134 | .. Negative resistance diode (e.g., tunnel, gunn, etc.): |
This subclass is indented under subclass 133. Subject matter includes a diode characterized by an operating
current-voltage plot having a portion with a negative slope.
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135 | . Negative resistance device: |
This subclass is indented under subclass 104. Subject matter which includes a semiconductor device characterized
by an operating current-voltage plot having a portion with a negative slope.
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136 | MISCELLANEOUS: |
This subclass is indented under the class definition. Subject matter not provided for in any of the preceding subclasses. | |
FOR000 | CLASS-RELATED FOREIGN DOCUMENTS |
This subclass has no definition. | |