US 9,814,106 B2
Backlight driver chip incorporating a phase lock loop (PLL) with programmable offset/delay and seamless operation
Asif Hussain, San Jose, CA (US); Andrew P. Aitken, Cupertino, CA (US); and Manisha P. Pandya, Sunnyvale, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 30, 2014, as Appl. No. 14/502,945.
Claims priority of provisional application 61/897,796, filed on Oct. 30, 2013.
Prior Publication US 2015/0116380 A1, Apr. 30, 2015
Int. Cl. G09G 3/34 (2006.01); H05B 33/08 (2006.01)
CPC H05B 33/0815 (2013.01) [G09G 3/342 (2013.01); G09G 3/3406 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/064 (2013.01); Y02B 20/346 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A control circuit for a display device, the control circuit comprising:
a phase detection module configured to concurrently receive a frequency-scaled (FS) feedback signal and an input clock signal, and provide a phase adjustment signal;
a voltage controlled oscillator (VCO) connected to: (i) the phase detection module, and (ii) separate arithmetic operators that are configured to provide the FS feedback signal and an output clock signal based on the phase adjustment signal;
a delay module, coupled to a first arithmetic operator of the separate arithmetic operators, wherein: i) the delay module comprises one or more selectable gate delays and ii) the delay module is configured to offset, by a delay value, a pulse edge of the output clock signal from a pulse edge of the input clock signal; and
a dimming generator coupled to an output of the delay module, wherein the delay value is based on a clock rate of the dimming generator.