US 9,813,653 B2
Solid state imaging device, method of controlling solid state imaging device, and program for controlling solid state imaging device
Takashi Kawaguchi, Fukuoka (JP)
Assigned to Sony Corporation, Tokyo (JP)
Filed by Sony Corporation, Tokyo (JP)
Filed on Apr. 18, 2017, as Appl. No. 15/490,590.
Application 15/397,631 is a division of application No. 15/298,574, filed on Oct. 20, 2016, granted, now 9,609,240.
Application 15/490,590 is a continuation of application No. 15/397,631, filed on Jan. 3, 2017.
Application 15/298,574 is a continuation of application No. 14/622,681, filed on Feb. 13, 2015, granted, now 9,692,994.
Application 14/622,681 is a continuation of application No. 13/598,986, filed on Aug. 30, 2012, granted, now 9,094,623.
Claims priority of application No. 2011-207368 (JP), filed on Sep. 22, 2011.
Prior Publication US 2017/0223297 A1, Aug. 3, 2017
Int. Cl. H01L 27/00 (2006.01); H04N 5/378 (2011.01); H04N 5/374 (2011.01); H04N 5/347 (2011.01); H04N 9/04 (2006.01); H01L 27/146 (2006.01)
CPC H04N 5/378 (2013.01) [H01L 27/14621 (2013.01); H01L 27/14636 (2013.01); H01L 27/14645 (2013.01); H04N 5/347 (2013.01); H04N 5/374 (2013.01); H04N 9/045 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An imaging device comprising:
a plurality of pixels arranged in columns and rows, the plurality of pixels including a first pixel in an ith column and a second pixel in a i+1th column;
a plurality of signal lines arranged in a column direction, the plurality of signal lines including a first signal line coupled to the first pixel and a second signal line coupled to a second pixel;
a plurality of comparators including a first comparator coupled to the first signal line, and a second comparator coupled to the second signal line;
a plurality of counters including a first counter and a second counter; and
an output control circuit configured to couple an output terminal of the first comparator and an output terminal of the second comparator to an input terminal of the first counter, and couple the output terminal of the first comparator and the output terminal of the second comparator to an input terminal of the second counter,
wherein the output control circuit includes a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit,
wherein the first switching circuit is coupled to the output terminal of the first comparator and the input terminal of the first counter,
wherein the second switching circuit is coupled to the output terminal of the first comparator and the input terminal of the second counter,
wherein the third switching circuit is coupled to the output terminal of the second comparator and the input terminal of the first counter,
wherein the fourth switching circuit is coupled to the output terminal of the second comparator and the input terminal of the second counter, and
wherein the first switch circuit and the fourth switch circuit are configured to switch at a same time.