US 9,813,648 B2
Semiconductor apparatus, solid-state image sensing apparatus, and camera system having via holes between substrates
Toshiaki Nagai, Kanagawa (JP); Ken Koseki, Kanagawa (JP); Yosuke Ueno, Kanagawa (JP); and Atsushi Suzuki, Kanagawa (JP)
Assigned to Sony Corporation, Tokyo (JP)
Filed by Sony Corporation, Tokyo (JP)
Filed on Jan. 24, 2017, as Appl. No. 15/414,019.
Application 15/414,019 is a continuation of application No. 15/264,272, filed on Sep. 13, 2016, granted, now 9,654,708.
Application 15/264,272 is a continuation of application No. 15/078,984, filed on Mar. 23, 2016, granted, now 9,509,933, issued on Nov. 29, 2016.
Application 15/078,984 is a continuation of application No. 14/348,722, granted, now 9,350,929, issued on May 24, 2016, previously published as PCT/JP2012/006497, filed on Oct. 10, 2012.
Claims priority of application No. 2011-232282 (JP), filed on Oct. 21, 2011.
Prior Publication US 2017/0134678 A1, May 11, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 5/363 (2011.01); H03M 1/56 (2006.01); H03M 1/08 (2006.01); H03M 1/12 (2006.01); H04N 5/359 (2011.01); H04N 5/378 (2011.01); H04N 5/225 (2006.01); H04N 5/374 (2011.01); H04N 5/3745 (2011.01); H01L 27/146 (2006.01)
CPC H04N 5/363 (2013.01) [H01L 27/14612 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); H03M 1/08 (2013.01); H03M 1/0863 (2013.01); H03M 1/123 (2013.01); H03M 1/56 (2013.01); H04N 5/2253 (2013.01); H04N 5/359 (2013.01); H04N 5/374 (2013.01); H04N 5/378 (2013.01); H04N 5/37457 (2013.01); H01L 27/14618 (2013.01); H01L 2924/0002 (2013.01)] 29 Claims
OG exemplary drawing
1. An imaging device comprising:
a first substrate including:
a pixel array unit including a plurality of pixels coupled to at least one of a floating diffusion, a reset transistor, an amplification transistor, and/or a selection transistor, respective ones of the plurality of pixels configured to receive an incident light and output an analog signal, and including a photoelectric conversion element and a transfer transistor,
a plurality of signal lines, a signal line of the plurality of signal lines being coupled to the plurality of pixels,
a first plurality of via holes disposed along a first side of the pixel array unit, and
a second plurality of via holes disposed along a second side of the pixel array unit, the second side being perpendicular to the first side; and
a second substrate including:
a column circuit including a plurality of comparators and a plurality of counters, and
at least a portion of a control circuit, wherein
at least one of the first plurality of via holes is coupled to one of the plurality of comparators,
the portion of the control circuit is coupled to at least one of the second plurality of via holes, and
the first substrate and the second substrate are bonded together.