US 9,813,631 B2
Image sensor configuration
Jeffrey M. Raynor, Edinburgh (GB)
Assigned to STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED, Marlow (GB)
Filed by STMicroelectronics (Research & Development) Limited, Marlow (GB)
Filed on May 10, 2016, as Appl. No. 15/151,240.
Claims priority of application No. 15202555 (EP), filed on Dec. 23, 2015.
Prior Publication US 2017/0187936 A1, Jun. 29, 2017
Int. Cl. H04N 5/235 (2006.01); H04N 9/04 (2006.01); H01L 27/146 (2006.01)
CPC H04N 5/235 (2013.01) [H01L 27/14609 (2013.01); H01L 27/14643 (2013.01); H04N 5/2353 (2013.01); H04N 9/045 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A device, comprising:
an array of light-sensitive pixels, each pixel of the array including:
a photodiode; and
a plurality of capacitors configured to store charge from the photodiode; and
an address decoder, coupled to the array of light-sensitive pixels, and which, in at least one mode of operation, controls a plurality of portions of the array of light-sensitive pixels to capture respective image exposures, wherein the address decoder comprises a plurality of row decoders, each row decoder associated with a respective row of the array of light-sensitive pixels and including:
a memory configured to store row-decoder enablement information;
enablement circuitry configured to receive a type signal and to generate an enable signal based on the type signal and the stored row-decoder enablement information; and
address circuitry configured to receive a row-address signal and the enable signal, and to selectively enable the respective row of the array of light sensitive pixels based on the row-address signal and the enable signal.