US 9,813,359 B2
Methods and apparatus related to a distributed switch fabric
Gunes Aybay, Los Altos, CA (US)
Assigned to Juniper Networks, Inc., Sunnyvale, CA (US)
Filed by Juniper Networks, Inc., Sunnyvale, CA (US)
Filed on May 10, 2016, as Appl. No. 15/151,071.
Application 15/151,071 is a continuation of application No. 14/610,143, filed on Jan. 30, 2015, granted, now 9,356,885.
Application 14/610,143 is a continuation of application No. 12/607,162, filed on Oct. 28, 2009, granted, now 8,953,603, issued on Oct. 2, 2015.
Prior Publication US 2016/0255019 A1, Sep. 1, 2016
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 12/56 (2006.01); H04L 12/935 (2013.01); H04L 12/54 (2013.01); H04L 12/933 (2013.01); H04L 12/947 (2013.01); H04L 12/741 (2013.01); H04L 12/743 (2013.01); H04L 29/06 (2006.01)
CPC H04L 49/3009 (2013.01) [H04L 12/5601 (2013.01); H04L 45/74 (2013.01); H04L 45/7453 (2013.01); H04L 49/101 (2013.01); H04L 49/1561 (2013.01); H04L 49/1569 (2013.01); H04L 49/1576 (2013.01); H04L 49/25 (2013.01); H04L 49/256 (2013.01); H04L 69/22 (2013.01); H04L 49/1515 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an input port configured to receive, from a first peripheral device, a first data packet including a first data packet header and a second data packet including a second data packet header, the first data packet header and the second data packet header each specifying a common destination address;
a processor operatively coupled to the input port, the processor configured to (1) parse the first data packet header and the second data packet header and (2) append an identifier of one destination edge device to each of the first data packet and the second data packet to define a first appended data packet and a second appended data packet, the identifier of the destination edge device based on the common destination address;
an output port operatively coupled to the processor, the output port configured to send each of the first appended data packet and the second appended data packet to one module associated with a first stage of a switch fabric based on the first data packet header and the second data packet header such that the module associated with the first stage of the switch fabric parses the identifier of the destination edge device of each of the first data packet and the second data packet and sends the first appended data packet and the second appended data packet to one module associated with the second stage of the switch fabric based on the identifier of the destination edge device without performing a calculation to associate the first data packet or the second data packet with the common destination address, the module associated with the first stage of the switch fabric being from a plurality of modules associated with the first stage of the switch fabric, the module associated with the second stage of the switch fabric being from a plurality of modules associated with the second stage of the switch fabric.