US 9,813,227 B2
At-rate SERDES clock data recovery with controllable offset
Jianghui Su, Santa Clara, CA (US)
Assigned to ORACLE INTERNATIONAL CORPORATION, Redwood City, CA (US)
Filed by Oracle International Corporation, Redwood City, CA (US)
Filed on Jan. 18, 2016, as Appl. No. 15/28.
Application 15/000,028 is a continuation in part of application No. 14/146,605, filed on Jan. 2, 2014, granted, now 9,306,732.
Prior Publication US 2016/0241383 A1, Aug. 18, 2016
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 7/00 (2006.01); H04L 7/02 (2006.01); H04L 7/033 (2006.01)
CPC H04L 7/0087 (2013.01) [H04L 7/0033 (2013.01); H04L 7/02 (2013.01); H04L 7/0334 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A system for at-rate clock data recovery comprising:
signal receiver subsystem that operates to receive a data signal from a data channel and to output a channel pulse response signal as a function of sampling the data signal according to a sampling clock phase that is dynamically adjustable according to an advance/retard signal;
an offset circuit that operates to store an advance threshold and a retard threshold, wherein one of the advance threshold or the retard threshold is a negative integer N; and
a voting circuit in communication with the offset circuit that operates to:
generate a plurality of votes each by measuring a pulse signal at a predetermined sample location that corresponds to the sampling clock phase and comparing the measurement to a reference level to generate an early vote when the measured pulse signal at the predetermined sample location compared to the reference level indicates that the sample location precedes a reference-level crossing associated with the predetermined sample location, and to generate a late vote when the measured pulse signal at the predetermined sample location compared to the reference level indicates that the reference-level crossing associated with the predetermined sample location precedes the sample location;
generate the advance/retard signal, the advance/retard signal comprising an advance signal when the generated late votes exceeds the generated early votes by at least the advance threshold, and
the advance/retard signal comprising a retard signal when the generated early votes exceeds the generated late votes by at least the retard threshold; and
feed back the advance/retard signal to the signal receiver subsystem for dynamic adjustment of the sampling clock phase.