US 9,813,188 B2
Transmitting circuit, communication system, and communication method
Yuuki Ogata, Kawasaki (JP); and Yoichi Koyanagi, Yokohama (JP)
Assigned to FUJITSU LIMITED, Kawasaki (JP)
Filed by FUJITSU LIMITED, Kawasaki-shi, Kanagawa (JP)
Filed on Jun. 27, 2014, as Appl. No. 14/318,392.
Claims priority of application No. 2013-155549 (JP), filed on Jul. 26, 2013.
Prior Publication US 2015/0029876 A1, Jan. 29, 2015
Int. Cl. H04L 1/00 (2006.01); H04J 3/04 (2006.01); H04L 25/02 (2006.01); H04L 25/03 (2006.01)
CPC H04L 1/0002 (2013.01) [H04J 3/047 (2013.01); H04L 25/028 (2013.01); H04L 25/03146 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A transmitting circuit comprising:
a multiplexer configured to output a third digital signal obtained by alternately synthesizing a first digital signal of a predetermined cycle length and a predetermined data rate with a second digital signal, shifted by a half of the predetermined cycle length from the first digital signal, of the predetermined cycle length and the predetermined data rate so as to ensure that a data rate of the third digital signal is twice as high as the data rate of the first digital signal;
a first selector configured to output the first digital signal in a first state and output the third digital signal in a second state that is different from the first state;
a second selector configured to output the second digital signal in the first state and output the third digital signal in the second state;
a first driver circuit configured to output a signal corresponding to a signal output from the first selector;
a second driver circuit coupled to the first driver through outputs of the first and second driver circuits and configured to output a signal corresponding to a signal output from the second selector, and
a third selector configured to supply a constant signal that represents 1 or 0 to the multiplexer in the first state, and supply a clock signal to the multiplexer in the second state,
wherein the multiplexer stops outputting the third digital signal when the constant signal is supplied to the multiplexer.