US 9,813,080 B1
Layer specific LDPC decoder
Rino Micheloni, Turate (IT); Alessia Marelli, Merate (IT); Peter Z. Onufryk, Flanders, NJ (US); and Christopher I. W. Norrie, San Jose, CA (US)
Assigned to MICROSEMI SOLUTIONS (U.S.), INC., Aliso Viejo, CA (US)
Filed by MICROSEMI SOLUTIONS (U.S.), INC., Aliso Viejo, CA (US)
Filed on Jun. 23, 2015, as Appl. No. 14/747,042.
Application 14/628,212 is a division of application No. 13/785,848, filed on Mar. 5, 2013, granted, now 8,990,661.
Application 14/747,042 is a continuation in part of application No. 14/628,212, filed on Feb. 21, 2015.
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/1131 (2013.01) [H03M 13/1111 (2013.01)] 33 Claims
OG exemplary drawing
 
1. An apparatus to decode low-density parity check (LDPC) encoded data using a parity check matrix having a plurality of layers, comprising:
a functional adjustment matrix containing functional adjustment parameters, each location in the functional adjustment matrix to provide a functional adjustment for a layer of the plurality of layers and an iteration of a plurality of iterations, the functional adjustment parameters including a first functional adjustment parameter for a first layer and a first iteration and a second functional adjustment parameter for a second layer and the first iteration, wherein the first functional adjustment parameter is different from the second functional adjustment parameter;
a check node processor coupled to the functional adjustment matrix, the check node processor having circuitry to perform check node processing on a plurality of values for each layer of the parity check matrix associated with a codeword utilizing an approximation to belief propagation, the check node processor configured to identify from the functional adjustment matrix a functional adjustment parameter for the particular layer and the particular iteration of the check node processing and configured to apply the identified functional adjustment parameter during the performing check node processing to alter the results of the check node processing;
a variable node processor coupled to the check node processor, the variable node processor having circuitry to perform variable node processing on a plurality of values for each layer of the parity check matrix associated with the codeword; and
a codeword estimate check processor coupled to the variable node processor, the codeword estimate check processor having circuitry to perform a check of an estimate of the codeword to determine if the estimate is valid.