US 9,813,069 B1
Half-rate bang-bang phase detector
Biman Chattopadhyay, Bengaluru (IN); and Ravi Mehta, Bengaluru (IN)
Assigned to SILAB TECH PVT. LTD., Karnataka (IN)
Filed by SILAB TECH PVT. LTD., Bengaluru, Karnataka (IN)
Filed on Oct. 5, 2016, as Appl. No. 15/286,029.
Int. Cl. H03D 3/24 (2006.01); H03L 7/08 (2006.01); H03K 19/21 (2006.01); H03L 7/099 (2006.01); H03L 7/091 (2006.01); H04L 7/033 (2006.01)
CPC H03L 7/0807 (2013.01) [H03K 19/21 (2013.01); H03L 7/091 (2013.01); H03L 7/099 (2013.01); H04L 7/0331 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A phase detector, comprising:
a sampling circuit for sampling a data signal, the sampling circuit including:
a first flip-flop that receives the data signal and a first clock signal, and generates a first sampling signal;
a second flip-flop that receives the data signal and a second clock signal, and generates a second sampling signal;
a third flip-flop that receives the data signal and a third clock signal, and generates a third sampling signal; and
a fourth flip-flop that receives the data signal and a fourth clock signal, and generates a fourth sampling signal, wherein the first and second clock signals, the second and third clock signals, the third and fourth clock signals, and the first and fourth clock signals have a predetermined phase difference therebetween;
a comparison circuit for receiving the first through fourth sampling signals, and generating first through fourth comparison signals, the comparison circuit including:
a first logic gate that receives the first and second sampling signals, compares the first and second sampling signals, and generates the first comparison signal;
a second logic gate that receives the second and third sampling signals, compares the second and third sampling signals, and generates the second comparison signal;
a third logic gate that receives the third and fourth sampling signals, compares the third and fourth sampling signals, and generates the third comparison signal; and
a fourth logic gate that receives the first and fourth sampling signals, compares the first and fourth sampling signals, and generates the fourth comparison signal; and
a resampling circuit for resampling the first through fourth comparison signals and generating first through fourth control signals, the resampling circuit including:
a fifth flip-flop that receives the first comparison signal and the first clock signal, and generates the first control signal;
a sixth flip-flop that receives the second comparison signal and the second clock signal, and generates the second control signal;
a seventh flip-flop that receives the third comparison signal and the third clock signal, and generates the third control signal; and
an eighth flip-flop that receives the fourth comparison signal and the fourth clock signal, and generates the fourth control signal, wherein the first and second control signals, the second and third control signals, the third and fourth control signals, and the first and fourth control signals have the predetermined phase difference therebetween.