US 9,813,062 B2
Finfet based driver circuit
Tsuyoshi Koike, Shiga (JP); Yasuhiro Agata, Osaka (JP); and Yoshinobu Yamagami, Osaka (JP)
Assigned to SOCIONEXT INC., Kanagawa (JP)
Filed by SOCIONEXT INC., Yokohama-shi, Kanagawa (JP)
Filed on Mar. 24, 2016, as Appl. No. 15/80,406.
Application 15/080,406 is a continuation of application No. PCT/JP2014/002281, filed on Apr. 23, 2014.
Claims priority of application No. 2013-201060 (JP), filed on Sep. 27, 2013.
Prior Publication US 2016/0211839 A1, Jul. 21, 2016
Int. Cl. H03K 17/12 (2006.01); H03K 19/017 (2006.01); H03K 19/094 (2006.01); H03K 19/0952 (2006.01); H01L 21/00 (2006.01); H01L 29/00 (2006.01)
CPC H03K 19/01721 (2013.01) [H03K 17/122 (2013.01); H03K 19/094 (2013.01); H01L 21/00 (2013.01); H01L 29/00 (2013.01); H03K 19/0952 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device having a plurality of semiconductor integrated circuits which include a first semiconductor integrated circuit, the first semiconductor integrated circuit being connected to an input node and first and second nodes, wherein
the first semiconductor integrated circuit has a plurality of transistors, each of which has a first channel conductivity type and which are configured as fin transistors having the same gate length and the same gate width, the plurality of transistors comprising:
a first group of transistors provided between the first and second nodes and including n of the transistor(s) where n is an integer equal to or greater than one, the n transistors being connected together in series; and
a second group of transistors provided between the first and second nodes in parallel with the first group of transistors and including m of the transistor(s) where m is an integer equal to or greater than one and not equal to n, the m transistors being connected together in series,
the semiconductor integrated circuit device further having a control transistor whose source or drain is connected to the first or second node and which is connected in series to the first semiconductor integrated circuit,
all of the n transistor(s) in the first group and all of the m transistor(s) in the second group have their gate connected to the input node,
the control transistor is supplied, at its gate, with a mode control signal controlling ON/OFF states of the control transistor.