US 9,813,061 B1
Circuitry for implementing multi-mode redundancy and arithmetic functions
Herman Henry Schmit, Palo Alto, CA (US); and David Lewis, Toronto (CA)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Altera Corporation, San Jose, CA (US)
Filed on May 10, 2016, as Appl. No. 15/150,869.
Application 15/150,869 is a continuation of application No. 14/499,006, filed on Sep. 26, 2014, granted, now 9,362,913.
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/003 (2006.01); G06F 7/501 (2006.01); H03K 19/23 (2006.01); H03K 19/007 (2006.01); G06F 11/20 (2006.01)
CPC H03K 19/00392 (2013.01) [G06F 7/501 (2013.01); G06F 11/2089 (2013.01); G06F 11/2094 (2013.01); H03K 19/0075 (2013.01); H03K 19/00369 (2013.01); H03K 19/23 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first logic circuit;
a second logic circuit; and
an adder circuit that receives signals from both the first and second logic circuits in a first mode and that receives signals from only the second logic circuit in a second mode that is different than the first mode, wherein the second mode implements a majority voting function.