US 9,813,057 B2
Sampling circuit and sampling method
Ming-Cheng Chiang, Hsinchu (TW); and Li-Lung Kao, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Mar. 1, 2017, as Appl. No. 15/446,652.
Application 15/446,652 is a division of application No. 14/957,327, filed on Dec. 2, 2015, granted, now 9,621,157.
Prior Publication US 2017/0179949 A1, Jun. 22, 2017
Int. Cl. H03K 17/687 (2006.01)
CPC H03K 17/6872 (2013.01) 13 Claims
OG exemplary drawing
 
1. A sampling circuit for sampling an input voltage and generating an output voltage, comprising:
a switch, switching off in a first switching state and switching on to make the output voltage equal to the input voltage in a second switching state, wherein the switch has a control terminal;
a capacitor, coupled to the switch;
a first switch group, coupled to the capacitor;
a second switch group, coupled to the capacitor; and
a voltage buffer, coupled to the switch, the capacitor, the first switch group and the second switch group, having large input impedance, wherein an input of the voltage buffer receives the input voltage and an output of the voltage buffer provides a voltage which is equal or close to the input voltage;
wherein, in the first switching state when the first switch group switches on and the second switch group switches off, the capacitor is charged to generate a voltage difference across the two terminals thereof, and in the second switching state when the first switch group switches off and the second switch group switches on, the input voltage is coupled to the control terminal of the switch through the voltage buffer and the capacitor so that a voltage at the control terminal is substantially equal or close to the input voltage plus the voltage difference across the capacitor.