US 9,813,056 B2
Active device divider circuit with adjustable IQ
Bin Shao, Shanghai (CN); Danzhu Lu, Shanghai (CN); and Junxiao Chen, Shanghai (CN)
Assigned to Analog Devices Global, Hamilton (BM)
Filed by Analog Devices Global, Hamilton (BM)
Filed on Oct. 16, 2015, as Appl. No. 14/885,601.
Application 14/885,601 is a continuation of application No. PCT/CN2015/090143, filed on Sep. 21, 2015.
Prior Publication US 2017/0085263 A1, Mar. 23, 2017
Int. Cl. H03K 17/10 (2006.01); H03K 17/06 (2006.01); H03K 17/687 (2006.01); H03K 17/22 (2006.01)
CPC H03K 17/6871 (2013.01) [H03K 17/223 (2013.01)] 20 Claims
OG exemplary drawing
1. A programmable quiescent current reference circuit comprising:
a first node;
a second node;
a third node;
multiple transistor load devices coupled in series between the first node and the second node;
multiple first switches, each associated with a different transistor load device to selectably bypass its associated transistor load device; and
second switch circuitry configured to selectably couple a first terminal of a selected transistor load device, from among the multiple transistor load devices, to the third node, while de-coupling the other transistor load devices, from among the multiple transistor load devices, from the third node.