US 9,813,055 B2
Gate driver that drives with a sequence of gate resistances
Andreas Laschek-Enders, Bensheim (DE)
Assigned to IXYS Corporation, Milpitas, CA (US)
Filed by IXYS Corporation, Milpitas, CA (US)
Filed on Apr. 1, 2016, as Appl. No. 15/88,124.
Prior Publication US 2017/0288661 A1, Oct. 5, 2017
Int. Cl. H03K 3/00 (2006.01); H03K 17/567 (2006.01); H01L 29/739 (2006.01); H01L 27/06 (2006.01); H03K 17/687 (2006.01); H03K 5/14 (2014.01); H03K 5/00 (2006.01)
CPC H03K 17/567 (2013.01) [H01L 27/0629 (2013.01); H01L 27/0647 (2013.01); H01L 29/7393 (2013.01); H03K 5/14 (2013.01); H03K 17/687 (2013.01); H03K 2005/00058 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first power transistor gate driver having an output lead;
a second power transistor gate driver having an output lead;
a third power transistor gate driver having an output lead;
a signal node, wherein a gate driver control signal is present on the signal node, wherein the gate driver control signal has a rising edge that is followed by a falling edge; and
a driver control circuit that receives the gate driver control signal and in response to the rising edge enables the first, second and third power transistor gate drivers sequentially in a first predetermined order, wherein each of the three power transistor gate drivers when enabled in response to the rising edge drives a high voltage onto its output lead, wherein the driver control circuit in response to the falling edge enables the first, second and third power transistor gate drivers sequentially in a second predetermined order, and wherein each of the three power transistor gate drivers when enabled in response to the falling edge drives a low voltage onto its output lead when it is enabled, wherein the driver control circuit comprises:
a first delay line having a plurality of nodes;
a second delay line having a plurality of nodes; and
an amount of digital logic coupled to receive signals from the plurality of nodes of the first delay line and coupled to receive signals from the plurality of nodes of the second delay line, wherein the amount of digital logic supplies a first enable signal to the first power transistor gate driver, wherein the amount of digital logic supplies a second enable signal to the second power transistor gate driver, and wherein the amount of digital logic supplies a third enable signal to the third power transistor gate driver.