US 9,813,048 B2
Electronic comparison systems
Kaushik Roy, West Lafayette, IN (US); and Mrigank Sharad, West Lafayette, IN (US)
Assigned to Purdue Research Foundation, West Lafayette, IN (US)
Filed by Purdue Research Foundation, West Lafayette, IN (US)
Filed on Oct. 26, 2016, as Appl. No. 15/334,649.
Application 15/334,649 is a division of application No. 14/287,701, filed on May 27, 2014, granted, now 9,489,618.
Prior Publication US 2017/0047913 A1, Feb. 16, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/356 (2006.01); G06N 3/063 (2006.01); G11C 11/16 (2006.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01); G11C 15/02 (2006.01); G11C 15/04 (2006.01); H03M 1/46 (2006.01); H03M 1/38 (2006.01)
CPC H03K 3/356104 (2013.01) [G06N 3/063 (2013.01); G11C 11/16 (2013.01); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1693 (2013.01); G11C 11/54 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 15/02 (2013.01); G11C 15/046 (2013.01); H03M 1/46 (2013.01); H03M 1/38 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An electronic comparison system, comprising:
a plurality of input stages, each configured to successively provide bits of a respective code word, starting with a most-significant bit thereof;
a plurality of one-shots connected to respective ones of the input stages to successively receive the bits of the respective code words, wherein each one-shot is configured to successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then to provide a second, different bit value;
an enable circuit connected to the outputs of the one-shots and configured to provide the enable signal if at least one of the one-shots is providing the first bit value.