US 9,813,047 B2
Standby mode state retention logic circuits
Senthilkumar Jayapal, Singapore (SG)
Assigned to MediaTek Singapore Pte. Ltd., Singapore (SG)
Filed by MediaTek Singapore Pte. Ltd., Singapore (SG)
Filed on Dec. 30, 2015, as Appl. No. 14/984,020.
Claims priority of provisional application 62/146,537, filed on Apr. 13, 2015.
Prior Publication US 2016/0301396 A1, Oct. 13, 2016
Int. Cl. H03K 3/356 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01)
CPC H03K 3/356008 (2013.01) [H03K 3/012 (2013.01); H03K 3/0375 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A state retention logic circuit comprising:
a first gate coupled to a clock signal input node and a retention signal input node, and outputting a second clock signal;
a first inverter coupled to the first gate, and outputting a first clock signal;
a second inverter coupled to a reset signal input node;
a third inverter coupled to the second inverter, and outputting a reset signal;
a pullup P-channel transistor that has a source, a gate and a drain, wherein the source is coupled to a supply voltage node for receiving a first supply voltage, the gate is coupled to the retention signal input node, and the drain is coupled to the reset signal input node;
a first latch receiving a data signal from a first data input node, wherein the first latch is clocked by the first clock signal and the second clock signal; and
a second latch coupled to the first latch, and outputting a data signal, wherein the second latch is clocked by the first clock signal and the second clock signal, and the second latch further comprises:
a second gate having a first input lead, a second input lead, and an output lead; and
a tri-statable feedback element having an input lead and an output lead, wherein the input lead of the tri-statable feedback element is coupled to the output lead of the second gate, the output lead of the tri-statable feedback element is coupled to the first input lead of the second gate, the tri-statable feedback element is enabled and disabled by the first clock signal and the second clock signal,
wherein the first inverter, the third inverter, the second gate of the second latch, and the tri-statable feedback element of the second latch are powered by a second supply voltage, and wherein the first latch, the first gate and the second inverter are powered by the first supply voltage.