US 9,813,046 B2
Embedded buffer circuit compensation scheme for integrated circuits
Sameer Shekhar, Poartland, OR (US); Amit K. Jain, Portland, OR (US); and Pooja Nukala, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 31, 2016, as Appl. No. 15/87,250.
Prior Publication US 2017/0288647 A1, Oct. 5, 2017
Int. Cl. H03K 3/011 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H05K 1/18 (2006.01); H01L 25/065 (2006.01)
CPC H03K 3/011 (2013.01) [H01L 23/49838 (2013.01); H01L 24/17 (2013.01); H01L 25/0655 (2013.01); H05K 1/181 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19101 (2013.01); H05K 2201/10166 (2013.01); H05K 2201/10234 (2013.01); H05K 2201/10318 (2013.01); H05K 2201/10378 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a package substrate including conductive contacts, conductive paths coupled to the conductive contacts, and a resistor embedded in the package substrate, and
a die including buffer circuits and a calibration module coupled to the buffer circuits and the resistor, the buffer circuits including output nodes coupled to the conductive contacts through the conductive paths, the calibration module configured to perform a calibration operation to adjust resistances of the buffer circuits based on a value of a voltage at a terminal of the resistor during the calibration operation.