US 9,813,023 B2
Common-mode impedance network for reducing sensitivity in oscillators
Aaron J. Caffee, Scappoose, OR (US)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on Dec. 16, 2015, as Appl. No. 14/970,865.
Prior Publication US 2017/0179881 A1, Jun. 22, 2017
Int. Cl. H03B 5/08 (2006.01); H03L 1/00 (2006.01); H03L 7/081 (2006.01); H03B 5/12 (2006.01); H03L 1/02 (2006.01)
CPC H03B 5/08 (2013.01) [H03B 5/12 (2013.01); H03L 1/00 (2013.01); H03L 1/026 (2013.01); H03L 7/0812 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An oscillator comprising:
a planar conductive loop comprising a first terminal, a second terminal, and a center tap, the planar conductive loop being formed from a first conductive layer above an integrated circuit substrate; and
a planar conductive structure extending from a first point proximate to the center tap and extending along a line of symmetry of the planar conductive loop to a second point proximate to the first terminal and the second terminal,
wherein the center tap is capacitively coupled to an AC ground node using the planar conductive structure, the planar conductive structure is capacitively coupled to the center tap of the planar conductive loop, and the planar conductive structure is directly coupled to the AC ground node.