US 9,812,987 B2
Topology for controlled power switch module
Jean-Marc Cyr, Candiac (CA); Maalainine El Yacoubi, Montreal (CA); Mohammed Amar, Montreal (CA); and Pascal Fleury, Sainte-Madeleine (CA)
Assigned to TM4 INC., Boucherville, Quebec (CA)
Appl. No. 14/429,200
Filed by TM4 Inc., Boucherville (CA)
PCT Filed Sep. 20, 2013, PCT No. PCT/CA2013/000805
§ 371(c)(1), (2) Date Mar. 18, 2015,
PCT Pub. No. WO2014/043795, PCT Pub. Date Mar. 27, 2014.
Claims priority of provisional application 61/704,807, filed on Sep. 24, 2012.
Prior Publication US 2015/0222202 A1, Aug. 6, 2015
Int. Cl. H02M 7/537 (2006.01); H03K 17/082 (2006.01); H02M 7/00 (2006.01); H03K 17/567 (2006.01)
CPC H02M 7/537 (2013.01) [H02M 7/003 (2013.01); H03K 17/0828 (2013.01); H03K 17/567 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A power switch module, comprising:
a top power switch including a gate, a collector and an emitter, the top power switch configured to be controlled by a top gate driver circuit;
a bottom power switch including a gate, a collector and an emitter, the bottom power switch configured to be controlled by a bottom gate driver circuit;
a top collector trace connected to the collector of the top power switch;
a bottom collector trace connected to the collector of the bottom power switch;
a top emitter trace connected to the emitter of the top power switch;
a bottom emitter trace connected to the emitter of the bottom power switch;
a −Vbus tab connected to the bottom emitter trace;
a +Vbus tab connected to the top collector trace;
at least one phase tab connected to either the bottom collector trace and the top emitter trace; and
an interconnection of the top emitter trace to the bottom collector trace defining a parasitic emitter inductance having such a value that a voltage generated thereacross, during dI/dt, is injected in the top gate driver circuit to create a positive voltage at the emitter of the top power switch to slow down a slope of a gate-emitter voltage (Vge) at turn on.