US 9,812,962 B2
Method and system for increasing efficiency and controlling slew rate in DC-DC converters
Alexandro Leoncini, Raleigh, NC (US); Edward Kohler, Boston, MA (US); and Timmy Lok, Palm Bay, FL (US)
Assigned to INTERSIL AMERICAS LLC, Milpitas, CA (US)
Filed by Intersil Americas LLC, Milpitas, CA (US)
Filed on Apr. 5, 2016, as Appl. No. 15/90,659.
Claims priority of provisional application 62/234,707, filed on Sep. 30, 2015.
Prior Publication US 2017/0093283 A1, Mar. 30, 2017
Int. Cl. H03B 1/00 (2006.01); H02M 3/158 (2006.01); H03K 19/0185 (2006.01); H03K 5/04 (2006.01); H03K 5/24 (2006.01); G11C 5/14 (2006.01); H02M 1/38 (2007.01); H02M 1/44 (2007.01); H03K 17/16 (2006.01); H02M 1/00 (2006.01)
CPC H02M 3/158 (2013.01) [G11C 5/147 (2013.01); H02M 1/38 (2013.01); H02M 1/44 (2013.01); H03K 5/04 (2013.01); H03K 5/24 (2013.01); H03K 17/163 (2013.01); H03K 19/018507 (2013.01); H02M 2001/0009 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first driver having first and second inputs, and first and second outputs;
wherein the first output is configured to be coupled to a first terminal of a first slew resistor having a second terminal coupled to an input of a first power transistor;
wherein the second output is configured to be coupled to a third terminal of a second slew resistor having a fourth terminal coupled to the input of the first power transistor;
a second driver having third and fourth inputs and third and fourth outputs;
wherein the third output is configured to be coupled to a fifth terminal of a third slew resistor also having a sixth terminal coupled to an input of a second power transistor;
wherein the fourth output is configured to be coupled to a seventh terminal of a fourth slew resistor also having an eighth terminal coupled to an input of the second power transistor;
wherein the first output is coupled to the fourth input;
wherein the third output is coupled to the second input;
wherein the first input is configured to receive an enable signal;
wherein the third input is configured to receive a complementary enable signal;
wherein the first output is configured to directly sense a voltage at the input of the first power transistor upon the first power transistor beginning to be turned off; and
wherein the third output is configured to directly sense a voltage at the input of the second power transistor upon the second power transistor beginning to be turned off.