US 9,812,958 B2
Voltage regulator with improved overshoot and undershoot voltage compensation
Fumiyasu Utsunomiya, Chiba (JP)
Assigned to SII SEMICONDUCTOR CORPORATION, Chiba (JP)
Filed by Seiko Instruments Inc., Chiba-shi, Chiba (JP)
Filed on Mar. 4, 2014, as Appl. No. 14/196,723.
Claims priority of application No. 2013-044169 (JP), filed on Mar. 6, 2013; and application No. 2014-002972 (JP), filed on Jan. 10, 2014.
Prior Publication US 2014/0253076 A1, Sep. 11, 2014
Int. Cl. G05F 1/565 (2006.01); G05F 1/00 (2006.01); G05F 1/44 (2006.01); H02M 3/158 (2006.01)
CPC H02M 3/158 (2013.01) [G05F 1/565 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A voltage regulator, comprising:
an error amplifier having an error output node having a voltage proportional to a difference between an inverting input and a non-inverting input of the error amplifier that is coupled to a first voltage reference;
an I-V converter circuit that comprises a first transistor having a gate coupled to the error output node of the error amplifier, and a second transistor having a gate and drain coupled to a drain of the first transistor and a drive output node;
an output transistor having a gate terminal coupled to the drive output node of the I-V converter circuit and an output terminal configured to output a voltage of the voltage regulator for driving a load, wherein the error output node and the drive output node are different; and
a third transistor that includes a gate configured to receive a second reference voltage from a reference voltage generator circuit that is separate from the I-V converter circuit, a source coupled to the output terminal, and a drain that is connected to an internal node of the I-V converter circuit,
wherein when the output voltage deviates from the second reference voltage by more than a predetermined threshold, current flows directly between the third transistor and the internal node of the I-V converter circuit to thereby control a current of the output transistor,
wherein the value of the second reference voltage received at the gate of the third transistor is set to be less than, equal to, or greater than the first voltage reference.