US 9,812,945 B2
Circuit structure for enhancing EFT immunity of primary side converter
Haisong Li, Jiangsu (CN); Ping Tao, Jiangsu (CN); Changshen Zhao, Jiangsu (CN); and Yangbo Yi, Jiangsu (CN)
Assigned to Wuxi Chipown Micro-Electronics, Limited, (CN)
Filed by Wuxi Chipown Micro-electronics Limited, Wuxi, Jiangsu (CN)
Filed on Oct. 12, 2015, as Appl. No. 14/880,943.
Claims priority of application No. 2015 1 0243735 (CN), filed on May 13, 2015.
Prior Publication US 2016/0336851 A1, Nov. 17, 2016
Int. Cl. H02M 3/335 (2006.01); H02M 1/32 (2007.01); H02M 1/44 (2007.01); H02M 1/00 (2006.01)
CPC H02M 1/32 (2013.01) [H02M 1/44 (2013.01); H02M 3/335 (2013.01); H02M 3/33507 (2013.01); H02M 3/33523 (2013.01); H02M 2001/0009 (2013.01); H02M 2001/0035 (2013.01); Y02B 70/16 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A circuit structure for enhancing EFT immunity of primary side converter, comprising:
a power ground and a feedback voltage detecting block (103), a feedback current detecting block (106), a controller (104), a PWM driving block (105), a HV start-up block (102), a start-up unit (107), a circuit for enhancing EFT immunity of primary side converter, a power MOS transistor (109), and an OR gate (108) configured to perform a logical operation OR of an off-time calculated theoretically and an off-time output by an off-time control block (203);
wherein, the circuit for enhancing EFT immunity of primary side converter comprises a VSENSE abrupt change detecting block (201), the off-time control block (203), an OCP threshold value adjusting block (204) and a timing block (202);
wherein, an input of the VSENSE abrupt change detecting block (201) is connected with a feedback voltage VSENSE terminal, outputs of the VSENSE abrupt change detecting block (201) are respectively connected with an input of the start-up unit (107), an input of the OCP threshold value adjusting block (204) and an input of the timing block (202); inputs of the off-time control block (203) are connected with outputs of the timing block (202), and an output of the off-time control block (203) is connected with an input of the OR gate (108); another input of the OCP threshold value adjusting block (204) is connected with an output of the controller (104), and an output of the OCP threshold value adjusting block (204) is connected with an input of the feedback current detecting block (106);
an input of the feedback voltage detecting block (103) is connected with the VSENSE terminal, and an output of the feedback voltage detecting block (103) is connected with an input of the controller (104);
outputs of the controller (104) are respectively connected with an input of the OCP threshold value adjusting block (204) and another input of the OR gate (108);
an output of the OR gate (108) is connected with an input of the PWM driver (105);
an output of the PWM driver (105) is connected with an input of the power MOS transistor(109);
the drain of power MOS transistor (109) is connected with the HV start-up block (102) and a high voltage port SW; the source of power MOS transistor (109) is connected with the feedback current detecting block (106) and a current feedback port ISENSE;
the feedback current detecting block (106) is also connected with the OCP threshold value adjusting block (204), and a current feedback port ISENSE;
the HV start-up block (102) is respectively connected with the high voltage port SW and a power port VDD;
the off-time control block (203) comprises an arithmetic unit (2031), a logic unit (2033), a maximum off-time selecting unit (2034) and an off-time timing and comparing unit (2032); an output of the arithmetic unit (2031) is connected with an input of the off-time timing and comparing unit (2032); an output of the logic unit (2033) is connected with an input of the maximum off-time selecting unit (2034); an output of the maximum off-time selecting unit (2034) is connected with another input of the off-time timing and comparing unit (2032);
the off-time timing and comparing unit (2032) is configured to select a minor value from an off-time output by the arithmetic unit (2031) and maximum off-time output by the maximum off-time selecting unit (2034); and the minor value is selected to be output signal of the off-time control block (203).