| US 9,812,942 B2 | ||
| Distributed driving system | ||
| Tetsuo Sato, San Jose, CA (US); Ryotaro Kudo, Takasaki (JP); Hideo Ishii, Takasaki (JP); and Kenichi Nakano, Takasaki (JP) | ||
| Assigned to Renesas Electronics America Inc., Santa Clara, CA (US) | ||
| Filed by Tetsuo Sato, San Jose, CA (US); Ryotaro Kudo, Takasaki (JP); Hideo Ishii, Takasaki (JP); and Kenichi Nakano, Takasaki (JP) | ||
| Filed on Jan. 10, 2012, as Appl. No. 13/347,197. | ||
| Prior Publication US 2013/0176015 A1, Jul. 11, 2013 | ||
| Int. Cl. G05F 1/00 (2006.01); H02M 1/088 (2006.01); H02M 3/158 (2006.01); H02M 1/00 (2006.01) | ||
| CPC H02M 1/088 (2013.01) [H02M 3/158 (2013.01); H02M 2001/0054 (2013.01); Y02B 70/1491 (2013.01)] | 13 Claims |
| 1. A DC-DC convertor comprising:
an inductor coupled to an output node;
a first circuit for transmitting current to the output node via the inductor during a pulse of a pulse width modulation (PWM)
signal, wherein the first circuit comprises a first transistor for transmitting current to the output node via the inductor
during the pulse of the PWM signal;
a current detector circuit for generating a signal corresponding to current flow through the first circuit during the pulse
of the PWM signal;
a second circuit for transmitting current to the output node via the inductor, wherein the second circuit comprises a plurality
of second transistors that vary in size, wherein the plurality of second transistors are coupled in parallel;
a third circuit for generating a multibit signal based on the signal generated by the current detector circuit, wherein each
bit of the multibit signal controls a respective one of the second transistors.
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