US 9,812,611 B2
Nitride semiconductor ultraviolet light-emitting element and nitride semiconductor ultraviolet light-emitting device
Akira Hirano, Aichi (JP); and Masamichi Ippommatsu, Aichi (JP)
Assigned to Soko Kagaku Co., Ltd., Ishikawa (JP)
Appl. No. 15/27,106
Filed by Soko Kagaku Co., Ltd., Ishikawa (JP)
PCT Filed Apr. 3, 2015, PCT No. PCT/JP2015/060588
§ 371(c)(1), (2) Date Apr. 4, 2016,
PCT Pub. No. WO2016/157518, PCT Pub. Date Oct. 6, 2016.
Prior Publication US 2017/0263817 A1, Sep. 14, 2017
Int. Cl. H01L 33/24 (2010.01); H01L 33/44 (2010.01); H01L 33/32 (2010.01); H01L 33/46 (2010.01); H01L 33/38 (2010.01)
CPC H01L 33/24 (2013.01) [H01L 33/32 (2013.01); H01L 33/387 (2013.01); H01L 33/44 (2013.01); H01L 33/46 (2013.01); H01L 2933/0016 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A nitride semiconductor ultraviolet light-emitting element comprising:
a semiconductor laminated portion including, in a laminated manner, a first semiconductor layer having one or more n-type AlGaN-based semiconductor layers, an active layer having one or more AlGaN-based semiconductor layers having an AlN mole fraction of zero or more, and a second semiconductor layer having one or more p-type AlGaN-based semiconductor layers;
an n electrode including one or more metal layers;
a p electrode including one or more metal layers;
a protective insulating film; and
a first plated electrode which is in contact with an exposed surface of the p electrode which is not covered with the protective insulating film, wherein
referring to a region that the one nitride semiconductor ultraviolet light-emitting element is formed in a plane parallel to a surface of the semiconductor laminated portion as an element region, the semiconductor laminated portion includes the active layer and the second semiconductor layer laminated on the first semiconductor layer in a first region which is a part of the element region, and does not include the active layer and the second semiconductor layer laminated on the first semiconductor layer in a second region in the element region other than the first region,
the first region has a recess surrounding the second region from three directions in planarly-viewed shape,
the second region continuously has a recessed region surrounded by the recess of the first region, and a periphery region other than the recessed region,
the n electrode is formed on the first semiconductor layer in the second region and covers the recessed region and the periphery region,
the p electrode is formed on an uppermost surface of the second semiconductor layer,
the protective insulating film covers at least a whole outer side surface of the semiconductor laminated portion in the first region, an upper surface of the first semiconductor layer provided between the first region and the n electrode, and an upper surface and a side surface of an outer edge portion of the n electrode including a portion at least facing the first region, and does not cover and exposes at least one part of a surface of the n electrode and at least one part of a surface of the p electrode, and
the first plated electrode is composed of copper or alloy containing copper as a main component, formed by wet plating method, spaced apart from the exposed surface of the n electrode which is not covered with the protective insulating film, and covers a whole upper surface of the first region including the exposed surface of the p electrode, the whole outer side surface of the first region covered with the protective insulating film, and a boundary region which is a part in the second region and is in contact with the first region.