US 9,812,586 B2
Transistor with curved active layer
Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi-shi, Kanagawa-ken (JP)
Filed on Oct. 20, 2014, as Appl. No. 14/518,237.
Claims priority of application No. 2013-219046 (JP), filed on Oct. 22, 2013.
Prior Publication US 2015/0108552 A1, Apr. 23, 2015
Int. Cl. H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 29/42384 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78693 (2013.01); H01L 2029/42388 (2013.01)] 25 Claims
OG exemplary drawing
 
21. A semiconductor device comprising:
a semiconductor layer over an insulating surface;
source and drain electrode layers electrically connected to the semiconductor layer;
a gate electrode layer overlapping with the semiconductor layer with a gate insulating layer therebetween,
wherein:
the semiconductor layer is in contact with the gate insulating layer,
in a cross section in a channel width direction, the semiconductor layer comprises a first region at one side portion of the semiconductor layer, a second region at an upper portion of the semiconductor layer, and a third region at the other side portion of the semiconductor layer,
one end portion of the first region is in contact with the insulating surface,
one end portion of the third region is in contact with the insulating surface,
end portions of the second region are in contact with the other end portion of the first region and the other end portion of the third region, respectively,
in the first region, a first interface with the gate insulating layer is concave,
in the second region, a second interface with the gate insulating layer is convex, and
in the third region, a third interface with the gate insulating layer is concave.