US 9,812,573 B1
Semiconductor structure including a transistor having stress creating regions and method for the formation thereof
Arkadiusz Malinowski, Dresden (DE); Chung Foong Tan, Dresden (DE); Nicolas Sassiat, Dresden (DE); and Maciej Wiatr, Dresden (DE)
Assigned to GLOBALFOUNDRIES Inc., Grand Cayman (KY)
Filed by GLOBALFOUNDRIES Inc., Grand Cayman (KY)
Filed on May 13, 2016, as Appl. No. 15/153,831.
Int. Cl. H01L 29/78 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 29/165 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01)
CPC H01L 29/7848 (2013.01) [H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/823425 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a semiconductor structure, comprising:
a substrate comprising a first semiconductor material and having a planar upper surface;
a gate structure formed over said substrate; and
a sidewall spacer formed adjacent said gate structure, wherein a first upper surface portion of said planar upper surface is covered by said gate structure and said sidewall spacer, and wherein a second upper surface portion of said planar upper surface is exposed;
performing a substantially isotropic first etch process on said exposed second upper surface portion to remove a first portion of said first semiconductor material, wherein an undercut is formed below said sidewall spacer during said first etch process;
after performing said first etch process, performing an anisotropic second etch process to remove a second portion of said first semiconductor material, wherein, during said second etch process, an etch rate of said first semiconductor material in a thickness direction of said substrate is greater than an etch rate of said first semiconductor material in a horizontal direction of said substrate that is perpendicular to said thickness direction; and
performing a crystallographic third etch process to remove a third portion of said first semiconductor material, wherein, during said third etch process, an etch rate of said first semiconductor material in a first crystal direction is greater than an etch rate of said first semiconductor material in a second crystal direction;
wherein said first, second and third etch processes form a source-side recess and a drain-side recess adjacent said gate structure.