US 9,812,567 B1
Precise control of vertical transistor gate length
Veeraraghavan S. Basker, Schenectady, NY (US); Kangguo Cheng, Schenectady, NY (US); Theodorus E. Standaert, Clifton Park, NY (US); and Junli Wang, Slingerlands, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on May 5, 2016, as Appl. No. 15/147,194.
Int. Cl. H01L 21/308 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01); H01L 21/3065 (2006.01); H01L 21/762 (2006.01); H01L 21/266 (2006.01)
CPC H01L 29/7827 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/3081 (2013.01); H01L 21/31111 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/42376 (2013.01); H01L 29/6656 (2013.01); H01L 29/66553 (2013.01); H01L 29/66666 (2013.01); H01L 21/266 (2013.01); H01L 21/3065 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method for forming a transistor, comprising:
forming a channel fin on a bottom source/drain region;
forming a dielectric fill around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin;
forming spacers in the gap;
etching away the dielectric fill; and
forming a gate stack on sidewalls of the channel fin directly underneath the spacers.