US 9,812,565 B2
N-channel double diffusion MOS transistor with p-type buried layer underneath n-type drift and drain layers, and semiconductor composite device
Kensuke Sawase, Kyoto (JP); and Motohiro Toyonaga, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Oct. 13, 2015, as Appl. No. 14/882,411.
Application 14/882,411 is a continuation of application No. 14/158,707, filed on Jan. 17, 2014, granted, now 9,190,513.
Claims priority of application No. 2013-012276 (JP), filed on Jan. 25, 2013.
Prior Publication US 2016/0035885 A1, Feb. 4, 2016
Int. Cl. H01L 29/78 (2006.01); H01L 27/06 (2006.01); H01L 29/10 (2006.01); H01L 21/8249 (2006.01); H01L 49/02 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7816 (2013.01) [H01L 21/8249 (2013.01); H01L 27/0623 (2013.01); H01L 27/0635 (2013.01); H01L 27/0922 (2013.01); H01L 28/10 (2013.01); H01L 28/40 (2013.01); H01L 29/0865 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/7825 (2013.01); H01L 29/7833 (2013.01); H01L 21/823814 (2013.01); H01L 21/823892 (2013.01); H01L 29/665 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An n-channel double diffusion MOS transistor, comprising:
a p-type layer;
an n-type buried layer provided in the p-type layer;
a p-type body layer provided in a surface portion of the p-type layer;
an n-type source layer provided in the p-type body layer and defining a double diffusion structure together with the p-type body layer;
an n-type drift layer provided in a surface portion of the p-type layer in spaced relation from the p-type body layer to define a channel region between the n-type source layer and the n-type drift layer;
an n-type drain layer provided in a surface portion of the p-type layer in spaced relation from the channel region and in contact with the n-type drift layer;
a p-type buried layer buried in the p-type layer between the n-type drift layer and the n-type buried layer and provided in a region including regions directly under the n-type drift layer and the n-type drain layer, the p-type buried layer being absent from a region present under the p-type body layer, the p-type buried layer having a lower impurity concentration than the n-type buried layer, the p-type buried layer being in contact with an upper surface of the n-type buried layer;
a gate insulation film provided in a surface of the p-type layer on the channel region; and
a gate electrode provided in opposed relation to the channel region with intervention of the gate insulation film,
wherein an upper surface of the p-type buried layer is spaced from the n-type drift layer, and the p-type layer is partly present between the p-type buried layer and the n-type drift layer such that the p-type layer separates the n-type drift layer and the p-type buried layer, whereby the n-type drift layer is not in contact with the p-type buried layer.
 
8. An n-channel double diffusion MOS transistor, comprising:
a p-type layer;
an n-type buried layer provided in the p-type layer;
a p-type body layer provided in a surface portion of the p-type layer;
an n-type source layer provided in the p-type body layer and defining a double diffusion structure together with the p-type body layer;
an n-type drift layer provided in a surface portion of the p-type layer in spaced relation from the p-type body layer to define a channel region between the n-type source layer and the n-type drift layer;
an n-type drain layer provided in a surface portion of the p-type layer in spaced relation from the channel region and in contact with the n-type drift layer;
a p-type buried layer buried in the p-type layer between the n-type drift layer and the n-type buried layer and provided in a region including regions directly under the n-type drift layer and the n-type drain layer, the p-type buried layer being absent from a region present under the channel region, the p-type buried layer having a lower impurity concentration than the n-type buried layer, the p-type buried layer being in contact with an upper surface of the n-type buried layer;
a gate insulation film provided in a surface of the p-type layer on the channel region; and
a gate electrode provided in opposed relation to the channel region with intervention of the gate insulation film,
wherein an upper surface of the p-type buried layer is spaced from the n-type drift layer, and the p-type layer is partly present between the p-type buried layer and the n-type drift layer such that the p-type layer separates the n-type drift layer and the p-type buried layer, whereby the n-type drift layer is not in contact with the p-type buried layer.