US 9,812,561 B2
Semiconductor device manufacturing method, including substrate thinning and ion implanting
Takashi Yoshimura, Matsumoto (JP); Hidenao Kuribayashi, Matsumoto (JP); Yuichi Onozawa, Matsumoto (JP); Hayato Nakano, Kofu (JP); and Daisuke Ozaki, Okaya (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kawasaki-Shi (JP)
Filed by FUJI ELECTRIC CO., LTD., Kawasaki-shi (JP)
Filed on Mar. 15, 2016, as Appl. No. 15/70,429.
Application 15/070,429 is a division of application No. 14/079,072, filed on Nov. 13, 2013, granted, now 9,324,847.
Application 14/079,072 is a continuation of application No. PCT/JP2012/062875, filed on May 18, 2012.
Claims priority of application No. 2011-111709 (JP), filed on May 18, 2011.
Prior Publication US 2016/0197170 A1, Jul. 7, 2016
Int. Cl. H01L 21/332 (2006.01); H01L 29/739 (2006.01); H01L 29/08 (2006.01); H01L 29/36 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 21/324 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/167 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/7397 (2013.01) [H01L 21/26513 (2013.01); H01L 21/2855 (2013.01); H01L 21/324 (2013.01); H01L 29/0615 (2013.01); H01L 29/0619 (2013.01); H01L 29/0804 (2013.01); H01L 29/0821 (2013.01); H01L 29/0834 (2013.01); H01L 29/1004 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01); H01L 29/36 (2013.01); H01L 29/4236 (2013.01); H01L 29/66348 (2013.01); H01L 29/7395 (2013.01); H01L 29/0847 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device including a first conductivity type drift layer formed of a first conductivity type semiconductor substrate, MOS gate structure formed of at least a gate electrode, a gate dielectric film, and the first conductivity type semiconductor substrate provided on one main surface side of the first conductivity type semiconductor substrate, a second conductivity type collector layer provided on the other main surface of the first conductivity type semiconductor substrate, a first conductivity type field-stop layer provided between the first conductivity type drift layer and second conductivity type collector layer and having an impurity concentration higher than that of the first conductivity type drift layer, and a first conductivity type buffer layer provided between the first conductivity type field-stop layer and second conductivity type collector layer and having an impurity concentration higher than that of the first conductivity type field-stop layer, the manufacturing method comprising:
a MOS gate structure formation step of forming the MOS gate structure on the one main surface side of the first conductivity type semiconductor substrate;
a substrate thinning step of grinding the other main surface of the first conductivity type semiconductor substrate to reduce the first conductivity type semiconductor substrate to a predetermined thickness;
an implantation step of ion implanting dopants into the ground surface of the first conductivity type semiconductor substrate in order to form each of the first conductivity type field-stop layer, first conductivity type buffer layer, and second conductivity type collector layer;
an activation step of carrying out heat treatment for simultaneously electrically activating a plurality of dopants ion implanted into the ground surface of the first conductivity type semiconductor substrate; and
an electrode film formation step of forming a metal electrode film by sputtering on the one main surface of the first conductivity type semiconductor substrate and carrying out heat treatment,
wherein selenium or sulfur for forming the first conductivity type field-stop layer, phosphorus for forming the first conductivity type buffer layer, and boron for forming the second conductivity type collector layer are sequentially ion implanted as a plurality of the dopant in the implantation step, and
the plurality of the dopant are simultaneously activated by the heat treatment in the activation step,
wherein the implantation step and activation step are carried out so that the net doping concentration of the first conductivity type field-stop layer is higher than the net doping concentration of the first conductivity type drift layer, the depth of the first conductivity type field-stop layer is 20 μm or more, the impurity concentration distribution of the first conductivity type field-stop layer has a concentration gradient that decreases from the other main surface side of the first conductivity type semiconductor substrate toward the one main surface side, and the maximum impurity concentration of the first conductivity type buffer layer is higher than the maximum impurity concentration of the first conductivity type field-stop layer at 6×1015 cm−3 or more, and one-tenth or less of the maximum impurity concentration of the second conductivity type collector layer.