US 9,812,560 B2
Field effect transistor and method for manufacturing the same
Yasuhiko Takemura, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken (JP)
Filed on Nov. 17, 2014, as Appl. No. 14/542,705.
Application 14/542,705 is a continuation of application No. 13/114,634, filed on May 24, 2011, granted, now 8,895,375.
Claims priority of application No. 2010-125443 (JP), filed on Jun. 1, 2010.
Prior Publication US 2015/0072471 A1, Mar. 12, 2015
Int. Cl. H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/385 (2006.01); H01L 21/477 (2006.01); H01L 27/13 (2006.01)
CPC H01L 29/66969 (2013.01) [H01L 21/02266 (2013.01); H01L 21/02565 (2013.01); H01L 21/02614 (2013.01); H01L 21/385 (2013.01); H01L 21/477 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H01L 29/242 (2013.01); H01L 29/7869 (2013.01); H01L 27/13 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for manufacturing an electronic device, comprising steps of:
forming a first conductive film over a substrate;
forming a first insulating film over the first conductive film;
forming a first insulating layer and a first conductive layer;
forming a semiconductor layer over and in contact with the first insulating layer and a second insulating layer over the semiconductor layer;
after forming the second insulating layer, etching the semiconductor layer so that the semiconductor layer does not overlap with any side edge of the first conductive layer;
forming a third insulating layer over the second insulating layer;
providing an opening reaching the semiconductor layer in the second insulating layer and the third insulating layer; and
forming a second conductive layer covering the opening.