| US 9,812,559 B2 | ||
| FINFET semiconductor devices and method of forming the same | ||
| Kyung-In Choi, Seoul (KR); Bong-Soo Kim, Hwaseong-si (KR); Hyun-Seung Kim, Bucheon-si (KR); and Hyun-Gi Hong, Seongnam-si (KR) | ||
| Assigned to Samsung Electronics Co., Ltd., (KR) | ||
| Filed by Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (KR) | ||
| Filed on Aug. 15, 2016, as Appl. No. 15/236,726. | ||
| Claims priority of application No. 10-2015-0124728 (KR), filed on Sep. 3, 2015. | ||
| Prior Publication US 2017/0069737 A1, Mar. 9, 2017 | ||
| Int. Cl. H01L 29/66 (2006.01); H01L 21/225 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01) | ||
| CPC H01L 29/66803 (2013.01) [H01L 21/02175 (2013.01); H01L 21/02244 (2013.01); H01L 21/02252 (2013.01); H01L 21/2255 (2013.01); H01L 21/2256 (2013.01); H01L 29/0847 (2013.01); H01L 29/66492 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01)] | 19 Claims |
| 1. A method of fabricating a semiconductor device, the method comprising:
forming an active fin extending along a first direction;
forming a field insulating layer exposing an upper part of the active fin, along long sides of the active fin;
forming a dummy gate pattern extending along a second direction intersecting the first direction, on the active fin;
forming a spacer on at least one side of the dummy gate pattern;
forming a liner layer covering the active fin exposed by the spacer and the dummy gate pattern;
forming a dopant supply layer containing a dopant element, on the liner layer; and
forming a doped region in the active fin along an upper surface of the active fin by heat-treating the dopant supply layer.
|